JP2010045309A - Exposure method, and method of manufacturing semiconductor device - Google Patents

Abstract

An optimal exposure condition for a mask pattern is determined by considering a hot spot together with the appearance frequency of a device pattern, and a chip performance as close as possible to a target is obtained.
A multiplication value of a square of a difference between a dimension of a predetermined device pattern under a predetermined exposure condition and a target value thereof and an appearance frequency of the device pattern is calculated for each device pattern, and the sum of the multiplication values is calculated. Is determined as the first term of the evaluation function, a limit exposure condition that may cause a disconnection or a short circuit in the device pattern is specified, and a function whose value is sufficiently large below the limit exposure condition and above the limit exposure condition is And the optimum exposure condition is determined based on the condition that the sum of the first to third terms of the evaluation function is minimized.
[Selection] Figure 4

Description

  The present invention relates to an exposure method for forming a device pattern by exposing and transferring a mask pattern of a photomask onto a substrate, and a method for manufacturing a semiconductor device.

  In manufacturing a semiconductor device, a mask pattern of a photomask is exposed and transferred to a resist film formed on a thin film such as an insulating film or a conductive film on a semiconductor substrate, and a resist pattern is formed through development. Then, using this resist pattern as a mask, the thin film is etched to form a device pattern having a shape following the resist pattern.

In order to satisfy the electrical characteristics required for the semiconductor device, the dimensional variation of the resist pattern transferred onto the semiconductor substrate must be within a certain range. For example, the dimensional variation of the gate (gate pattern) of the transistor causes variations in the threshold voltage of the transistor, and thus the dimensional variation of the resist pattern when forming the gate pattern needs to be within a certain range.
The resist pattern changes depending on the exposure energy and the focus correction value. Here, the exposure energy is the energy amount of exposure light applied to the photosensitive resin resist film. The focus correction value is a correction value by wafer stage correction driving in a direction perpendicular to the projection lens surface (based on a point recognized by the focus sensor built in the exposure apparatus as the best focus). In order to control the dimension of the resist pattern, the exposure energy and the focus correction value are used as control factors.

Conventionally, as in Patent Document 1, for example, an exposure energy and a focus correction value are set by an exposure condition determination experiment.
In this method, first, an experimental substrate on which exposure processing is performed by changing the exposure energy and the focus correction value for each step shot is manufactured. Then, the dimension and shape of the resist pattern at each exposure energy and focus correction value are measured by a dimension measuring device. Examples of the dimension measuring device include a scanning electron microscope (SEM) and an optical measuring device based on analysis of scattered light of a periodic pattern. The dimension of the resist pattern measured at this time is called a CD (Critical Dimension) value.
Next, for each measurement point, among the measured CD value and shape, a range of exposure energy and focus correction value that are within a certain range from the standard is obtained, and a window called a process window is created. For each measurement point, for example, the center of gravity of the window is set as an exposure energy setting value and a focus correction value setting value, respectively.

  Such an exposure condition setting operation based on an experiment for determining the exposure condition includes reticle individual differences and process conditions between exposure processes (for example, a film configuration of a semiconductor device and an illumination condition of an illumination optical system of an exposure apparatus (a reduction lens aperture)). This is performed when the reticle, the exposure process, and the exposure apparatus change due to the influence of the difference in the number NA and illumination coherency (σ) and the like and the machine difference between the exposure apparatuses.

  The resist pattern whose CD value is measured using an experimental substrate is usually an evaluation pattern designed in advance for dimensional management in the lithography process and the etching process. Generally, an isolated pattern and a fine pattern are used as the evaluation pattern. An isolated pattern is a pattern in which the smallest pattern (allowed by mask design rules) existing in a semiconductor circuit is laid out in isolation. A fine pattern is laid out in an array at a fine pitch.

  The reason why an isolated pattern and a fine pattern are used for the evaluation pattern is that these two patterns have the most extreme characteristics of other intermediate pitch patterns, both in terms of optical characteristics and layout. Therefore, it can be said that keeping the dimensions of these two types of patterns within a certain value may lead to the management of the dimensions of patterns having other intermediate properties. In addition, these two types of patterns are often the most sensitive to exposure and focus fluctuations, which are dimensional fluctuation factors, and may be considered to have characteristics necessary for the management pattern.

Japanese Patent Laid-Open No. 2003-257838 Mary Jane Brodsky, Scott Halle, Vickie Jophlin-Gut, Lars Liebmann, Don Samuels, Gary Crispo, Kourosh Nafisi, Vijay Ramani, and Ingrid Peterson, "Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub -wavelength era ", Proc. SPIE 5756, 51 (2005) Yongfa Huang, Edward Tseng, Benjamin Szu-Min Lin, Chun Chi Yu, Chien-Ming Wang, and Hua-Yu Liu, "Full-chip lithography manufacturability check for yield improvement", Proc.SPIE 6156, 61560W (2006)

Although the conventional use of the evaluation pattern is reasonable from the viewpoint of the exposure technique, there is a problem that it is not necessarily optimal when the actual state of the device pattern to be actually formed is taken into consideration.
FIG. 1 is a characteristic diagram in which the frequency of appearance of an inter-pattern space is plotted against the space for a so-called standard cell gate pattern. In FIG. 1, the horizontal axis is normalized by the minimum space allowed by the photomask design rule, and 1 corresponds to the minimum pitch pattern. 2, 3, 4, 5, and 6 correspond to spaces when the layout shown in FIG. 1 is drawn with the minimum rule allowed by the mask design rule.

  As is clear from FIG. 1, as a matter of fact, the appearance frequency of the fine pitch pattern is not so high. Further, for miniaturization of a semiconductor chip, it is desirable that the gate interval is small, and there should not be so many gate patterns such as evaluation patterns that are isolated on both the left and right sides. In order to bring the chip performance close to the target value (target value), it is considered essential that the size and shape of the majority of gates in the semiconductor chip are close to the target value. However, in the conventional evaluation pattern, the appearance frequency is not taken into consideration, and a high chip performance close to the target value cannot always be obtained.

In addition, due to the recent miniaturization of device patterns that have been proceeding at an accelerated rate, the process margin becomes smaller depending on the two-dimensional pattern arrangement, causing hot breaks that can cause disconnection or short-circuiting and reduce yield. Spots (hotspots) have become a problem.
Therefore, in order to determine the optimal exposure conditions for the mask pattern, it is essential to consider hot spots in addition to the appearance frequency of the device pattern. At present, such an exposure method has been devised. It has not been.

  This case has been made in view of the above-mentioned problems.The optimum exposure condition for the mask pattern is determined by considering hot spots together with the appearance frequency of the device pattern, and chip performance as close as possible to the target value is achieved. An object of the present invention is to provide a highly reliable exposure method and apparatus that can be obtained, and a method for manufacturing a semiconductor device.

  The exposure method according to the present invention, when determining the optimum exposure conditions for forming a plurality of types of device patterns, squares the difference between the dimensions of the predetermined device pattern and the target value under the predetermined exposure condition, A step of calculating a multiplication value with the appearance frequency of each pattern for each device pattern, and obtaining a sum of the multiplication values as the first term of the evaluation function, and a limit that may cause a disconnection or a short circuit in the device pattern A step of specifying an exposure condition, a step of obtaining a function whose value is sufficiently large below the limit exposure condition and above the limit exposure condition as the second and third terms of the evaluation function, and the evaluation function Determining the optimum exposure condition based on a condition that the sum of the first term, the second term, and the third term is minimized.

  The exposure apparatus of the present case is an exposure apparatus that determines optimum exposure conditions for forming a plurality of types of device patterns, and is a difference between a CD value corresponding to a predetermined device pattern under a predetermined exposure condition and its target value. A first calculation unit that calculates a multiplication value of the square of the value and the appearance frequency of the device pattern for each device pattern, and obtains a sum of the multiplication values as a first term of the evaluation function; Based on the limit exposure conditions that may cause a disconnection or a short circuit in the pattern, functions that are sufficiently large below the limit exposure conditions and above the limit exposure conditions are the second and third terms of the evaluation function. And an exposure condition that determines the optimum exposure condition based on a condition that minimizes the sum of the first term, the second term, and the third term of the evaluation function. And a determination unit.

  The method of manufacturing a semiconductor device according to the present invention includes a first step of exposing and transferring a mask pattern of a photomask onto a resist on a semiconductor substrate to form a resist pattern, and a device pattern on the semiconductor substrate using the resist pattern. A second step of forming a plurality of device patterns, wherein the first step determines the optimum exposure conditions for forming a plurality of types of device patterns, and the predetermined dimensions of the device patterns under predetermined exposure conditions; Calculating a square value of the difference between the target value and the appearance frequency of the device pattern for each device pattern, and obtaining a sum of the multiplication values as a first term of the evaluation function; A step of identifying a limit exposure condition that may cause a disconnection or a short circuit in the device pattern; and a step below the limit exposure condition and the limit exposure A step of obtaining a function whose value is sufficiently large above the condition as the second and third terms of the evaluation function, and the sum of the first, second, and third terms of the evaluation function is minimum And determining the optimum exposure condition based on the following condition.

  According to the present case, it is possible to determine the optimum exposure condition of the mask pattern with the appearance frequency of the device pattern and the hot spot as considerations, and obtain a chip performance as close as possible to the target value.

―Basic outline of this case―
In this case, a new evaluation function f for determining the optimum exposure condition is introduced with the appearance frequency of the device pattern as a consideration and hot spots (FIG. 2).

In the equation (1), Pi is an appearance probability (appearance frequency) of the i-th resist pattern i (i = 1, 2,...) In the semiconductor chip among a plurality of types of resist patterns. ΔCDi is a deviation from the target value in the condition x of the resist pattern i, and x is an exposure condition such as an exposure amount and a focus value.
Accordingly, the first term of the expression (1) represents the dispersion when the target value when exposed under the condition x is used as a reference. The smaller this value, the more the average pattern size of the semiconductor chip becomes the target. Approaching the value.

The second and third terms of equation (1) are terms necessary to ensure that no disconnection or short-circuit occurs within the range of exposure conditions that can occur during mass production from the determined optimum conditions.
Exposure conditions that may cause disconnection or short-circuiting in the device pattern corresponding to the resist patterns j, k (j, k = 1, 2,...) Serving as hot spots are set to xj or more and xk or less. When there is an optimum condition between the exposure condition fluctuation amount δ that can occur during mass production from the hot spot, a disconnection or a short circuit occurs with a certain probability. Therefore, in f (x) of the equation (1), outside the position shifted by δ from xj and xk so that the optimum condition is not located between δ from the exposure condition that may cause disconnection or short circuit. An ∞ × θ function with an infinite value is added as the second and third terms. The dimension average value of the device pattern in the semiconductor chip is closest to the target value as long as the exposure condition in which f (x) in Equation (1) is minimum does not cause disconnection or short-circuit during mass production due to hot spots. The optimum exposure condition is as follows.

-Preferred embodiments to which this case is applied-
Hereinafter, specific embodiments to which the present application is applied will be described in detail with reference to the drawings.

(First embodiment)
In this embodiment, a case where, for example, a gate pattern is formed as a device pattern will be described. The exposure conditions optimized in this embodiment are an exposure amount and a focus value.

In the present embodiment, as shown in FIG. 5, among the device patterns permitted by the mask design rule, in addition to the narrowest gate isolated pattern and fine line & space pattern, there are three contact pitch patterns. Is newly added as an evaluation pattern. The contact pitch pattern is a gate pattern in a case where contacts are arranged between two gates in a minimum space allowed by the mask design rule.
FIG. 6 is a characteristic diagram showing the results of examining the appearance frequency of each device pattern in a certain semiconductor chip. It can be seen that the contact pitch pattern is used about five times as often as the fine pattern and twice as often as the isolated pattern.

[Schematic configuration of exposure apparatus]
FIG. 3 is a schematic diagram showing a schematic configuration of the exposure apparatus according to the first embodiment.
In this exposure apparatus, light emitted from a light source 11 such as an excimer laser is formed into slit-shaped exposure light optimal for exposure by an illumination optical system 12 to illuminate a pattern surface formed on the surface of the photomask 10. To do. A mask pattern corresponding to an IC circuit to be exposed is formed on the pattern surface of the photomask 10, and the exposure light transmitted through the mask pattern passes through the projection optical system 14 and is formed on the surface of the semiconductor substrate 20. An image is formed to form a pattern image.

  Here, the photomask 10 is placed on a mask stage 13 capable of reciprocating scanning in a predetermined direction. Further, the semiconductor substrate 20 is placed on a wafer stage 15 that can be driven in a predetermined direction and that can correct a tilt.

  The shot area on the photomask 10 is exposed by relatively scanning the mask stage 13 and the wafer stage 15 at the speed of the ratio of the exposure magnification. After the end of one-shot exposure, the wafer stage 15 moves stepwise to the next shot area, scanning exposure is performed in the opposite direction to the previous shot area, and the next shot area is exposed. Such an operation is called step-and-scan. By repeating this operation, shot exposure is performed on the entire area of the semiconductor substrate 20.

Reference numeral 10 denotes a control unit that performs overall control of the exposure apparatus.
The control unit 10 includes a first term calculation unit 21 and a second term calculation unit 22 that determine optimum exposure conditions for forming a plurality of types of device patterns, here isolated patterns, fine patterns, and contact pitch patterns. The third term calculation unit 23, the evaluation function determination unit 24, and the exposure condition determination unit 25 are connected.

The 1st term calculation part 21 calculates the 1st term of the evaluation function shown by said (1) Formula. Specifically, the multiplication value of the square of the difference between the dimension of the evaluation pattern under a predetermined exposure condition and its target value and the appearance frequency of the evaluation pattern is calculated for each evaluation pattern, and the sum of the multiplication values is calculated. Obtained as the first term of the evaluation function.
The second term calculation unit 22 calculates a function whose value becomes sufficiently large above the limit exposure condition with respect to the limit exposure condition specified as the possibility that disconnection or short circuit may occur in the evaluation pattern. Is what you want.
The third term calculation unit 23 obtains a function whose value is sufficiently large under the limit exposure condition as the third term of the evaluation function.

The evaluation function determination unit 24 indicates the exposure condition dependence of the obtained evaluation function based on the calculated first, second, and third terms.
The exposure condition determination unit 25 determines a condition that minimizes the sum of the first, second, and third terms of the evaluation function as the optimum exposure condition.

[Exposure setting method]
FIG. 4 is a flowchart showing the exposure setting method according to the first embodiment in the order of steps.
First, as shown in FIG. 6, for example, the frequency of appearance of mask patterns corresponding to isolated patterns, fine patterns, and contact pitch patterns, which are evaluation patterns, is investigated (step S1).
Subsequently, using a photomask including a mask pattern corresponding to an evaluation pattern of an isolated pattern, a fine pattern, and a contact pitch pattern, a resist pattern is formed on the semiconductor substrate by varying (changing) the exposure amount and the focus (step) S2).

Subsequently, the CD value of the resist pattern corresponding to the evaluation pattern is measured using, for example, a scanning electron microscope (SEM) (step S3).
FIG. 7 is a characteristic diagram showing the relationship between the measured CD value and the focus value set in the exposure apparatus. Since the three types of evaluation patterns have different degrees of dimensional variation due to focus, it can be seen that the curvature of each convex curve is different. It can also be seen that the optimum focus value at which the inclination is 0 with respect to the focus variation is slightly different depending on the evaluation pattern.
FIG. 8 is a characteristic diagram showing the dependency of the CD value on the exposure amount when the focus value on the setting of the exposure apparatus is 0 nm and ± 40 nm. In any evaluation pattern, the target value is 70 nm, but the dimension of 70 nm is not obtained with the same exposure amount. This is due to incomplete optical proximity effect correction (OPC) (including the OPC model), deviation of the mask pattern dimension from the target value, slight pattern-dependent changes in dimensions due to differences in resist lots, etc. It is caused by this.

Subsequently, the first term calculation unit 21 calculates the first term of the evaluation function expressed by the above equation (1) (step S4).
The first term of the evaluation function for each exposure dose and each focus value matrix, ie,

FIG. 9 shows the result obtained. It can be seen that the minimum value is 1 when the focus value is −40 nm or −80 nm and the exposure amount is 19.5 mJ / cm ² .

Subsequently, the range of exposure conditions that may cause disconnection or short-circuit at the hot spot occurrence location is estimated (step S5). There are several possible methods. For example, Process Window Qualification (PWQ) of Non-Patent Document 1 can be used as one of methods for experimentally estimating exposure conditions that may cause disconnection / short circuit.
In PWQ, a semiconductor chip exposed under optimum exposure conditions and a semiconductor chip manufactured under different exposure conditions are compared and inspected using a DUV wavelength bright field defect inspection apparatus. It is possible to identify a place that is likely to change. By observing the specific portion with, for example, an SEM, an exposure condition in which each device pattern is disconnected or short-circuited is determined.

Further, for example, using Non-Patent Document 2, it is also possible to estimate exposure conditions that cause disconnection or short-circuit by simulation.
Conventionally, full-chip simulation has been unrealistic because it took a long calculation time, but by using dedicated hardware, simulation under a plurality of exposure conditions is possible.
FIG. 10 is a diagram showing a result of extracting a hot spot by performing a simulation under the same exposure conditions as those for measuring the CD value.
In the device pattern obtained by the simulation, the case where both the pattern width and the space width were less than 35 nm was defined as a hot spot with a possibility of disconnection or short circuit. In FIG. 10, the exposure conditions with a checkerboard pattern are exposure conditions that may cause a disconnection or a short circuit.

  Subsequently, the second term calculation unit 22 and the third term calculation unit 23 calculate the second and third terms of the evaluation function expressed by the above equation (1), that is,

Is calculated (step S6).
First, the fluctuation width of the exposure condition that can occur during mass production is obtained from the specifications of the exposure apparatus, the length measurement result of the management pattern, and the like. It is not essential to use this technique for this case, but FIG. 11 shows an example in which the touch width of exposure conditions that can occur during mass production is obtained from the specifications of the exposure apparatus. The specifications are 1% for the overall exposure accuracy and 80 nm for the focus accuracy. From the conditions for generating hot spots shown in FIG. 10 with hot spots + unexamined conditions (conditions exceeding the survey range), the conditions of this spec range (locations with a sand pattern in FIG. 12) Add infinity to the evaluation function. Since it is difficult to handle infinity in the actual calculation, a sufficiently large value compared to the first term, which is 10,000 in the present embodiment, is added.

Subsequently, the evaluation function determination unit 24 obtains the dependency of the obtained evaluation function on the exposure condition based on the calculated first, second, and third terms (step S7).
FIG. 13 shows the exposure condition dependence of the evaluation function obtained in step S7. As shown in the figure, it can be seen that the evaluation value is very large under the condition of a certain width from the danger spot where the hot spot is generated, and the optimum condition is always obtained inside the wall.

Then, the exposure condition determination unit 25 determines the optimum exposure based on the condition that the sum total of the first term, the second term, and the third term of the evaluation function is minimum based on the dependence of the evaluation function obtained in step S7 on the exposure condition. The condition is determined (step S8).
In the present embodiment, the exposure condition that minimizes the evaluation function value is determined such that the area with the mesh pattern in the upper diagram of FIG. 13, that is, the exposure amount is 19.5 mJ / cm ² and the focus value is −40 nm. It is done.

  In the present embodiment, the case where three types of an isolated pattern, a fine pattern, and a contact pitch pattern are used as the evaluation pattern is illustrated. If there is no problem with the measurement pattern measurement time and evaluation pattern area, it is possible to determine the optimum exposure conditions in consideration of the appearance frequency and hot spots of four or more types of evaluation patterns using the method described above. It is.

[Method for Manufacturing Semiconductor Device]
In the present embodiment, a method for manufacturing a semiconductor device using the above-described exposure setting method is disclosed. Here, a MOS transistor is exemplified as the semiconductor device. Of course, the semiconductor device can be applied to a semiconductor memory other than a MOS transistor (for example, a constituent element of a ROM that is a functional block) and various semiconductor devices that are constituent elements of another functional block.
FIG. 14 is a schematic cross-sectional view showing a MOS transistor manufactured according to the first embodiment.

The method for manufacturing a semiconductor device according to the present embodiment includes a first step of exposing and transferring a mask pattern of a photomask onto a resist on a semiconductor substrate to form a resist pattern, and a device pattern on the semiconductor substrate using the resist pattern. Forming a second step.
Here, in the first step, for example, when forming a gate pattern, steps S1 to S8 of the exposure setting method described above are sequentially performed, and exposure transfer of the mask pattern is executed based on the determined optimum exposure condition. .

First, a resist pattern for element isolation is formed in the element isolation region of the silicon substrate 31 by lithography. Using this resist pattern as a mask, the semiconductor substrate is dry etched to form element isolation grooves. The resist pattern is removed by ashing or the like.
Then, an insulating film for embedding the element isolation trench, such as a silicon oxide film, is deposited by CVD or the like, and planarized by a chemical mechanical polishing (CMP) method or the like, and the inside of the element isolation trench is silicon oxide. Then, an STI (Shallow Trench Isolation) element isolation structure 32 filled with is formed.

Subsequently, after a thin insulating film, here a silicon oxide film, is formed on the silicon substrate 31 by a thermal oxidation method or the like, a polycrystalline silicon film is deposited by a CVD method or the like.
In the first step, a resist pattern for a gate is formed on the polycrystalline silicon film by lithography including an exposure step based on the determined optimum exposure condition. In the subsequent second step, the polycrystalline silicon film and the silicon oxide film are dry-etched using this resist pattern as a mask to pattern the gate electrode 34 on the silicon substrate 31 with the gate insulating film 33 interposed therebetween. The resist pattern is removed by ashing or the like.

Subsequently, using the gate electrode 34 as a mask, impurities (such as boron (B ⁺ ) in the case of P type or phosphorus (P ⁺ ) or arsenic (As ⁺ ) in the case of N type) are predetermined on the surface layer of the silicon substrate 31. The ion implantation is performed with the dose amount and the acceleration energy. As a result, extension regions 35 are formed on both sides of the gate electrode 34.

Subsequently, an insulating film, here a silicon oxide film, is deposited on the entire surface of the silicon substrate 31 including the gate electrode 34 by CVD or the like.
Then, the entire surface of the silicon oxide film is anisotropically dry etched (etched back) to leave the silicon oxide only on both sides of the gate electrode 34 and the gate insulating film 33 to form a sidewall insulating film 36.

Subsequently, using the gate electrode 34 and the sidewall insulating film 36 as a mask, impurities (such as boron (B ⁺ ) in the case of P type) or phosphorus (P ⁺ ) or arsenic (As in the case of N type) are formed on the surface layer of the silicon substrate 31. ⁺ ) Etc.) is ion-implanted with a predetermined dose and acceleration energy. As a result, source / drain regions 37 partially overlapping with the extension regions 35 are formed on both sides of the sidewall insulating film 36.

  Subsequently, an interlayer insulating film 38 is formed by depositing an insulating film, here a silicon oxide film, over the entire surface of the silicon substrate 31 by a CVD method or the like so as to fill the gate electrode 34.

Subsequently, a resist pattern for contact holes is formed on the interlayer insulating film 38 by lithography. Using this resist pattern as a mask, the interlayer insulating film 38 is dry etched to form a contact hole that exposes a part of the surface of the source / drain region 37. The resist pattern is removed by ashing or the like.
Then, a conductive material, here, tungsten (W) or the like is deposited on the interlayer insulating film 38 by a CVD method or the like so as to embed the contact hole via a predetermined glue film or the like, and is planarized by a CMP method or the like. A contact plug 39 filling the inside with W is formed.

Subsequently, a wiring material, here, an Al alloy or the like is deposited on the interlayer insulating film 38 by a sputtering method or the like.
Then, a resist pattern for contact holes is formed on the wiring material by lithography. Using this resist pattern as a mask, the wiring material is dry-etched to form a wiring 41 connected to the contact plug 39. The resist pattern is removed by ashing or the like.

  Subsequently, an insulating film, here a silicon oxide film, is deposited on the entire surface of the interlayer insulating film 38 so as to have a film thickness for embedding the wiring 41 by a CVD method or the like, thereby forming an interlayer insulating film 42.

Note that the first-layer wiring may be formed by a so-called damascene method.
Specifically, for example, after forming the interlayer insulating film 42 (the lower layer portion thereof), a resist pattern for the wiring trench is formed on the interlayer insulating film 42 by lithography using a photomask. Using this resist pattern as a mask, the interlayer insulating film 42 is dry-etched to form a wiring groove that exposes a part of the surface of the contact plug 49. The resist pattern is removed by ashing or the like.
Then, a conductive material, here copper (Cu) or Cu alloy or the like is deposited by a plating method or the like so as to fill the wiring groove, flattened by a CMP method or the like, and the wiring filling the wiring groove with Cu or Cu alloy is formed. Form.
Thereafter, an interlayer insulating film 42 (upper layer portion) is formed.

Subsequently, a resist pattern for via holes is formed on the interlayer insulating film 42 by lithography. Using this resist pattern as a mask, the interlayer insulating film 42 is dry-etched to form a via hole exposing a part of the surface of the wiring 41. The resist pattern is removed by ashing or the like.
Then, a conductive material, here copper (Cu) or a Cu alloy or the like is deposited by a plating method or the like so as to embed a via hole through a predetermined glue film or the like, and is planarized by a CMP method or the like, and the wiring trench is filled with Cu. Alternatively, a via plug 43 filled with a Cu alloy is formed.

Subsequently, a wiring material, here, an Al alloy or the like is deposited on the interlayer insulating film 42 by sputtering or the like.
Then, a resist pattern for contact holes is formed on the wiring material by lithography. Using this resist pattern as a mask, the wiring material is dry-etched to form a wiring 44 connected to the via plug 43. The resist pattern is removed by ashing or the like.
Note that the second-layer wiring may be formed by a damascene method as in the first-layer wiring.

Subsequently, an interlayer insulating film 45 is formed by depositing an insulating film, here a silicon oxide film, over the entire surface of the interlayer insulating film 42 so as to have a film thickness for embedding the wiring 44 by a CVD method or the like.
Thereafter, a further upper layer wiring and an interlayer insulating film are formed to complete the MOS transistor.

  In the above example, the case where the exposure setting method of the present embodiment is applied to the formation of the resist pattern when forming the gate electrode 34 is illustrated, but the resist pattern when forming the wirings 41, 44 and the like is illustrated. The exposure setting method of this embodiment may be applied to the formation.

As described above, according to the present embodiment, the optimum exposure condition of the mask pattern is determined in consideration of the hot spot as well as the appearance frequency of the device pattern, and the chip performance as close as possible to the target value is obtained. Is possible.
Then, by determining the optimum exposure condition and exposing the mask pattern in this way, a highly reliable semiconductor device is realized.

(Second Embodiment)
In this embodiment, exposure conditions are set in the same manner as in the first embodiment. However, vertical and horizontal patterns (evaluation patterns extending in the vertical direction and evaluation extending in the horizontal direction on the exposed surface) are used as evaluation patterns. Pattern) is considered.

For example, the ratio of the pattern extending in the vertical direction (vertical pattern) to the pattern extending in the horizontal direction (horizontal pattern) of the gate pattern laid out on a certain semiconductor chip is investigated. In the semiconductor chip used for the sample of this embodiment, the ratio of the vertical pattern was 0.88, and the ratio of the horizontal pattern was 0.12.
In this embodiment, there are four types of evaluation patterns: a vertical pattern fine pattern and an isolated pattern, and a horizontal pattern fine pattern and an isolated pattern.

And like 1st Embodiment, after performing step S1-S3 sequentially, in step S4, the 1st term of the evaluation function shown by said (1) Formula is calculated. Here, in Pi, the vertical pattern is fine and the isolated pattern is 0.88 / 2, and the horizontal pattern is fine and the isolated pattern is 0.12 / 2. The reason why the appearance frequency is divided by 2 is that the evaluation patterns are sparse and dense in consideration of two types.
Then, similarly to the first embodiment, steps S5 to S8 are sequentially performed to determine optimum exposure conditions.

According to the present embodiment, the optimal exposure condition of the mask pattern is determined for the hot spot as well as the appearance frequency of the device pattern considering the vertical pattern and the horizontal pattern, and the chip performance as close as possible to the target value is achieved. Can be obtained.
Then, by determining the optimum exposure condition and exposing the mask pattern in this way, a highly reliable semiconductor device is realized.

(Third embodiment)
It may be difficult to lay out a large number of evaluation patterns in advance in a semiconductor chip, and the measurement of exposure dose and focus dependency for determining the conditions requires a sufficient amount of time to ship the product quickly. In many cases, it cannot be hung. In the present embodiment, a method for determining the optimum exposure condition in consideration of the deviation from the target value that is known in advance and the appearance frequency of the evaluation pattern corresponding to each device pattern will be described.

FIG. 15 is a flowchart showing the exposure setting method according to the third embodiment in order of steps.
Here, for convenience of explanation, the focus value is not considered as the exposure condition, and only the exposure amount is targeted.
First, an OPC residue and EL (Exposure Latitude) are examined in advance for many resist patterns using a dedicated mask for examining exposure characteristics of resist patterns having various pitches (steps S11 and S12). Here, the OPC residue is a technique for obtaining a desired pattern shape by changing the mask shape in accordance with the peripheral pattern by shifting the pattern from the target due to the proximity effect, which is called OPC (Optical Proximity Correction). In spite of the above, the correction grid, the incompleteness of the OPC model, the deviation of the mask pattern dimension from the target value, the deviation from the target dimension caused by the difference in resist lot, and the like. Further, EL is a ratio of exposure amount fluctuation that causes a CD value fluctuation of 10%. An example of this investigation is shown in FIG.
The exposure amount for obtaining the OPC residue is determined by examining the optimum exposure condition obtained from a conventional method (an array of isolated patterns and fine patterns), and the dependency on the exposure amount, with the optimum exposure condition as a center.

  Subsequently, when the actual device pattern is entered, the appearance frequency in the actual device pattern is obtained for the resist pattern for which the OPC residue or the like has been obtained (step S13). An example of this investigation is shown in FIG.

Subsequently, as in the first embodiment, the first term calculation unit 21 calculates the first term of the evaluation function represented by the above equation (1) (step S14).
In the present embodiment, ΔCD _i (ΔDose) is calculated using the previously obtained OPC residue and EL,
ΔCD _i (ΔDose) = OPC residue _i + {0.2 × TargetCD _i / EL _i } ΔDose
Can be obtained as follows. Here, the OPC residue _i , TargetCD _i , and EL _i are the i-th OPC residue, CD target value, and EL. Therefore, the first term of the evaluation function is as shown in FIG. 18, and it can be seen that the minimum value is obtained when the exposure amount is -0.37%.

Subsequently, as in step S5 of the first embodiment, an exposure amount at which the pattern may be disconnected or short-circuited is obtained (step S15).
Subsequently, similarly to step S6 of the first embodiment, the second term calculation unit 22 and the third term calculation unit 23 calculate the second term and the third term of the evaluation function from the range of the exposure amount fluctuation that can occur during mass production. Is obtained (step S16).
Subsequently, as in step S7 of the first embodiment, the evaluation function determination unit 24 obtains the dependence of the obtained evaluation function on the exposure condition based on the calculated first, second, and third terms. (Step S17).

Subsequently, the exposure condition determination unit 25 determines the optimum exposure amount that minimizes the sum of the first, second, and third terms of the evaluation function based on the exposure condition dependency of the evaluation function obtained in step S17. The percentage is determined (step S18).
Then, the exposure condition determination unit 25 calculates a value obtained by correcting the optimum exposure amount obtained by the conventional method (steps S19 to S21) by the percentage of the optimum exposure amount determined in step S18 as the optimum condition. (Step S22).
Here, in steps S19 to S21, the evaluation pattern is an isolated pattern and a fine pattern, and a resist pattern is formed on the semiconductor substrate by changing (changing) the exposure amount and focus, and the CD value of the resist pattern corresponding to the evaluation pattern Is measured using, for example, an SEM, and a set value of the exposure condition is calculated.

In the present embodiment, the case where only the exposure amount is used as the exposure condition is illustrated. However, when the exposure condition is the exposure amount and the focus value, for example (for each pattern, DOF (Depth of focus: 10% CD fluctuation) The amount of defocusing that causes the image is measured in advance, and ΔCD _i (ΔDose, ΔFocus) is calculated using the previously obtained OPC residue, EL, and DOF.
ΔCD _i (ΔDose, ΔFocus)
= OPC residue _i + {0.4 × TargetCD _i / DOF _i ² } ΔFocus ²
+ {0.2 × TargetCD _i / EL _i } ΔDose
You can ask.

As described above, according to the present embodiment, the optimum exposure condition for the mask pattern is determined as much as possible to the target value, considering the hot spot together with the appearance frequency of the device pattern in a simpler and shorter time. It is possible to obtain a chip performance close to.
Then, by determining the optimum exposure condition and exposing the mask pattern in this way, a highly reliable semiconductor device is realized.

(Fourth embodiment)
In this embodiment, in addition to the case of the third embodiment, when the average dimension of the newly entered mask pattern is smaller than the target value (for example, when it is smaller by about 2 nm), A method for obtaining the optimum exposure amount will be described.
FIG. 19 is a flowchart showing the exposure setting method according to the fourth embodiment in the order of steps.

When the average value of the mask pattern dimension is small, MEEF (Mask Error Enhancement Factor: the ratio indicating the amount of change in the resist pattern dimension when the mask pattern dimension differs by the unit amount) differs depending on the resist pattern. Therefore, not only the OPC residue moves in parallel to the minus side, but also the overall dependence changes (FIG. 20).
In order to determine the optimum exposure conditions while taking into account the difference in MEEF depending on the resist pattern, it is necessary to measure the MEEF of the resist pattern in advance using a dedicated photomask in addition to the OPC residue and EL. (FIG. 21).

That is, in this embodiment, after performing step S11 in the third embodiment, instead of step S12, in step S31, the MEEF of the resist pattern is measured in addition to the OPC residue and EL.
The OPC residue when there is a mask pattern average value deviation is a value obtained by adding the original OPC residue to the MEEF of each pattern multiplied by the mask pattern average value deviation. Therefore, in step S14, ΔCD _i (ΔDose) is
ΔCD _i (ΔDose)
= OPC residue _i + MEEF _i × ΔMask + {0.2 × TargetCD _i / EL _i } ΔDose
Can be obtained as follows. Accordingly, the first term of the evaluation function is as shown in FIG. 22, and it can be seen that the minimum value is obtained when the exposure amount is 1.1%.
Then, similarly to the third embodiment, steps S13 to S22 are sequentially executed to determine the optimum condition.

Further, in the fourth embodiment, when the inter-pattern difference of the dimensional deviation of the mask pattern is known, the first term of the evaluation function may be obtained in consideration of the inter-pattern difference. In that case,
ΔCD _i (ΔDose)
= OPC residue _i + MEEF _i × ΔMask _i + {0.2 × TargetCD _i / EL _i } ΔDose
The formula that takes into account the pattern dependence of ΔMask is used. Here, ΔMask of the i-th device pattern is ΔMask _i .

As described above, according to the present embodiment, the optimum exposure condition for the mask pattern is determined as much as possible to the target value, considering the hot spot together with the appearance frequency of the device pattern in a simpler and shorter time. It is possible to obtain a chip performance close to.
Then, by determining the optimum exposure condition and exposing the mask pattern in this way, a highly reliable semiconductor device is realized.

  In addition, about the above-mentioned 1st-4th embodiment, you may use the value which performed some reweighting or took the logarithm, without using the appearance frequency of a device pattern as it is. Further, the appearance frequency of the device pattern may not be obtained for each semiconductor chip, but may be obtained from, for example, a general-purpose macro or standard cell, and the value may be used as a representative appearance frequency of various semiconductor chips.

  Also in the third and fourth embodiments, the second embodiment may be applied. That is, in step S13, when the appearance frequency in the actual device pattern is obtained for the resist pattern for which the OPC residue or the like is obtained, the appearance frequency may be obtained in consideration of the vertical pattern and the horizontal pattern. .

(Other embodiments)
The first term calculation unit 21, the second term calculation unit 22, the third term calculation unit 23, the evaluation function determination unit 24, and the exposure conditions, which are components of the exposure apparatus according to the above-described embodiment, here the exposure apparatus of FIG. The functions of the determination unit 25 and the like can be realized by operating a program stored in a RAM or ROM of a computer. Similarly, each step of the exposure setting method (steps S1 to S8 in FIG. 4, steps S11 to S22 in FIG. 15, steps S11, S31, S13 to S22 in FIG. 19, etc.) is stored in the RAM or ROM of the computer. It can be realized by running the program. This program and a computer-readable storage medium storing the program are included in the present invention.

  Specifically, the program is recorded on a recording medium such as a CD-ROM or provided to a computer via various transmission media. As a recording medium for recording the program, besides a CD-ROM, a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk, a nonvolatile memory card, or the like can be used. On the other hand, as the program transmission medium, a communication medium in a computer network system for propagating and supplying program information as a carrier wave can be used. Here, the computer network is a WAN such as a LAN or the Internet, a wireless communication network, or the like, and the communication medium is a wired line such as an optical fiber or a wireless line.

  Further, the program included in the present invention is not limited to the one in which the functions of the above-described embodiments are realized by the computer executing the supplied program. For example, such a program is also included in the present invention when the function of the above-described embodiment is realized in cooperation with an OS (operating system) or other application software running on the computer. Further, when all or part of the processing of the supplied program is performed by the function expansion board or function expansion unit of the computer and the functions of the above-described embodiment are realized, the program is also included in the present invention.

  For example, FIG. 23 is a schematic diagram illustrating an internal configuration of a personal user terminal device. In FIG. 23, reference numeral 1200 denotes a personal computer (PC) provided with a CPU 1201. The PC 1200 executes device control software stored in the ROM 1202 or the hard disk (HD) 1211 or supplied from the flexible disk drive (FD) 1212. The PC 1200 generally controls each device connected to the system bus 1204.

  According to the program stored in the CPU 1201 of the PC 1200, the ROM 1202 or the hard disk (HD) 1211, steps S1 to S8 in FIG. 4, steps S11 to S22 in FIG. 15, and steps S11, S31, and S13 to S22 in FIG. Procedures are realized.

  Reference numeral 1203 denotes a RAM which functions as a main memory, work area, and the like for the CPU 1201. A keyboard controller (KBC) 1205 controls instruction input from a keyboard (KB) 1209, a device (not shown), or the like.

  Reference numeral 1206 denotes a CRT controller (CRTC), which controls display on a CRT display (CRT) 1210. Reference numeral 1207 denotes a disk controller (DKC). The DKC 1207 controls access to a hard disk (HD) 1211 and a flexible disk (FD) 1212 that store a boot program, a plurality of applications, an editing file, a user file, a network management program, and the like. Here, the boot program is a startup program: a program for starting execution (operation) of hardware and software of a personal computer.

  Reference numeral 1208 denotes a network interface card (NIC) that exchanges data bidirectionally with a network printer, another network device, or another PC via the LAN 1220.

  Hereinafter, various aspects of the present case will be collectively described as additional notes.

(Appendix 1) When determining the optimum exposure conditions for forming a plurality of types of device patterns,
A multiplication value of the square of the difference between the predetermined dimension of the device pattern under a predetermined exposure condition and its target value and the appearance frequency of the device pattern is calculated for each device pattern, and the sum of the multiplication values As a first term of the evaluation function;
Identifying a limit exposure condition that may cause a disconnection or a short circuit in the device pattern; and
Obtaining a function having a sufficiently large value below the limit exposure condition and above the limit exposure condition as the second and third terms of the evaluation function;
And determining the optimum exposure condition based on a condition that minimizes the sum of the first term, the second term, and the third term of the evaluation function.

(Additional remark 2) The process of carrying out exposure formation of various evaluation patterns by the said several exposure conditions,
Further measuring the dimension of each evaluation pattern,
In the step of obtaining the first term of the evaluation function, a square of a difference between a dimension of a predetermined evaluation pattern under a predetermined exposure condition and a target value thereof, and an appearance frequency of a device pattern corresponding to the evaluation pattern A multiplication value is calculated for each evaluation pattern, and the sum of the multiplication values is the first term,
2. The exposure method according to appendix 1, wherein a condition that minimizes the sum of the first term, the second term, and the third term of the evaluation function is the optimum exposure condition.

  (Supplementary Note 3) In the step of obtaining the first term of the evaluation function, the difference between the predicted dimension and its target value is determined using a predetermined predicted dimension of the device pattern under a predetermined exposure condition. 2. The exposure method according to appendix 1, wherein a multiplication value of the square and the appearance frequency of the device pattern is calculated for each device pattern, and a sum of the multiplication values is the first term.

  (Supplementary note 4) The exposure method according to supplementary note 3, wherein MEEF is added to the predetermined predicted size.

  (Appendix 5) The various device patterns include the device pattern extending in the vertical direction and the device pattern extending in the horizontal direction on the exposed surface. 5. The exposure method according to any one of 4 above.

(Appendix 6) An exposure apparatus for determining optimum exposure conditions when forming a plurality of types of device patterns,
A multiplication value of the square of the difference value between the CD value corresponding to the predetermined device pattern under a predetermined exposure condition and its target value and the appearance frequency of the device pattern is calculated for each device pattern, A first calculation unit for obtaining a sum of multiplication values as a first term of the evaluation function;
Based on the limit exposure conditions that may cause a disconnection or a short circuit in the device pattern, a function whose value is sufficiently large below the limit exposure condition and above the limit exposure condition is expressed by the second and second terms of the evaluation function. A second calculation unit for obtaining three terms;
An exposure apparatus comprising: an exposure condition determining unit that determines the optimum exposure condition based on a condition that the sum of the first term, the second term, and the third term of the evaluation function is minimized.

(Appendix 7) Various evaluation patterns are formed by exposure under a plurality of the exposure conditions, and the dimensions of the evaluation patterns are measured.
The first calculation unit calculates a multiplication value of a square of a difference between a dimension of a predetermined evaluation pattern under a predetermined exposure condition and a target value thereof, and an appearance frequency of a corresponding device pattern of the evaluation pattern, Calculated for each evaluation pattern, the sum of the multiplication values as the first term,
The exposure according to appendix 6, wherein the condition determination unit sets the condition that minimizes the sum of the first term, the second term, and the third term of the evaluation function as the optimum exposure condition. apparatus.

  (Additional remark 8) The said 1st calculation part uses the square of the difference of the said estimated dimension and its target value using the estimated dimension of the said predetermined | prescribed device pattern in the predetermined | prescribed exposure conditions, and the said 7. The exposure apparatus according to appendix 6, wherein a multiplication value with the appearance frequency of the device pattern is calculated for each device pattern, and the sum of the multiplication values is the first term.

  (Supplementary note 9) The exposure apparatus according to supplementary note 8, wherein MEEF is added to the predetermined predicted size.

  (Supplementary Note 10) The various device patterns include the device pattern extending in the vertical direction and the device pattern extending in the horizontal direction on the exposed surface. 10. The exposure apparatus according to any one of 9 above.

(Appendix 11) A first step of exposing and transferring a mask pattern of a photomask to a resist on a semiconductor substrate to form a resist pattern;
A second step of forming a device pattern on the semiconductor substrate using the resist pattern,
The first step includes
In determining the optimum exposure conditions for forming a plurality of types of device patterns,
A multiplication value of the square of the difference between the predetermined dimension of the device pattern under a predetermined exposure condition and its target value and the appearance frequency of the device pattern is calculated for each device pattern, and the sum of the multiplication values As a first term of the evaluation function;
Identifying a limit exposure condition that may cause a disconnection or a short circuit in the device pattern; and
Obtaining a function having a sufficiently large value below the limit exposure condition and above the limit exposure condition as the second and third terms of the evaluation function;
And determining the optimum exposure condition based on a condition in which the sum of the first term, the second term, and the third term of the evaluation function is minimized.

(Supplementary Note 12) The first step includes
A step of exposing and forming various evaluation patterns according to a plurality of the exposure conditions;
Further measuring the dimension of each evaluation pattern,
In the step of obtaining the first term of the evaluation function, a square of a difference between a dimension of a predetermined evaluation pattern under a predetermined exposure condition and a target value thereof, and an appearance frequency of a device pattern corresponding to the evaluation pattern A multiplication value is calculated for each evaluation pattern, and the sum of the multiplication values is the first term,
12. The method of manufacturing a semiconductor device according to appendix 11, wherein a condition that minimizes the sum of the first term, the second term, and the third term of the evaluation function is the optimum exposure condition.

  (Supplementary note 13) In the step of obtaining the first term of the evaluation function, the difference between the predicted dimension and its target value is determined using a predicted dimension of the predetermined device pattern defined in a predetermined exposure condition. The multiplication value of the square and the appearance frequency of the device pattern is calculated for each device pattern, and the sum of the multiplication values is the first term. Production method.

  (Supplementary note 14) The method of manufacturing a semiconductor device according to supplementary note 13, wherein MEEF is added to the predetermined predicted size.

  (Supplementary Note 15) The various device patterns include the device pattern extending in the vertical direction and the device pattern extending in the horizontal direction on the exposed surface. 14. The method for manufacturing a semiconductor device according to claim 14.

It is the characteristic view which plotted the appearance frequency of the space between patterns about the gate pattern of a standard cell with respect to the space. It is a characteristic view which shows the evaluation function in this case. It is a schematic diagram which shows schematic structure of the exposure apparatus by 1st Embodiment. It is a flowchart which shows the exposure setting method by 1st Embodiment in order of a step. It is a schematic diagram which shows the evaluation pattern used in 1st Embodiment. It is a characteristic view which shows the result of having investigated the appearance frequency of each device pattern in a certain semiconductor chip. FIG. 6 is a characteristic diagram showing a relationship between a measured CD value and a focus value set in the exposure apparatus. FIG. 10 is a characteristic diagram showing the dependency of the CD value on the exposure amount when the focus value on the setting of the exposure apparatus is 0 nm and ± 40 nm. It is a figure which shows the 1st term of an evaluation function with respect to the matrix of each exposure amount and each focus value. It is a figure which shows the result of having performed simulation on the exposure conditions similar to the conditions which measured CD value, and extracting the hot spot. It is a figure which shows the example which calculated | required the touch width of the exposure conditions which may occur at the time of mass production from the specification of exposure apparatus. It is a figure which shows the range of the exposure condition variation | variation of exposure condition + exposure apparatus with which disconnection or a short circuit may occur. It is a figure which shows the exposure condition dependence of an evaluation function. It is a schematic sectional drawing which shows the MOS transistor produced by 1st Embodiment. It is a flowchart which shows the exposure setting method by 3rd Embodiment in order of a step. It is a figure which shows an example of the investigation of an OPC residue and EL. It is a characteristic view which shows the appearance frequency in the actual device pattern about the resist pattern which calculated | required OPC residue etc. It is a characteristic view which shows the 1st term of an evaluation function. It is a flowchart which shows the exposure setting method by 4th Embodiment in order of a step. It is a characteristic view which shows an OPC residue when the average dimension of a mask pattern has become small compared with the target value. It is a characteristic view which shows the pattern dependence of MEEF. It is a figure which shows the 1st term of an evaluation function. It is a schematic diagram which shows the internal structure of a personal user terminal device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Photomask 11 Light source 12 Illumination optical system 13 Mask stage 14 Projection optical system 15 Wafer stage 16 Control part 20 Semiconductor substrate 21 1st term calculation part 22 2nd term calculation part 23 3rd term calculation part 24 Evaluation function determination part 25 Exposure Condition determining section

Claims (6)

When determining the optimum exposure conditions for forming multiple types of device patterns,
A multiplication value of the square of the difference between the predetermined dimension of the device pattern under a predetermined exposure condition and its target value and the appearance frequency of the device pattern is calculated for each device pattern, and the sum of the multiplication values As a first term of the evaluation function;
Identifying a limit exposure condition that may cause a disconnection or a short circuit in the device pattern; and
Obtaining a function having a sufficiently large value below the limit exposure condition and above the limit exposure condition as the second and third terms of the evaluation function;
And determining the optimum exposure condition based on a condition that minimizes the sum of the first term, the second term, and the third term of the evaluation function. A step of exposing and forming various evaluation patterns according to a plurality of the exposure conditions;
Further measuring the dimension of each evaluation pattern,
In the step of obtaining the first term of the evaluation function, a square of a difference between a dimension of a predetermined evaluation pattern under a predetermined exposure condition and a target value thereof, and an appearance frequency of a device pattern corresponding to the evaluation pattern A multiplication value is calculated for each evaluation pattern, and the sum of the multiplication values is the first term,
2. The exposure method according to claim 1, wherein a condition that minimizes the sum of the first term, the second term, and the third term of the evaluation function is the optimum exposure condition.   In the step of obtaining the first term of the evaluation function, using a predicted dimension of the predetermined device pattern under a predetermined exposure condition, a square of a difference between the predicted dimension and a target value thereof, The exposure method according to claim 1, wherein a multiplication value with the appearance frequency of the device pattern is calculated for each device pattern, and a total sum of the multiplication values is the first item.   4. The exposure method according to claim 3, wherein MEEF is added to the predetermined predicted size.   5. The device according to claim 1, wherein the various device patterns include the device pattern extending in a vertical direction and the device pattern extending in a horizontal direction on a surface to be exposed. The exposure method according to claim 1. A first step of exposing and transferring a mask pattern of a photomask to a resist on a semiconductor substrate to form a resist pattern;
A second step of forming a device pattern on the semiconductor substrate using the resist pattern,
The first step includes
In determining the optimum exposure conditions for forming a plurality of types of device patterns,
A multiplication value of the square of the difference between the predetermined dimension of the device pattern under a predetermined exposure condition and its target value and the appearance frequency of the device pattern is calculated for each device pattern, and the sum of the multiplication values As a first term of the evaluation function;
Identifying a limit exposure condition that may cause a disconnection or a short circuit in the device pattern; and
Obtaining a function having a sufficiently large value below the limit exposure condition and above the limit exposure condition as the second and third terms of the evaluation function;
And determining the optimum exposure condition based on a condition in which the sum of the first term, the second term, and the third term of the evaluation function is minimized.

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