JP2010045203A - Semiconductor chip and method of manufacturing the same - Google Patents

Abstract

A semiconductor chip having no voids and high productivity and a method for manufacturing the same are provided.
An n type silicon layer is formed on an n ⁺ type silicon wafer, and a trench extending in one direction from the upper surface side of the n type silicon layer is formed. At this time, the trench 13 is continuously formed from the vicinity of one edge of the wafer 11w to the vicinity of the other edge so that both ends of the trench 13 are not disposed inside the chip region Rc. Next, the p-type silicon pillar 14 is embedded in the trench 13 by epitaxially growing p-type silicon on the inner surface of the trench 13. Next, the wafer 11w is cut into a plurality of chips along the dicing line DL. Thereby, a semiconductor chip is manufactured.
[Selection] Figure 4

Description

  The present invention relates to a semiconductor chip and a manufacturing method thereof, and more particularly to a power control semiconductor chip having a super junction structure and a manufacturing method thereof.

  As a power control semiconductor chip that achieves both high breakdown voltage and low on-resistance, a super junction structure in which p-type semiconductor pillars are embedded in an n-type semiconductor layer and n-type portions and p-type portions are alternately arranged ( Hereinafter, a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a “SJ structure” is known. In the SJ structure, by making the amounts of impurities contained in the n-type part and the p-type part equal to each other, a pseudo non-doped layer is created and a high breakdown voltage is maintained, and the n-type part has a high impurity concentration. By flowing a current, a low on-resistance can be realized.

As one of the methods for forming such an SJ-structure MOSFET, an n-type semiconductor layer is grown on an n ⁺ -type semiconductor substrate by an epitaxial growth method, and a plurality of trenches are formed in the semiconductor layer. There is a method of forming a p-type semiconductor pillar by epitaxially growing a p-type semiconductor material.

  However, in this method, the growth rate of the p-type semiconductor material in the opening of the trench is higher than the growth rate in the inside of the trench, and the opening is closed before the inside of the trench is filled. There is a problem that is formed. In order to avoid this problem, a method of controlling the epitaxial growth conditions within a predetermined range has been proposed (see, for example, Patent Document 1). However, if the conditions for epitaxial growth are such that no voids are formed, the growth rate of the p-type semiconductor material becomes slow, and there is a problem that productivity decreases.

JP 2007-96139 A

  An object of the present invention is to provide a semiconductor chip having no voids and high productivity and a method for manufacturing the same.

  According to one aspect of the present invention, a first conductivity type semiconductor substrate, a first conductivity type semiconductor layer provided on the semiconductor substrate and having a trench extending in one direction formed from the upper surface side, and the inside of the trench A semiconductor pillar of a second conductivity type embedded in the semiconductor pillar, wherein the semiconductor pillar is continuously formed over the entire length from one end face to the other end face in the one direction of the semiconductor layer. A semiconductor chip is provided.

  According to another aspect of the present invention, a step of forming a first conductivity type semiconductor layer on a first conductivity type semiconductor wafer, and a step of forming a trench extending in one direction from the upper surface side of the semiconductor layer; And burying a semiconductor pillar in the trench by depositing a semiconductor material of a second conductivity type on the inner surface of the trench, and slicing the semiconductor wafer into a plurality of chips. In the process, a semiconductor chip manufacturing method is provided, wherein dicing is performed so that the semiconductor pillar is exposed at an end face of the chip.

  According to the present invention, it is possible to realize a semiconductor chip having no voids and high productivity and a manufacturing method thereof.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described.
FIG. 1 is a plan view illustrating a semiconductor chip according to this embodiment.
2 is a partial cross-sectional view taken along line AA ′ shown in FIG.
FIG. 3 is a partial cross-sectional view taken along the line BB ′ shown in FIG.
The semiconductor chip according to the present embodiment is a power control semiconductor chip in which an SJ structure and a vertical MOSFET are formed.
In FIG. 1, for convenience of illustration, only an n-type silicon layer 12, a p-type silicon pillar 14, and a diffusion region 20, which will be described later, are schematically shown, and other components are not shown.

As shown in FIGS. 1 to 3, in the semiconductor chip 1 according to this embodiment, as the semiconductor substrate, n ⁺ -type silicon substrate 11 made of n ⁺ -type single crystal silicon is provided, the n ⁺ -type silicon An n-type silicon layer 12 made of n-type single crystal silicon is provided on the substrate 11. A plurality of trenches 13 are formed in the n-type silicon layer 12 so as to extend from the upper surface side of the n-type silicon layer 12 in one direction parallel to the upper surface. When viewed from above, the plurality of trenches 13 are formed in parallel to each other. Further, the trench 13 does not reach the n ⁺ type silicon substrate 11.

  A p-type silicon pillar 14 is embedded in the trench 13 by embedding p-type single crystal silicon. Thus, in the n-type silicon layer 12, the p-type silicon pillars 14 and the portions between the p-type silicon pillars 14 in the n-type silicon layer 12 are alternately arranged to form a super junction structure (SJ structure). Has been. Hereinafter, the direction in which the p-type silicon pillar 14 extends is referred to as “pillar direction”, and the direction orthogonal to the pillar direction, that is, the direction in which the p-type silicon pillars 14 are arranged is referred to as “SJ direction”.

  Each trench 13 is continuously formed over the entire length of the semiconductor chip 1. Accordingly, each p-type silicon pillar 14 is continuously provided over the entire length of the semiconductor chip 1. That is, the p-type silicon pillar 14 is continuously formed over the entire length from one end face to the other end face in the pillar direction of the n-type silicon layer 12. The end surface of the n-type silicon layer 12 constitutes a part of the dicing surface DS of the semiconductor chip 1. Therefore, the p-type silicon pillar 14 is exposed at the dicing surface DS.

A p-type base region 15 extending in the pillar direction is formed above the p-type silicon pillar 14 in the n-type silicon layer 12. In the upper layer portion of the p-type base region 15, a pair of n ⁺ -type source regions 16 extending in the pillar direction are formed apart from each other. A p ⁺ -type contact region 17 is formed between the source regions 16 in the p-type base region 15.

Further, an n ⁺ type diffusion region 20 is formed in the upper layer portion of the n-type silicon layer 12 and the p-type silicon pillar 14 at the terminal portion of the semiconductor chip 1. The impurity concentration of the diffusion region 20 is higher than the impurity concentration of the n-type silicon layer 12. Further, the shape of the diffusion region 20 viewed from above is an annular shape along the outer edge of the semiconductor chip 1, that is, the outer edge of the n-type silicon layer 12.

  Further, a gate electrode 21 is provided on the n-type silicon layer 12, and a gate insulating film 22 is provided so as to surround the gate electrode 21. The gate electrode 21 is made of, for example, polysilicon, and the gate insulating film 22 is made of, for example, silicon oxide. The gate electrode 21 is disposed immediately above a region between adjacent source regions 16 formed in adjacent p-type base regions 15. That is, the gate electrode 21 is provided immediately above one of the p-type base region 15, the n-type silicon layer 12, and the other p-type base region 15 disposed between the adjacent source regions 16. It is provided in a region including a region directly above the portion between the n-type silicon layer 12 and the source region 16 in the type base region 15. In addition, the gate electrode 21 is curved so as to protrude upward, and the center portion, that is, the position corresponding to the region directly above the n-type silicon layer 12 is relatively high, and both end portions are relatively low. Yes.

Furthermore, a source electrode 23 is provided between and on the gate electrodes 21. A portion between the gate electrodes 21 in the source electrode 23 is connected to the source region 16 and the contact region 17. The gate electrode 21 is insulated from the n-type silicon layer 12 and the source electrode 23 by the gate insulating film 22. On the other hand, on the lower surface of the n ⁺ -type silicon substrate 11, the drain electrode 24 is provided, which is connected to the n ⁺ -type silicon substrate 11. The source electrode 23 and the drain electrode 24 are made of, for example, metal.

Next, a method for manufacturing a semiconductor chip according to the present embodiment will be described.
FIG. 4A is a plan view illustrating the method for manufacturing a semiconductor chip according to this embodiment, and FIG. 4B is a partially enlarged plan view illustrating one chip region shown in FIG.
4A and 4B, for convenience of illustration, the area of the chip region relative to the wafer and the width of the p-type silicon pillar are drawn larger than actual.

First, as shown in FIGS. 2 and 4A, a wafer 11w made of n ⁺ -type single crystal silicon is prepared. Then, n-type silicon is epitaxially grown on the upper surface of the wafer 11w to form the n-type silicon layer 12. Next, a plurality of trenches 13 extending in one direction (pillar direction) parallel to the upper surface of the n-type silicon layer 12 are formed from the upper surface side of the n-type silicon layer 12 to the middle of the n-type silicon layer 12. At this time, as shown in FIGS. 4A and 4B, each trench 13 is continuously formed from one edge in the pillar direction to the other edge in the wafer 11w, and both ends of the trench 13 are formed. The portion is a chip region Rc, that is, a rectangular region surrounded by the dicing line DL, and is not arranged in a region to be a chip after dicing. That is, each trench 13 is formed so as to straddle the dicing line DL of the wafer 11w, and both end portions of the trench 13 are disposed in the discard region Rs on the outer peripheral portion of the wafer 11w.

Next, as shown in FIGS. 2 and 3, p-type silicon is epitaxially grown and deposited in the trench 13, and a p-type silicon pillar 14 is embedded in the trench 13. At this time, the epitaxial growth is performed by, for example, the CVD method (Chemical Vapor Deposition method) after the upper surface of the n-type silicon layer 12 is covered with the silicon oxide film 31 (see FIG. 5). The CVD conditions are, for example, using trichlorosilane (TCS) as a raw material, a temperature of 1100 to 1150 ° C., and a pressure of atmospheric pressure. Alternatively, dichlorosilane (DCS) is used as a raw material, the temperature is set to 900 to 1100 ° C., and the pressure is set to a reduced pressure condition, for example, 1 to 40 kPa. Alternatively, silane (SiH ₄ ) is used as a raw material, the temperature is set to 800 to 1000 ° C., and the pressure is set to a reduced pressure condition, for example, 1 to 40 kPa.

  Next, the p-type base region 15, the source region 16, and the contact region 17 are formed by a normal method. Further, the diffusion region 20 is formed along the dicing line DL. Then, the gate electrode 21 and the gate insulating film 22 are formed on the n-type silicon layer 12, and the source electrode 23 is formed so as to cover the gate electrode 21 and the gate insulating film 22. On the other hand, the drain electrode 24 is formed on the lower surface of the wafer 11w.

Next, as shown in FIGS. 4A and 4B, the wafer 11w and the components formed thereon are diced along a dicing line DL and cut into a plurality of chips. At this time, dicing is performed so that the p-type silicon pillar 14 is exposed at the end face of each chip. Thereby, the wafer 11w is cut into a plurality of n ⁺ -type silicon substrates 11, and a plurality of semiconductor chips 1 are manufactured. In each semiconductor chip 1, portions other than both ends of the p-type silicon pillar 14 are disposed, and both ends of the p-type silicon pillar 14 are disposed in the discard region Rs on the outer peripheral portion of the wafer 11 w. Therefore, as shown in FIG. 3, in each semiconductor chip 1, the p-type silicon pillar 14 is exposed on the dicing surface DS facing the pillar direction.

Next, the effect of this embodiment is demonstrated.
FIG. 5 is a diagram illustrating the flow of a source gas when epitaxially growing p-type silicon in a trench.
FIGS. 6A and 6B are cross-sectional views illustrating a buried p-type silicon pillar, where FIG. 6A shows an intermediate portion of the trench, and FIG. 6B shows an end portion of the trench.

  As shown in FIG. 5, when silicon is epitaxially grown in the trench 13, the upper surface of the n-type silicon layer 12 is covered with the silicon oxide film 31, and the source gas is allowed to enter the trench 13. At this time, in a portion other than both end portions 13a in the longitudinal direction (pillar direction) of the trench 13 (hereinafter referred to as “intermediate portion 13b”), the source gas flows from two directions, that is, from the width direction of the trench 13 (SJ direction). Supplied. On the other hand, the source gas is supplied from three directions at the end 13a of the trench 13. That is, in the end portion 13a, the source gas is supplied from one direction on the side where the trench terminates in the longitudinal direction (pillar direction) in addition to the two directions in the width direction (SJ direction) of the trench 13. The For this reason, the supply amount of the source gas is larger in the end portion 13a of the trench 13 than in the intermediate portion 13b. Further, the end portion 13a has a different crystal orientation on the inner surface of the trench 13 compared to the intermediate portion 13b. Due to these factors, silicon grows faster in the end portion 13a of the trench 13 than in the intermediate portion 13b.

  As a result, as shown in FIG. 6A, even if CVD is performed in the intermediate portion 13b of the trench 13 under the condition that the inside of the trench 13 is completely filled with silicon, as shown in FIG. At both end portions 13a of 13, the growth of silicon in the opening portion of the trench 13 becomes too fast, the opening portion is closed before the inside is filled with silicon, and a void 32 is formed. When the void 32 is generated in the p-type silicon pillar 14, the characteristics of the semiconductor chip 1 are deteriorated.

  In order to avoid this, it is also conceivable that the CVD conditions are such that the inside of the trench 13 is completely filled at both ends 13a of the trench 13. However, in this case, the growth rate of silicon is remarkably slowed, and the productivity of the semiconductor chip 1 is significantly reduced.

  Therefore, in the present embodiment, the trench 13 is continuously formed from the vicinity of one edge in the pillar direction of the wafer 11w to the vicinity of the other edge, and both ends of the trench 13 are in a region where chips are to be formed. Avoid being placed. Thereby, only the middle part of the p-type silicon pillar 14 is arranged in the semiconductor chip 1 after dicing, and the end part of the p-type silicon pillar 14 is arranged in the discard region Rs of the outer peripheral part of the wafer 11w. As a result, only the intermediate part of the p-type silicon pillar 14 where no void is generated can be used for the semiconductor chip 1. Thus, according to this embodiment, a semiconductor chip having no voids and good characteristics can be manufactured with high productivity.

  In this embodiment, since the dicing is performed so that the p-type silicon pillar 14 is divided, in the semiconductor chip 1 after dicing, the p-type silicon pillar 14 is exposed at the dicing surface DS of the semiconductor chip 1. . Therefore, in the present embodiment, an annular diffusion region 20 is formed on the outer periphery of the semiconductor chip 1. By applying a constant potential to the diffusion region 20, the diffusion region 20 functions as an EQPR (Equivalent Potential Ring), and the depletion generated from the junction interface between the n-type silicon layer 12 and the p-type silicon pillar 14. It is possible to prevent the layer from reaching the dicing surface DS.

Next, a comparative example of this embodiment will be described.
FIG. 7A is a plan view illustrating a method for manufacturing a semiconductor chip according to this comparative example, and FIG. 7B is a partially enlarged plan view illustrating one chip region shown in FIG.
7A and 7B, for convenience of illustration, the area of the chip region relative to the wafer and the width of the p-type silicon pillar are drawn larger than actual.

  As shown in FIGS. 7A and 7B, in the method of manufacturing a semiconductor chip according to this comparative example, when the trench 13 is formed in the n-type silicon layer 12 formed on the wafer 11w, the chip region A trench 13 is formed for each Rc. Subsequent steps are the same as those in the first embodiment.

  According to this comparative example, both ends of the p-type silicon pillar 14, that is, portions where voids are generated are included in the chip after dicing. For this reason, the characteristics of the semiconductor chip are lowered.

Next, a second embodiment of the present invention will be described.
FIG. 8 is a plan view illustrating a semiconductor chip according to this embodiment.
FIG. 9 is a partial cross-sectional view illustrating a semiconductor chip according to this embodiment.
In FIG. 8, for convenience of illustration, components other than the n-type silicon region 12, a trench 41 and an insulating layer 42 described later are not shown.

As shown in FIGS. 8 and 9, the semiconductor chip 2 according to the present embodiment has a diffusion region 20 (see FIG. 1) that becomes an EQPR as compared with the semiconductor chip 1 according to the first embodiment described above (see FIG. 1). 1) is provided, and instead, a trench 41 is formed in the n-type silicon layer 12 and the p-type silicon pillar 14 from the upper surface side of the n-type silicon layer 12 and the p-type silicon pillar 14. The trench 41 is different in that an insulating material, for example, silicon oxide is embedded in the trench 41 and an insulating layer 42 is formed. Note that the trench 41 does not reach the n ⁺ -type silicon substrate 11. The insulating layer 42 is formed at the terminal portion of the semiconductor chip 2, and the shape viewed from above is an annular shape along the outer edge of the semiconductor chip 2, that is, the outer edge of the n-type silicon layer 12.

  In the present embodiment, since the annular insulating layer 42 is provided at the terminal portion of the semiconductor chip 2, the depletion layer generated from the junction interface between the n-type silicon layer 12 and the p-type silicon pillar 14 is the semiconductor chip 2. The dicing surface DS is not reached. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

Next, a third embodiment of the present invention will be described.
FIG. 10 is a partial cross-sectional view illustrating a semiconductor chip according to this embodiment.
As shown in FIG. 10, the semiconductor chip 3 according to the present embodiment has a diffusion region 20 (see FIG. 1) that becomes an EQPR as compared with the semiconductor chip 1 (see FIG. 1) according to the first embodiment described above. However, the field plate electrode 46 is provided on the n-type silicon layer 12 instead. The field plate electrode 46 is formed at the terminal portion of the semiconductor chip 3, and the shape seen from above is an annular shape along the outer edge of the semiconductor chip 3, that is, the outer edge of the n ⁺ -type silicon substrate 11. The field plate electrode 46 is formed of a conductive material such as metal.

  In the present embodiment, since the annular field plate electrode 46 is provided at the terminal portion of the semiconductor chip 3, the electric field concentration at the terminal portion is alleviated, and the junction interface between the n-type silicon layer 12 and the p-type silicon pillar 14 is reduced. It is possible to prevent the depletion layer generated from reaching the dicing surface DS of the semiconductor chip 3. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to these embodiments. For example, those in which the person skilled in the art appropriately added, deleted, or changed the design of the above-described embodiments, or those in which the process was added, omitted, or changed the conditions are also included in the gist of the present invention. As long as it is provided, it is included in the scope of the present invention.

For example, in each of the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is It can also be implemented as an n-type. Further, an n ⁻ -type buffer layer having an impurity concentration lower than that of the n-type silicon layer 12 may be provided between the n ⁺ -type silicon substrate 11 and the n-type silicon layer 12. Furthermore, in each of the above-described embodiments, the semiconductor chip having a planar MOS gate structure has been described as an example. However, the semiconductor chip according to the present invention can also be implemented using a trench MOS gate structure (UMOS structure). Is possible. Furthermore, in each of the above-described embodiments, an example in which silicon (Si) is used as a semiconductor has been described. For example, a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN), or diamond is used as the semiconductor. A wide bandgap semiconductor such as can also be used.

1 is a plan view illustrating a semiconductor chip according to a first embodiment of the invention. It is a fragmentary sectional view by the A-A 'line shown in FIG. It is a fragmentary sectional view by the B-B 'line shown in FIG. (A) is a top view which illustrates the manufacturing method of the semiconductor chip which concerns on 1st Embodiment, (b) is a partially expanded plan view which illustrates one chip area | region shown to (a). It is a figure which illustrates the flow of source gas at the time of carrying out the epitaxial growth of p-type silicon in a trench. (A) And (b) is sectional drawing which illustrates the embedded p-type silicon pillar, (a) shows the intermediate part of a trench, (b) shows the edge part of a trench. (A) is a top view which illustrates the manufacturing method of the semiconductor chip which concerns on a comparative example, (b) is a partially expanded plan view which illustrates one chip area | region shown to (a). FIG. 6 is a plan view illustrating a semiconductor chip according to a second embodiment of the invention. FIG. 6 is a partial cross-sectional view illustrating a semiconductor chip according to a second embodiment. FIG. 6 is a partial cross-sectional view illustrating a semiconductor chip according to a third embodiment of the invention.

Explanation of symbols

1, 2, 3 Semiconductor chip, 11 n ⁺ type silicon substrate, 11w wafer, 12 n type silicon layer, 13 trench, 13a end, 13b middle part, 14 p type silicon pillar, 15 p type base region, 16 source region , 17 contact region, 20 diffusion region, 21 gate electrode, 22 gate insulating film, 23 source electrode, 24 drain electrode, 31 silicon oxide film, 32 void, 41 trench, 42 insulating layer, 46 field plate electrode, DL dicing line, DS dicing surface, Rc chip area, Rs discard area

Claims (5)

A first conductivity type semiconductor substrate;
A semiconductor layer of a first conductivity type provided on the semiconductor substrate and having a trench extending in one direction formed from the upper surface side;
A second conductivity type semiconductor pillar embedded in the trench;
With
The semiconductor chip is formed continuously over the entire length from one end surface to the other end surface in the one direction of the semiconductor layer.   A diffusion region formed in an upper layer portion of the semiconductor layer and the semiconductor pillar, the impurity concentration being higher than the impurity concentration of the semiconductor layer, and a shape viewed from above is an annular shape along the outer edge of the semiconductor chip; The semiconductor chip according to claim 1.   The semiconductor chip according to claim 1, further comprising an insulating layer embedded in the semiconductor layer and the semiconductor pillar and having an annular shape along an outer edge of the semiconductor chip as viewed from above.   2. The semiconductor device according to claim 1, further comprising a field plate electrode provided above the semiconductor layer and the semiconductor pillar, made of a conductive material and having an annular shape along the outer edge of the semiconductor chip as viewed from above. The semiconductor chip described. Forming a first conductivity type semiconductor layer on a first conductivity type semiconductor wafer;
Forming a trench extending in one direction from the upper surface side of the semiconductor layer;
Burying a semiconductor pillar in the trench by depositing a second conductivity type semiconductor material on the inner surface of the trench;
Cutting the semiconductor wafer into a plurality of chips;
With
In the step of cutting the chip, dicing is performed so that the semiconductor pillar is exposed at the end face of the chip.

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