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JP2010040616A - Method for forming electrode and semiconductor device - Google Patents

Method for forming electrode and semiconductor device Download PDF

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JP2010040616A
JP2010040616A JP2008199161A JP2008199161A JP2010040616A JP 2010040616 A JP2010040616 A JP 2010040616A JP 2008199161 A JP2008199161 A JP 2008199161A JP 2008199161 A JP2008199161 A JP 2008199161A JP 2010040616 A JP2010040616 A JP 2010040616A
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insulating film
film
electrode
forming
semiconductor substrate
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JP2010040616A5 (en
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Takashi Washino
隆 鷲野
Shigenori Hayakawa
茂則 早川
Kazuhiro Komatsu
和弘 小松
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Opnext Japan Inc
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Opnext Japan Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To precisely form an electrode pattern by using a first insulating film (for lift-off) and a second insulating film (for electrode layer separation) whose etching rate is lower than the first insulating film, as masks in vapor deposition of an electrode. <P>SOLUTION: The method of forming an electrode includes steps of: forming an insulating film of four layers where SiO<SB>2</SB>film 12-1, SiN film 14-1, SiO<SB>2</SB>film 12-2, and SiN film 14-2 are sequentially stacked on one surface (contact layer 10) of a semiconductor substrate; forming a contact hole that penetrates up to the surface of the contact layer 10 in the insulating film of four layers; causing the side surface of the SiO<SB>2</SB>film 12-2 exposed in the contact hole to recede by a predetermined distance from the side surface of the SiN film 14-2 exposed ion the contact hole, using a chemical liquid (for example hydrofluoric acid) whose etching rate to the SiO<SB>2</SB>film 12 is higher than that to the SiN film 14; forming an electrode layer 20-1 having a thickness not abutting with the SiN film 14-2 by vapor-deposition on the contact layer 10 exposed in the contact hole; and removing the SiN film 14-2 together with the SiO<SB>2</SB>film 12-2 using a chemical liquid. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、電極形成方法および半導体素子に関し、特に、２層以上の絶縁膜をマスクとして利用する技術に関する。   The present invention relates to an electrode forming method and a semiconductor element, and more particularly, to a technique using two or more insulating films as a mask.

従来、半導体素子に対する電極形成方法として２つの方法が知られている。   Conventionally, two methods are known as electrode forming methods for semiconductor elements.

１つは、半導体基板上に形成されたレジストマスクの上から電極材料を蒸着する方法（以下「従来電極形成方法１」という）である。従来電極形成方法１には、図５に示すように、半導体基板１０上に形成された絶縁膜１２を覆うレジスト膜２２を形成する工程（同図（ａ））と、レジスト膜２２をマスクとして蒸着により電極層２０を形成する工程（同図（ｂ）と、レジスト膜２２上に蒸着された電極層２０−２をレジスト膜２２とともに除去（リフトオフ）する工程（同図（ｃ））と、が含まれる。この方法によれば、レジスト膜２２で覆われていない領域に電極が形成される。なお、特許文献１には、従来電極形成方法１の一例が開示されている。   One is a method of depositing an electrode material from above a resist mask formed on a semiconductor substrate (hereinafter referred to as “conventional electrode forming method 1”). As shown in FIG. 5, the conventional electrode forming method 1 includes a step of forming a resist film 22 covering the insulating film 12 formed on the semiconductor substrate 10 (FIG. 5A), and using the resist film 22 as a mask. A step of forming the electrode layer 20 by vapor deposition (FIG. 2B), a step of removing (lift-off) the electrode layer 20-2 deposited on the resist film 22 together with the resist film 22 (FIG. 1C), According to this method, an electrode is formed in a region that is not covered with the resist film 22. Note that Patent Document 1 discloses an example of the conventional electrode forming method 1.

もう１つは、半導体基板上に広く蒸着された電極材料を後から部分的に除去する方法（以下「従来電極形成方法２」という）である。従来電極形成方法２には、図６に示すように、半導体基板１０および半導体基板１０上に形成された絶縁膜１２の上に蒸着により電極層２０を形成する工程（同図（ａ））と、電極層２０のうち電極となる部分を覆うレジスト膜２４を形成する工程（同図（ｂ））と、電極層２０のうちレジスト膜２４で覆われていない部分をドライエッチングにより除去する工程（同図（ｃ））と、電極層２０上に形成されたレジスト膜２４を除去（リフトオフ）する工程（同図（ｄ））と、が含まれる。この方法によれば、レジスト膜２４で覆われた領域に電極が形成される。なお、特許文献２には、従来電極形成方法２の一例が開示されている。
特開平７−１５３６６６号公報 特開平１０−０２２４５３号公報 The other is a method in which an electrode material widely deposited on a semiconductor substrate is partially removed later (hereinafter referred to as “conventional electrode formation method 2”). As shown in FIG. 6, the conventional electrode forming method 2 includes a step of forming an electrode layer 20 by vapor deposition on a semiconductor substrate 10 and an insulating film 12 formed on the semiconductor substrate 10 (FIG. 6A). The step of forming a resist film 24 that covers the electrode layer 20 in the electrode layer 20 (FIG. 5B), and the step of removing the portion of the electrode layer 20 that is not covered with the resist film 24 by dry etching (see FIG. (C)) and a step of removing (lifting off) the resist film 24 formed on the electrode layer 20 ((d) in the same figure). According to this method, an electrode is formed in a region covered with the resist film 24. Patent Document 2 discloses an example of a conventional electrode forming method 2.
JP-A-7-153666 Japanese Patent Laid-Open No. 10-022453

しかしながら、上記従来電極形成方法１および従来電極形成方法２による電極のパタニング精度は十分でない。その理由を以下に説明する。   However, the electrode patterning accuracy by the conventional electrode forming method 1 and the conventional electrode forming method 2 is not sufficient. The reason will be described below.

従来電極形成方法１では、レジストマスクの上から電極材料を蒸着する。このため、電極蒸着時の熱によってレジスト膜２２が軟化または溶融し、レジスト膜２２が図７（ａ）に示す形状から図７（ｂ）に示す形状に変形する場合がある。この場合、図７（ｃ）に示すように、所期の形状とは異なる形状の電極層２０が形成されてしまう。   In the conventional electrode forming method 1, an electrode material is deposited on the resist mask. For this reason, the resist film 22 is softened or melted by heat during electrode deposition, and the resist film 22 may be deformed from the shape shown in FIG. 7A to the shape shown in FIG. In this case, as shown in FIG. 7C, the electrode layer 20 having a shape different from the intended shape is formed.

一方、従来電極形成方法２では、電極が形成される領域以外の領域に蒸着された電極材料が方向性を有するドライエッチングによって除去される。このため、電極が形成される領域以外の領域に段差が存在すると、図８（ａ）〜（ｄ）に示すように、ドライエッチングの影となる部分に蒸着された電極材料２０−３が除去されずに残ってしまう場合がある。   On the other hand, in the conventional electrode forming method 2, the electrode material deposited in a region other than the region where the electrode is formed is removed by dry etching having directionality. For this reason, if there is a step in a region other than the region where the electrode is formed, the electrode material 20-3 deposited on the portion that is shaded by dry etching is removed as shown in FIGS. It may remain without being.

本発明は、上記課題に鑑みてなされたものであり、電極パタンを精度よく形成することができる電極形成方法およびそれにより製造される半導体素子を提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide an electrode forming method capable of forming an electrode pattern with high accuracy and a semiconductor element manufactured thereby.

上記課題を解決するために、本発明に係る電極形成方法は、半導体基板の一方面上に第１の絶縁膜を形成する工程と、前記第１の絶縁膜上に、所定の薬液によるエッチングレートが前記第１の絶縁膜より低い第２の絶縁膜を形成する工程と、前記第１および第２の絶縁膜に、前記半導体基板の一方面まで貫通する開口部を形成する工程と、前記所定の薬液を用いたエッチングにより、前記開口部に露出した前記第１の絶縁膜の側面を前記開口部に露出した前記第２の絶縁膜の側面より所定長だけ後退させる工程と、前記開口部に露出した前記半導体基板の一方面上に、前記第２の絶縁膜に当接しない厚さを有する電極層を蒸着により形成する工程と、前記所定の薬液を用いたエッチングにより、前記第２の絶縁膜を前記第１の絶縁膜とともに除去する工程と、を含むことを特徴とする。   In order to solve the above problems, an electrode forming method according to the present invention includes a step of forming a first insulating film on one surface of a semiconductor substrate, and an etching rate with a predetermined chemical solution on the first insulating film. Forming a second insulating film lower than the first insulating film, forming an opening penetrating to one surface of the semiconductor substrate in the first and second insulating films, and the predetermined A step of causing the side surface of the first insulating film exposed to the opening to recede by a predetermined length from the side surface of the second insulating film exposed to the opening by etching using the chemical solution; An electrode layer having a thickness that does not contact the second insulating film is formed on the exposed one surface of the semiconductor substrate by vapor deposition, and the second insulating layer is formed by etching using the predetermined chemical solution. A film together with the first insulating film Characterized in that it comprises the steps of to, a.

本発明では、まず、半導体基板の一方面上に第１の絶縁膜を形成し、その上に所定の薬液によるエッチングレートが第１の絶縁膜より低い第２の絶縁膜を形成する。次に、第１および第２の絶縁膜に半導体基板の一方面まで貫通する開口部を形成し、形成された開口部の内側面を上記薬液を用いてエッチングする。これにより、開口部の内側面には、第２の絶縁膜が第１の絶縁膜より所定長だけ突き出した「ひさし部」が形成される。   In the present invention, first, a first insulating film is formed on one surface of a semiconductor substrate, and a second insulating film having an etching rate of a predetermined chemical solution lower than that of the first insulating film is formed thereon. Next, an opening that penetrates to one surface of the semiconductor substrate is formed in the first and second insulating films, and an inner surface of the formed opening is etched using the chemical solution. As a result, an “eave portion” in which the second insulating film protrudes by a predetermined length from the first insulating film is formed on the inner surface of the opening.

続いて、第１および第２の絶縁膜をマスクとして、第２の絶縁膜に当接しない厚さを有する電極層を開口部に露出した半導体基板の一方面上に形成する。このとき、第２の絶縁膜上に形成される電極層は、上記ひさし部によって、半導体基板の一方面上に形成された電極層から好適に分離される。   Subsequently, using the first and second insulating films as a mask, an electrode layer having a thickness that does not contact the second insulating film is formed on one surface of the semiconductor substrate exposed in the opening. At this time, the electrode layer formed on the second insulating film is preferably separated from the electrode layer formed on one surface of the semiconductor substrate by the eaves portion.

ここで、上記薬液を用いてエッチングすれば、半導体基板の一方面上に形成された電極層の上面と、第２の絶縁膜（上記ひさし部）と、の間から上記薬液が侵入し、第２の絶縁膜が第１の絶縁膜とともに除去（リフトオフ）される。   Here, if etching is performed using the chemical solution, the chemical solution enters between the upper surface of the electrode layer formed on one surface of the semiconductor substrate and the second insulating film (the eaves portion), and the first The two insulating films are removed (lifted off) together with the first insulating film.

本発明によれば、第１の絶縁膜（リフトオフ用）および第１の絶縁膜よりエッチングレートの低い第２の絶縁膜（電極層分離用）を電極蒸着時のマスクとして用いることにより、電極パタンを精度よく形成することができる。   According to the present invention, the first insulating film (for lift-off) and the second insulating film (for electrode layer separation) having an etching rate lower than that of the first insulating film are used as a mask during electrode deposition. Can be formed with high accuracy.

また、電極蒸着時のマスクとして耐熱性の低いレジストを用いないため、電極形成中の基板加熱が可能となる。これにより、電極密度および電極と半導体基板との密着性が高まり、半導体素子の特性および信頼性を向上させることができる。   In addition, since a resist having low heat resistance is not used as a mask during electrode deposition, the substrate can be heated during electrode formation. As a result, the electrode density and the adhesion between the electrode and the semiconductor substrate are enhanced, and the characteristics and reliability of the semiconductor element can be improved.

さらに、第２の絶縁膜が第１の絶縁膜とともに除去されるため、第２の絶縁膜上に形成された電極層、すなわち電極が形成される領域以外の領域に形成された電極層を完全に除去することができる。このため、仮に半導体基板面に段差が存在していても、電極が形成される領域以外の領域に電極材料が除去されずに残ることはない。   Further, since the second insulating film is removed together with the first insulating film, the electrode layer formed on the second insulating film, that is, the electrode layer formed in a region other than the region where the electrode is formed is completely formed. Can be removed. For this reason, even if there is a step on the surface of the semiconductor substrate, the electrode material does not remain without being removed in a region other than the region where the electrode is formed.

また、本発明に係る他の電極形成方法は、半導体基板の一方面上に第１の絶縁膜を形成する工程と、前記第１の絶縁膜上に、所定の薬液によるエッチングレートが前記第１の絶縁膜より高い第２の絶縁膜を形成する工程と、前記第２の絶縁膜上に、前記所定の薬液によるエッチングレートが前記第２の絶縁膜より低い第３の絶縁膜を形成する工程と、前記第１、第２および第３の絶縁膜に、前記半導体基板の一方面まで貫通する開口部を形成する工程と、前記所定の薬液を用いたエッチングにより、前記開口部に露出した前記第２の絶縁膜の側面を前記開口部に露出した前記第３の絶縁膜の側面より所定長だけ後退させる工程と、前記開口部に露出した前記半導体基板の一方面上に、前記第３の絶縁膜に当接しない厚さを有する電極層を蒸着により形成する工程と、前記所定の薬液を用いたエッチングにより、前記第３の絶縁膜を前記第２の絶縁膜とともに除去する工程と、を含むことを特徴とする。   In another electrode forming method according to the present invention, a step of forming a first insulating film on one surface of a semiconductor substrate, and an etching rate by a predetermined chemical solution on the first insulating film is the first insulating film. Forming a second insulating film higher than the first insulating film, and forming a third insulating film having an etching rate of the predetermined chemical solution lower than that of the second insulating film on the second insulating film. And the step of forming an opening penetrating to one surface of the semiconductor substrate in the first, second, and third insulating films, and the opening exposed to the opening by etching using the predetermined chemical solution A step of retracting a side surface of the second insulating film by a predetermined length from a side surface of the third insulating film exposed in the opening; and the third surface exposed on the one surface of the semiconductor substrate exposed in the opening. Evaporate an electrode layer with a thickness that does not contact the insulating film A step of further forming, by etching using a predetermined chemical liquid, characterized in that it comprises a and removing with said third insulating film using the second insulating film.

本発明によれば、第１の絶縁膜（基板保護用）、第１の絶縁膜よりエッチングレートの高い第２の絶縁膜（リフトオフ用）、および第２の絶縁膜よりエッチングレートの低い第３の絶縁膜（電極層分離用）を電極蒸着時のマスクとして用いることにより、電極パタンを精度よく形成することができる。また、同時に、電極が形成される半導体基板の一方面を第１の絶縁膜で保護することができる。   According to the present invention, the first insulating film (for protecting the substrate), the second insulating film (for lift-off) having a higher etching rate than the first insulating film, and the third having a lower etching rate than the second insulating film. By using this insulating film (for electrode layer separation) as a mask during electrode deposition, the electrode pattern can be formed with high accuracy. At the same time, one surface of the semiconductor substrate on which the electrode is formed can be protected with the first insulating film.

また、本発明に係る他の電極形成方法は、半導体基板の一方面上に第１の絶縁膜を形成する工程と、前記第１の絶縁膜上に、所定の薬液によるエッチングレートが前記第１の絶縁膜より低い第２の絶縁膜を形成する工程と、前記第２の絶縁膜上に、前記所定の薬液によるエッチングレートが前記第２の絶縁膜より高い第３の絶縁膜を形成する工程と、前記第３の絶縁膜上に、前記所定の薬液によるエッチングレートが前記第３の絶縁膜より低い第４の絶縁膜を形成する工程と、前記第１、第２、第３および第４の絶縁膜に、前記半導体基板の一方面まで貫通する開口部を形成する工程と、前記所定の薬液を用いたエッチングにより、前記開口部に露出した前記第３の絶縁膜の側面を前記開口部に露出した前記第４の絶縁膜の側面より所定長だけ後退させる工程と、前記開口部に露出した前記半導体基板の一方面上に、前記第４の絶縁膜に当接しない厚さを有する電極層を蒸着により形成する工程と、前記所定の薬液を用いたエッチングにより、前記第４の絶縁膜を前記第３の絶縁膜とともに除去する工程と、を含むことを特徴とする。   In another electrode forming method according to the present invention, a step of forming a first insulating film on one surface of a semiconductor substrate, and an etching rate by a predetermined chemical solution on the first insulating film is the first insulating film. Forming a second insulating film lower than the first insulating film, and forming a third insulating film on the second insulating film, the etching rate of the predetermined chemical solution being higher than that of the second insulating film. Forming a fourth insulating film having an etching rate of the predetermined chemical solution lower than that of the third insulating film on the third insulating film, and the first, second, third and fourth Forming the opening penetrating to one surface of the semiconductor substrate in the insulating film and etching the side surface of the third insulating film exposed to the opening by etching using the predetermined chemical solution. It is a predetermined length from the side surface of the fourth insulating film exposed to A step of retracting, a step of forming an electrode layer having a thickness that does not contact the fourth insulating film on one surface of the semiconductor substrate exposed to the opening, and using the predetermined chemical solution And removing the fourth insulating film together with the third insulating film by etching.

本発明によれば、第１の絶縁膜（基板保護用）、第１の絶縁膜よりエッチングレートの低い第２の絶縁膜（基板保護用）、第２の絶縁膜よりエッチングレートの高い第３の絶縁膜（リフトオフ用）、および第３の絶縁膜よりエッチングレートの低い第４の絶縁膜（電極層分離用）を電極蒸着時のマスクとして用いることにより、電極パタンを精度よく形成することができる。また、同時に、電極が形成される半導体基板の一方面を第１および第２の絶縁膜で保護することができる。特に、半導体基板の一方面に密着する第１の絶縁膜は、その上に形成された第２の絶縁膜に比べてエッチングレートが高い、すなわち密度が低く応力が小さいため、半導体基板の表面をより安全に保護することができる。   According to the present invention, the first insulating film (for protecting the substrate), the second insulating film (for protecting the substrate) whose etching rate is lower than that of the first insulating film, and the third whose etching rate is higher than that of the second insulating film. The electrode pattern can be accurately formed by using the insulating film (for lift-off) and the fourth insulating film (for electrode layer separation) having an etching rate lower than that of the third insulating film as a mask during electrode deposition. it can. At the same time, one surface of the semiconductor substrate on which the electrode is formed can be protected with the first and second insulating films. In particular, the first insulating film in close contact with one surface of the semiconductor substrate has a higher etching rate than that of the second insulating film formed thereon, that is, the density is low and the stress is low. It can be protected more safely.

また、本発明に係る半導体素子は、半導体基板と、前記半導体基板の一方面上に形成された第１の絶縁膜と、前記第１の絶縁層上に形成された、所定の薬液によるエッチングレートが前記第１の絶縁膜より低い第２の絶縁膜と、前記第１および第２の絶縁膜に形成された前記半導体基板の一方面まで貫通する開口部の内側面と、前記半導体基板の一方面と、からなる凹状部を、少なくとも前記第２の絶縁膜の下面を超える高さまで埋める電極層と、を含み、前記電極層の外側面に接する前記第１の絶縁膜の側面は、前記電極層の外側面に接する前記第２の絶縁膜の側面より所定長だけ前記凹状部の中央から離れる方向に後退している、ことを特徴とする。   The semiconductor element according to the present invention includes a semiconductor substrate, a first insulating film formed on one surface of the semiconductor substrate, and an etching rate by a predetermined chemical solution formed on the first insulating layer. A second insulating film lower than the first insulating film, an inner surface of an opening penetrating to one surface of the semiconductor substrate formed in the first and second insulating films, and one of the semiconductor substrates And an electrode layer that fills at least a height of the concave portion including the lower surface of the second insulating film, and the side surface of the first insulating film in contact with the outer surface of the electrode layer includes the electrode It is characterized by receding in a direction away from the center of the concave portion by a predetermined length from the side surface of the second insulating film in contact with the outer surface of the layer.

以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、同一の構成要素には同一の符号を付し、重複説明を省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same component and duplication description is abbreviate | omitted.

［実施形態１］
本発明の実施形態１に係る電極形成方法を図１に基づいて説明する。 [Embodiment 1]
An electrode forming method according to Embodiment 1 of the present invention will be described with reference to FIG.

コンタクト層１０は、半導体素子を構成する半導体基板の一部であり、電極配線と半導体基板内の他の一部とを電気的に接続する導電層である。本実施形態では、このコンタクト層１０上に第１の絶縁膜としてＳｉＯ２膜（シリコン酸化膜）１２を成長させ、たとえばＣＶＤ法（Cemical Vapor Deposition：化学気相成長法）により、ＳｉＯ２膜１２上に第２の絶縁膜としてＳｉＮ膜（シリコン窒化膜）１４をさらに堆積する（図１（ａ））。 The contact layer 10 is a part of the semiconductor substrate constituting the semiconductor element, and is a conductive layer that electrically connects the electrode wiring and the other part in the semiconductor substrate. In this embodiment, the SiO 2 film (silicon oxide film) as the first insulating film on the contact layer 1012 is grown, for example, CVD: by (Cemical Vapor Deposition chemical vapor deposition), SiO 2 film 12 A SiN film (silicon nitride film) 14 is further deposited thereon as a second insulating film (FIG. 1A).

次に、コンタクト層１０に連絡するコンタクトホールを形成するために、たとえばフォトリソグラフィによって、コンタクトホールに沿う開口を有するレジスト膜１６をＳｉＮ膜１４上に形成する（図１（ｂ））。そして、レジスト膜１６をマスクとして、たとえば方向性を有するドライエッチングにより、積層した２層の絶縁膜（ＳｉＯ２膜１２およびＳｉＮ膜１４）に、コンタクト層１０の表面まで貫通するコンタクトホールを形成し（図１（ｃ））、レジスト膜１６を除去する（図１（ｄ））。 Next, in order to form a contact hole communicating with the contact layer 10, a resist film 16 having an opening along the contact hole is formed on the SiN film 14 by, for example, photolithography (FIG. 1B). Then, using the resist film 16 as a mask, a contact hole penetrating to the surface of the contact layer 10 is formed in the laminated insulating film (SiO 2 film 12 and SiN film 14) by, for example, directional dry etching. (FIG. 1C), the resist film 16 is removed (FIG. 1D).

その後、ＳｉＯ２膜１２に対するエッチングレートがＳｉＮ膜１４に対するエッチングレートより高い薬液（ここではフッ酸（フッ化水素：ＨＦ）とする）を用いたウェットエッチングにより、コンタクトホールに露出したＳｉＯ２膜１２の側面をコンタクトホールに露出したＳｉＮ膜１４の側面より所定長だけ後退させる（図１（ｅ））。これにより、コンタクトホールの内側面には、ＳｉＮ膜１４がＳｉＯ２膜１２より所定長だけ突き出した「ひさし部」が形成される。 Thereafter, chemical etching rate for SiO 2 film 12 is higher than the etching rate for the SiN film 14 (here hydrofluoric acid (hydrogen fluoride: HF) to) by wet etching using, SiO 2 film 12 exposed in the contact hole The side surface is retracted by a predetermined length from the side surface of the SiN film 14 exposed in the contact hole (FIG. 1E). As a result, an “eave portion” in which the SiN film 14 protrudes from the SiO 2 film 12 by a predetermined length is formed on the inner side surface of the contact hole.

続いて、積層した２層の絶縁膜（ＳｉＯ２膜１２およびＳｉＮ膜１４）をマスクとして電極材料（チタン、白金、金など）を蒸着することにより、ＳｉＮ膜１４（特に、ひさし部）に当接しない厚さを有する電極層２０−１をコンタクトホールに露出したコンタクト層１０上に形成する（図１（ｆ））。このとき、ＳｉＮ膜１４上にも、電極層２０−１と同様の厚さを有する電極層２０−２が形成されるが、この電極層２０−２は、上記ひさし部によって、コンタクトホール内に形成された電極層２０−１から好適に分離される。 Subsequently, electrode materials (titanium, platinum, gold, etc.) are deposited by using the laminated two insulating films (SiO 2 film 12 and SiN film 14) as a mask, so that the SiN film 14 (especially the eaves portion) is contacted. An electrode layer 20-1 having a thickness that does not contact is formed on the contact layer 10 exposed in the contact hole (FIG. 1 (f)). At this time, an electrode layer 20-2 having the same thickness as the electrode layer 20-1 is also formed on the SiN film 14, and this electrode layer 20-2 is formed in the contact hole by the eaves portion. It is preferably separated from the formed electrode layer 20-1.

ここで、フッ酸を用いてエッチングすれば、電極層２０−１の上面とＳｉＮ膜１４（ひ<さし部）との間からフッ酸が侵入し、ＳｉＮ膜１４がＳｉＯ２膜１２とともに除去（リフトオフ）され、コンタクト層１０上には電極層２０−１だけが残る（図１（ｇ））。 Here, if etching is performed using hydrofluoric acid, hydrofluoric acid enters from between the upper surface of the electrode layer 20-1 and the SiN film 14 (eave portion), and the SiN film 14 is removed together with the SiO 2 film 12. (Lift off), and only the electrode layer 20-1 remains on the contact layer 10 (FIG. 1G).

このように、本実施形態によれば、ＳｉＯ２膜１２（リフトオフ用）およびＳｉＯ２膜１２よりエッチングレートの低いＳｉＯ２膜１４（電極層分離用）を電極蒸着時のマスクとして用いることにより、電極パタンを精度よく形成することができる。 Thus, according to this embodiment, by using the SiO 2 film 12 (for lift-off) and the SiO 2 film 14 (for electrode layer separation) having an etching rate lower than that of the SiO 2 film 12 as a mask during electrode deposition, The electrode pattern can be formed with high accuracy.

さらに、ＳｉＮ膜１４がＳｉＯ２膜１２とともに除去されるため、ＳｉＮ膜１４上に形成された電極層２０−２、すなわち電極が形成される領域以外の領域に形成された電極層を完全に除去することができる。 Further, since the SiN film 14 is removed together with the SiO 2 film 12, the electrode layer 20-2 formed on the SiN film 14, that is, the electrode layer formed in a region other than the region where the electrode is formed is completely removed. can do.

［実施形態２］
本発明の実施形態２に係る電極形成方法を図２に基づいて説明する。 [Embodiment 2]
An electrode forming method according to Embodiment 2 of the present invention will be described with reference to FIG.

本実施形態では、たとえばＣＶＤ法により、コンタクト層１０上に第１の絶縁膜としてＳｉＮ膜１４−１を堆積し、ＳｉＮ膜１４−１上に第２の絶縁膜としてＳｉＯ２膜１２を成長させ、さらにＳｉＯ２膜１２上に第３の絶縁膜としてＳｉＮ膜１４−２を堆積する（図２（ａ））。 In the present embodiment, the SiN film 14-1 is deposited as the first insulating film on the contact layer 10 by, for example, the CVD method, and the SiO 2 film 12 is grown as the second insulating film on the SiN film 14-1. Further, a SiN film 14-2 is deposited as a third insulating film on the SiO 2 film 12 (FIG. 2A).

次に、コンタクト層１０に連絡するコンタクトホールを形成するために、たとえばフォトリソグラフィによって、コンタクトホールに沿う開口を有するレジスト膜１６をＳｉＮ膜１４−２上に形成する（図２（ｂ））。そして、レジスト膜１６をマスクとして、たとえば方向性を有するドライエッチングにより、積層した３層の絶縁膜（ＳｉＮ膜１４−１、ＳｉＯ２膜１２、およびＳｉＮ膜１４−２）に、コンタクト層１０の表面まで貫通するコンタクトホールを形成し（図２（ｃ））、レジスト膜１６を除去する（図２（ｄ））。 Next, in order to form a contact hole communicating with the contact layer 10, a resist film 16 having an opening along the contact hole is formed on the SiN film 14-2 by, for example, photolithography (FIG. 2B). Then, with the resist film 16 as a mask, the contact layer 10 is formed on the laminated three insulating films (SiN film 14-1, SiO 2 film 12, and SiN film 14-2) by, for example, directional dry etching. A contact hole penetrating to the surface is formed (FIG. 2C), and the resist film 16 is removed (FIG. 2D).

その後、ＳｉＯ２膜１２に対するエッチングレートがＳｉＮ膜１４に対するエッチングレートより高い薬液（ここではフッ酸とする）を用いたウェットエッチングにより、コンタクトホールに露出したＳｉＯ２膜１２の側面をコンタクトホールに露出したＳｉＮ膜１４−２の側面より所定長だけ後退させる（図２（ｅ））。これにより、コンタクトホールの内側面には、ＳｉＮ膜１４−２がＳｉＯ２膜１２より所定長だけ突き出した「ひさし部」が形成される。 Thereafter, the side surface of the SiO 2 film 12 exposed to the contact hole is exposed to the contact hole by wet etching using a chemical (here, hydrofluoric acid) having a higher etching rate for the SiO 2 film 12 than the etching rate for the SiN film 14. The SiN film 14-2 is made to recede by a predetermined length from the side surface (FIG. 2E). As a result, an “eave portion” in which the SiN film 14-2 protrudes from the SiO 2 film 12 by a predetermined length is formed on the inner side surface of the contact hole.

続いて、積層した３層の絶縁膜（ＳｉＮ膜１４−１、ＳｉＯ２膜１２、およびＳｉＮ膜１４−２）をマスクとして電極材料（チタン、白金、金など）を蒸着することにより、ＳｉＮ膜１４−２（特に、ひさし部）に当接しない厚さを有する電極層２０−１をコンタクトホールに露出したコンタクト層１０上に形成する（図２（ｆ））。このとき、ＳｉＮ膜１４−２上にも、電極層２０−１と同様の厚さを有する電極層２０−２が形成されるが、この電極層２０−２は、上記ひさし部によって、コンタクトホール内に形成された電極層２０−１から好適に分離される。 Subsequently, an electrode material (titanium, platinum, gold, etc.) is vapor-deposited using the stacked three-layer insulating films (SiN film 14-1, SiO 2 film 12, and SiN film 14-2) as a mask, thereby forming a SiN film. An electrode layer 20-1 having a thickness that does not contact 14-2 (particularly the eaves) is formed on the contact layer 10 exposed in the contact hole (FIG. 2 (f)). At this time, an electrode layer 20-2 having the same thickness as that of the electrode layer 20-1 is also formed on the SiN film 14-2. This electrode layer 20-2 is formed in the contact hole by the eaves portion. It is preferably separated from the electrode layer 20-1 formed therein.

ここで、フッ酸を用いてエッチングすれば、電極層２０−１の上面とＳｉＮ膜１４−２（ひさし部）との間からフッ酸が侵入し、ＳｉＮ膜１４−２がＳｉＯ２膜１２とともに除去（リフトオフ）され、コンタクト層１０上にはＳｉＮ膜１４−１と電極層２０−１だけが残る（図２（ｇ））。 Here, if etching is performed using hydrofluoric acid, hydrofluoric acid enters from between the upper surface of the electrode layer 20-1 and the SiN film 14-2 (eave portion), and the SiN film 14-2 together with the SiO 2 film 12. After removal (lift-off), only the SiN film 14-1 and the electrode layer 20-1 remain on the contact layer 10 (FIG. 2G).

このように、本実施形態によれば、ＳｉＮ膜１４−１（基板保護用）、ＳｉＮ膜１４−１よりエッチングレートの高いＳｉＯ２膜１２（リフトオフ用）、およびＳｉＯ２膜１２よりエッチングレートの低いＳｉＮ膜１４−２（電極層分離用）を電極蒸着時のマスクとして用いることにより、電極パタンを精度よく形成することができる。また、同時に、電極層２０−１が形成される半導体基板の表面をＳｉＮ膜１４−１で保護することができる。 As described above, according to the present embodiment, the SiN film 14-1 (for substrate protection), the SiO 2 film 12 (for lift-off) having a higher etching rate than the SiN film 14-1, and the etching rate higher than that of the SiO 2 film 12 are obtained. By using the low SiN film 14-2 (for electrode layer separation) as a mask during electrode deposition, the electrode pattern can be formed with high accuracy. At the same time, the surface of the semiconductor substrate on which the electrode layer 20-1 is formed can be protected with the SiN film 14-1.

さらに、ＳｉＮ膜１４−２がＳｉＯ２膜１２とともに除去されるため、ＳｉＮ膜１４−２上に形成された電極層２０−２、すなわち電極が形成される領域以外の領域に形成された電極層を完全に除去することができる。 Further, since the SiN film 14-2 is removed together with the SiO 2 film 12, the electrode layer 20-2 formed on the SiN film 14-2, that is, an electrode layer formed in a region other than the region where the electrode is formed. Can be completely removed.

［実施形態３］
本発明の実施形態３に係る電極形成方法を図３に基づいて説明する。 [Embodiment 3]
An electrode forming method according to Embodiment 3 of the present invention will be described with reference to FIG.

本実施形態では、このコンタクト層１０上に第１の絶縁膜としてＳｉＯ２膜１２−１を成長させ、たとえばＣＶＤ法により、ＳｉＯ２膜１２−１上に第２の絶縁膜としてＳｉＮ膜１４−１を堆積し、ＳｉＮ膜１４−１上に第３の絶縁膜としてＳｉＯ２膜１２−２を成長させ、さらにＳｉＯ２膜１２−２上に第４の絶縁膜としてＳｉＮ膜１４−２を堆積する（図３（ａ））。 In the present embodiment, a SiO 2 film 12-1 is grown as a first insulating film on the contact layer 10, and the SiN film 14- is formed as a second insulating film on the SiO 2 film 12-1 by, eg, CVD. 1 is grown, a SiO 2 film 12-2 is grown as a third insulating film on the SiN film 14-1, and a SiN film 14-2 is deposited as a fourth insulating film on the SiO 2 film 12-2. (FIG. 3A).

次に、コンタクト層１０に連絡するコンタクトホールを形成するために、たとえばフォトリソグラフィによって、コンタクトホールに沿う開口を有するレジスト膜１６をＳｉＮ膜１４−２上に形成する（図３（ｂ））。そして、レジスト膜１６をマスクとして、たとえば方向性を有するドライエッチングにより、積層した４層の絶縁膜（ＳｉＯ２膜１２−１、ＳｉＮ膜１４−１、ＳｉＯ２膜１２−２、およびＳｉＮ膜１４−２）に、コンタクト層１０の表面まで貫通するコンタクトホールを形成し（図３（ｃ））、レジスト膜１６を除去する（図３（ｄ））。 Next, in order to form a contact hole communicating with the contact layer 10, a resist film 16 having an opening along the contact hole is formed on the SiN film 14-2 by, for example, photolithography (FIG. 3B). Then, using the resist film 16 as a mask, for example, four layers of insulating films (SiO 2 film 12-1, SiN film 14-1, SiO 2 film 12-2, and SiN film 14 are formed by directional dry etching. -2), a contact hole penetrating to the surface of the contact layer 10 is formed (FIG. 3C), and the resist film 16 is removed (FIG. 3D).

その後、ＳｉＯ２膜１２に対するエッチングレートがＳｉＮ膜１４に対するエッチングレートより高い薬液（ここではフッ酸とする）を用いたウェットエッチングにより、コンタクトホールに露出したＳｉＯ２膜１２−２の側面をコンタクトホールに露出したＳｉＮ膜１４−２の側面より所定長だけ後退させる（図３（ｅ））。これにより、コンタクトホールの内側面には、ＳｉＮ膜１４−２がＳｉＯ２膜１２−２より所定長だけ突き出した「ひさし部」が形成される。なお、このとき、コンタクトホールに露出したＳｉＯ２膜１２−１の側面も、コンタクトホールに露出したＳｉＮ膜１４−１の側面よりほぼ所定長だけ後退する。 Thereafter, the side surface of the SiO 2 film 12-2 exposed to the contact hole is removed by wet etching using a chemical solution (here, hydrofluoric acid) whose etching rate for the SiO 2 film 12 is higher than the etching rate for the SiN film 14. Is retracted by a predetermined length from the side surface of the SiN film 14-2 exposed to the surface (FIG. 3E). Thereby, an “eave portion” in which the SiN film 14-2 protrudes from the SiO 2 film 12-2 by a predetermined length is formed on the inner surface of the contact hole. At this time, the side surface of the SiO 2 film 12-1 exposed in the contact hole also recedes by a predetermined length from the side surface of the SiN film 14-1 exposed in the contact hole.

続いて、積層した４層の絶縁膜（ＳｉＯ２膜１２−１、ＳｉＮ膜１４−１、ＳｉＯ２膜１２−２、およびＳｉＮ膜１４−２）をマスクとして電極材料（チタン、白金、金など）を蒸着することにより、ＳｉＮ膜１４−２（特に、ひさし部）に当接しない厚さを有する電極層２０−１をコンタクトホールに露出したコンタクト層１０上に形成する（図３（ｆ））。このとき、ＳｉＮ膜１４−２上にも、電極層２０−１と同様の厚さを有する電極層２０−２が形成されるが、この電極層２０−２は、上記ひさし部によって、コンタクトホール内に形成された電極層２０−１から好適に分離される。 Subsequently, electrode materials (titanium, platinum, gold, etc.) using the stacked four-layer insulating films (SiO 2 film 12-1, SiN film 14-1, SiO 2 film 12-2, and SiN film 14-2) as a mask. Is deposited on the contact layer 10 exposed to the contact hole (FIG. 3F). The electrode layer 20-1 having a thickness that does not contact the SiN film 14-2 (particularly the eaves) is deposited. ). At this time, an electrode layer 20-2 having the same thickness as that of the electrode layer 20-1 is also formed on the SiN film 14-2. This electrode layer 20-2 is formed in the contact hole by the eaves portion. It is preferably separated from the electrode layer 20-1 formed therein.

ここで、フッ酸を用いてエッチングすれば、電極層２０−１の上面とＳｉＮ膜１４−２（ひさし部）との間からフッ酸が侵入し、ＳｉＮ膜１４−２がＳｉＯ２膜１２−２とともに除去（リフトオフ）され、コンタクト層１０上には、ＳｉＯ２膜１２−１とＳｉＮ膜１４−１と電極層２０−１だけが残る（図３（ｇ））。 Here, if etching is performed using hydrofluoric acid, hydrofluoric acid enters from between the upper surface of the electrode layer 20-1 and the SiN film 14-2 (eave portion), and the SiN film 14-2 becomes the SiO 2 film 12-. 2 is removed (lifted off) together with the SiO 2 film 12-1, the SiN film 14-1, and the electrode layer 20-1 on the contact layer 10 (FIG. 3G).

図４は、本電極形成方法により製造された半導体素子の部分断面図である。この半導体素子は、コンタクト層１０上に形成されたＳｉＯ２膜１２−１と、ＳｉＯ２膜１２−１上に形成されたＳｉＮ膜１４−１と、ＳｉＯ２膜１２−１およびＳｉＮ膜１４−１に形成されたコンタクトホールの内側面とコンタクト層１０の表面とからなる凹状部を、少なくともＳｉＮ膜１４−１の下面を超える高さまで埋める電極層２０−１と、を含んで構成される。 FIG. 4 is a partial cross-sectional view of a semiconductor device manufactured by the present electrode forming method. The semiconductor device includes a SiO 2 film 12-1 formed on the contact layer 10, a SiN film 14-1 formed on the SiO 2 film 12-1, SiO 2 film 12-1 and the SiN film 14 And an electrode layer 20-1 that fills at least the concave portion formed by the inner surface of the contact hole formed in 1 and the surface of the contact layer 10 to a height exceeding the lower surface of the SiN film 14-1.

図４（ａ）〜（ｃ）に示すように、ＳｉＮ膜１４−１の下面と電極層２０−１の上面との距離が異なるいくつかの変形が考えられるが、そのいずれにも共通する点は、電極層２０−１の上面がＳｉＮ膜１４−１の下面を超える位置にある点と、電極層２０−１の外側面に接するＳｉＯ２膜１２−１の側面が電極層２０−１の外側面に接するＳｉＮ膜１４−１の側面より所定長だけ上記凹状部の中央から離れる方向に後退している点である。 As shown in FIGS. 4A to 4C, several variations in which the distance between the lower surface of the SiN film 14-1 and the upper surface of the electrode layer 20-1 can be considered. Shows that the upper surface of the electrode layer 20-1 is located above the lower surface of the SiN film 14-1, and the side surface of the SiO 2 film 12-1 in contact with the outer surface of the electrode layer 20-1 is the electrode layer 20-1. The point is that the SiN film 14-1 in contact with the outer side surface recedes in a direction away from the center of the concave portion by a predetermined length.

このように、本実施形態によれば、ＳｉＯ２膜１２−１（基板保護用）、ＳｉＮ膜１４−１よりエッチングレートの低いＳｉＮ膜１４−１（基板保護用）、ＳｉＮ膜１４−１よりエッチングレートの高いＳｉＯ２膜１２−２（リフトオフ用）、およびＳｉＯ２膜１２−２よりエッチングレートの低いＳｉＮ膜１４−２（電極層分離用）を電極蒸着時のマスクとして用いることにより、電極パタンを精度よく形成することができる。また、同時に、電極層２０−１が形成される半導体基板の表面を、ＳｉＯ２膜１２−１およびＳｉＮ膜１４−１で保護することができる。特に、半導体基板の表面に密着するＳｉＯ２膜１２−１は、その上に形成されたＳｉＮ膜１４−１に比べてエッチングレートが高い、すなわち密度が低く応力が小さいため、半導体基板の表面をより安全に保護することができる。 Thus, according to this embodiment, SiO 2 film 12-1 (substrate protection), lower SiN film etching rate of SiN film 14-1 14-1 (substrate protection), of SiN film 14-1 By using the SiO 2 film 12-2 (for lift-off) with a high etching rate and the SiN film 14-2 (for electrode layer separation) with a lower etching rate than the SiO 2 film 12-2 as a mask during electrode deposition, The pattern can be formed with high accuracy. At the same time, the surface of the semiconductor substrate on which the electrode layer 20-1 is formed can be protected with the SiO 2 film 12-1 and the SiN film 14-1. In particular, since the SiO 2 film 12-1 that adheres to the surface of the semiconductor substrate has a higher etching rate than the SiN film 14-1 formed thereon, that is, the density is low and the stress is small, the surface of the semiconductor substrate is It can be protected more safely.

さらに、ＳｉＮ膜１４−２がＳｉＯ２膜１２−２とともに除去されるため、ＳｉＮ膜１４−２上に形成された電極層２０−２、すなわち電極が形成される領域以外の領域に形成された電極層を完全に除去することができる。 Further, since the SiN film 14-2 is removed together with the SiO 2 film 12-2, the electrode layer 20-2 formed on the SiN film 14-2, that is, formed in a region other than the region where the electrode is formed. The electrode layer can be completely removed.

以上説明した実施形態１〜３によれば、エッチングレートの異なる２層以上の絶縁膜を電極蒸着時のマスクとして用いることにより、電極パタンを精度よく形成することができる。   According to Embodiments 1 to 3 described above, an electrode pattern can be formed with high accuracy by using two or more insulating films having different etching rates as a mask during electrode deposition.

また、電極蒸着時のマスクとして耐熱性の低いレジストを用いないため、電極形成中の基板加熱が可能となる。これにより、電極密度および電極と半導体基板との密着性が高まり、半導体素子の特性および信頼性を向上させることができる。また、半導体基板上に直接レジストマスクを形成しないため、半導体基板（特にコンタクト層）の表面にレジストの一部が除去されずに残ることもない。このため、電極と半導体基板との界面に残渣が介在することによる半導体素子の特性や信頼性の低下を防ぐことができる。   In addition, since a resist having low heat resistance is not used as a mask during electrode deposition, the substrate can be heated during electrode formation. As a result, the electrode density and the adhesion between the electrode and the semiconductor substrate are enhanced, and the characteristics and reliability of the semiconductor element can be improved. Further, since the resist mask is not directly formed on the semiconductor substrate, a part of the resist is not left unremoved on the surface of the semiconductor substrate (particularly, the contact layer). For this reason, it is possible to prevent deterioration of the characteristics and reliability of the semiconductor element due to the presence of residues at the interface between the electrode and the semiconductor substrate.

さらに、仮に半導体基板面に段差が存在していても、電極が形成される領域以外の領域に電極材料が除去されずに残ることはない。   Furthermore, even if there is a step on the surface of the semiconductor substrate, the electrode material does not remain without being removed in a region other than the region where the electrode is formed.

なお、本発明は、上記実施形態に限定されるものではなく、種々の変形実施が可能である。たとえば、絶縁膜にＳｉＯ２膜やＳｉＮ膜以外の絶縁材料を用いてもよいし、絶縁膜のウェットエッチングにフッ酸以外の薬液を用いてもよい。 In addition, this invention is not limited to the said embodiment, A various deformation | transformation implementation is possible. For example, an insulating material other than a SiO 2 film or a SiN film may be used for the insulating film, or a chemical solution other than hydrofluoric acid may be used for wet etching of the insulating film.

また、本発明は、コンタクト層上に電極を形成する場合に限らず、半導体基板の一方面上（表面、裏面、または側面）に電極を形成する場合に広く適用可能である。   Further, the present invention is not limited to the case where the electrode is formed on the contact layer, but can be widely applied to the case where the electrode is formed on one surface (front surface, back surface, or side surface) of the semiconductor substrate.

本発明の実施形態１に係る電極形成方法を示す図である。It is a figure which shows the electrode formation method which concerns on Embodiment 1 of this invention. 本発明の実施形態２に係る電極形成方法を示す図である。It is a figure which shows the electrode formation method which concerns on Embodiment 2 of this invention. 本発明の実施形態３に係る電極形成方法を示す図である。It is a figure which shows the electrode formation method which concerns on Embodiment 3 of this invention. 本発明の実施形態３に係る電極形成方法により製造された半導体素子の部分断面図である。It is a fragmentary sectional view of the semiconductor element manufactured by the electrode formation method concerning Embodiment 3 of the present invention. 従来の電極形成方法の１つ（従来電極形成方法１）を示す図である。It is a figure which shows one (conventional electrode formation method 1) of the conventional electrode formation method. 従来の電極形成方法の１つ（従来電極形成方法２）を示す図である。It is a figure which shows one (conventional electrode formation method 2) of the conventional electrode formation method. 従来電極形成方法１の課題を説明する図である。It is a figure explaining the subject of the conventional electrode formation method 1. FIG. 従来電極形成方法２の課題を説明する図である。It is a figure explaining the subject of the conventional electrode formation method 2. FIG.

符号の説明Explanation of symbols

１０ コンタクト層（半導体基板）、１２ ＳｉＯ２膜（絶縁膜）、１４ ＳｉＮ膜（絶縁膜）、１６，２２，２４ レジスト膜、２０ 電極層（電極材料）。 10 contact layer (semiconductor substrate), 12 SiO 2 film (insulating film), 14 SiN film (insulating film), 16, 22, 24 resist film, 20 electrode layer (electrode material).

Claims (4)

半導体基板の一方面上に第１の絶縁膜を形成する工程と、
前記第１の絶縁膜上に、所定の薬液によるエッチングレートが前記第１の絶縁膜より低い第２の絶縁膜を形成する工程と、
前記第１および第２の絶縁膜に、前記半導体基板の一方面まで貫通する開口部を形成する工程と、
前記所定の薬液を用いたエッチングにより、前記開口部に露出した前記第１の絶縁膜の側面を前記開口部に露出した前記第２の絶縁膜の側面より所定長だけ後退させる工程と、
前記開口部に露出した前記半導体基板の一方面上に、前記第２の絶縁膜に当接しない厚さを有する電極層を蒸着により形成する工程と、
前記所定の薬液を用いたエッチングにより、前記第２の絶縁膜を前記第１の絶縁膜とともに除去する工程と、
を含むことを特徴とする電極形成方法。 Forming a first insulating film on one side of the semiconductor substrate;
Forming a second insulating film on the first insulating film, the etching rate of a predetermined chemical solution being lower than that of the first insulating film;
Forming an opening penetrating to one surface of the semiconductor substrate in the first and second insulating films;
Retreating a side surface of the first insulating film exposed in the opening by a predetermined length from a side surface of the second insulating film exposed in the opening by etching using the predetermined chemical solution;
Forming an electrode layer having a thickness that does not contact the second insulating film on one surface of the semiconductor substrate exposed in the opening by vapor deposition;
Removing the second insulating film together with the first insulating film by etching using the predetermined chemical solution;
An electrode forming method comprising: 半導体基板の一方面上に第１の絶縁膜を形成する工程と、
前記第１の絶縁膜上に、所定の薬液によるエッチングレートが前記第１の絶縁膜より高い第２の絶縁膜を形成する工程と、
前記第２の絶縁膜上に、前記所定の薬液によるエッチングレートが前記第２の絶縁膜より低い第３の絶縁膜を形成する工程と、
前記第１、第２および第３の絶縁膜に、前記半導体基板の一方面まで貫通する開口部を形成する工程と、
前記所定の薬液を用いたエッチングにより、前記開口部に露出した前記第２の絶縁膜の側面を前記開口部に露出した前記第３の絶縁膜の側面より所定長だけ後退させる工程と、
前記開口部に露出した前記半導体基板の一方面上に、前記第３の絶縁膜に当接しない厚さを有する電極層を蒸着により形成する工程と、
前記所定の薬液を用いたエッチングにより、前記第３の絶縁膜を前記第２の絶縁膜とともに除去する工程と、
を含むことを特徴とする電極形成方法。 Forming a first insulating film on one side of the semiconductor substrate;
Forming a second insulating film on the first insulating film, the etching rate of a predetermined chemical solution being higher than that of the first insulating film;
Forming a third insulating film having an etching rate of the predetermined chemical solution lower than that of the second insulating film on the second insulating film;
Forming an opening penetrating to one surface of the semiconductor substrate in the first, second and third insulating films;
Etching with the predetermined chemical solution causes the side surface of the second insulating film exposed in the opening to recede by a predetermined length from the side surface of the third insulating film exposed in the opening;
Forming an electrode layer having a thickness that does not contact the third insulating film on one surface of the semiconductor substrate exposed in the opening by vapor deposition;
Removing the third insulating film together with the second insulating film by etching using the predetermined chemical solution;
An electrode forming method comprising: 半導体基板の一方面上に第１の絶縁膜を形成する工程と、
前記第１の絶縁膜上に、所定の薬液によるエッチングレートが前記第１の絶縁膜より低い第２の絶縁膜を形成する工程と、
前記第２の絶縁膜上に、前記所定の薬液によるエッチングレートが前記第２の絶縁膜より高い第３の絶縁膜を形成する工程と、
前記第３の絶縁膜上に、前記所定の薬液によるエッチングレートが前記第３の絶縁膜より低い第４の絶縁膜を形成する工程と、
前記第１、第２、第３および第４の絶縁膜に、前記半導体基板の一方面まで貫通する開口部を形成する工程と、
前記所定の薬液を用いたエッチングにより、前記開口部に露出した前記第３の絶縁膜の側面を前記開口部に露出した前記第４の絶縁膜の側面より所定長だけ後退させる工程と、
前記開口部に露出した前記半導体基板の一方面上に、前記第４の絶縁膜に当接しない厚さを有する電極層を蒸着により形成する工程と、
前記所定の薬液を用いたエッチングにより、前記第４の絶縁膜を前記第３の絶縁膜とともに除去する工程と、
を含むことを特徴とする電極形成方法。 Forming a first insulating film on one side of the semiconductor substrate;
Forming a second insulating film on the first insulating film, the etching rate of a predetermined chemical solution being lower than that of the first insulating film;
Forming a third insulating film on the second insulating film, the etching rate of the predetermined chemical solution being higher than that of the second insulating film;
Forming a fourth insulating film on the third insulating film, the etching rate of the predetermined chemical solution being lower than that of the third insulating film;
Forming an opening penetrating to one surface of the semiconductor substrate in the first, second, third and fourth insulating films;
Etching with the predetermined chemical solution causes the side surface of the third insulating film exposed in the opening to recede by a predetermined length from the side surface of the fourth insulating film exposed in the opening;
Forming an electrode layer having a thickness that does not contact the fourth insulating film on one surface of the semiconductor substrate exposed in the opening by vapor deposition;
Removing the fourth insulating film together with the third insulating film by etching using the predetermined chemical solution;
An electrode forming method comprising: 半導体基板と、
前記半導体基板の一方面上に形成された第１の絶縁膜と、
前記第１の絶縁層上に形成された、所定の薬液によるエッチングレートが前記第１の絶縁膜より低い第２の絶縁膜と、
前記第１および第２の絶縁膜に形成された前記半導体基板の一方面まで貫通する開口部の内側面と、前記半導体基板の一方面と、からなる凹状部を、少なくとも前記第２の絶縁膜の下面を超える高さまで埋める電極層と、
を含み、
前記電極層の外側面に接する前記第１の絶縁膜の側面は、前記電極層の外側面に接する前記第２の絶縁膜の側面より所定長だけ前記凹状部の中央から離れる方向に後退している、
ことを特徴とする半導体素子。 A semiconductor substrate;
A first insulating film formed on one surface of the semiconductor substrate;
A second insulating film formed on the first insulating layer and having a predetermined chemical etching rate lower than that of the first insulating film;
At least the second insulating film has a concave portion formed by an inner surface of an opening that penetrates to one surface of the semiconductor substrate formed in the first and second insulating films and one surface of the semiconductor substrate. An electrode layer filling up to a height exceeding the lower surface of
Including
The side surface of the first insulating film in contact with the outer surface of the electrode layer recedes in a direction away from the center of the concave portion by a predetermined length from the side surface of the second insulating film in contact with the outer surface of the electrode layer. Yes,
The semiconductor element characterized by the above-mentioned.
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