JP2009302304A - Method of manufacturing semiconductor device - Google Patents

Abstract

In a method of manufacturing a semiconductor device provided with a ferroelectric capacitor, the reliability of the semiconductor device is improved.
A step of forming an insulating film over a semiconductor substrate, a step of forming a first conductive film on the insulating film, and crystallization on the first conductive film. The step of forming the first ferroelectric film 49, the step of performing the first annealing on the first ferroelectric film 49, and the first annealing so that the semiconductor substrate 30 is not exposed to the atmosphere. A step of forming an amorphous second ferroelectric film 50 on the first ferroelectric film 49, and a second conductive film 51 on the second ferroelectric film 50. After forming the second conductive film 51, annealing the second ferroelectric film 50 to crystallize, the first conductive film 48, the first ferroelectric film 49, the second Manufacturing a ferroelectric device having a step of patterning the ferroelectric film 50 and the second conductive film 51 to form a ferroelectric capacitor Q. It depends on the manufacturing method.
[Selection] Figure 25

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, with the advancement of digital technology, there is an increasing demand for electronic devices such as mobile phones to process and store large volumes of data at high speed. Known nonvolatile memories for storing data include DRAM (Dynamic Random Access Memory) and FeRAM (Ferroelectric Random Access Memory).

  Among these, the FeRAM has a ferroelectric capacitor in which a ferroelectric film is formed as a capacitor dielectric film, and stores information by utilizing the spontaneous polarization of the ferroelectric film. This is advantageous in that the operating voltage is low compared to the above, and high-speed operation is possible.

  The FeRAM is also required to have a lower operating voltage. In order to realize a low voltage, there is a method of reducing the polarization inversion voltage of the ferroelectric capacitor by thinning the capacitor dielectric film.

  However, if the capacitor dielectric film is simply thinned and a voltage of the same magnitude as the current state is applied to the ferroelectric capacitor, the strength of the electric field applied to the capacitor dielectric film will be greater than the current state, and the capacitor dielectric There is a possibility that the leakage current in the body membrane increases.

  It is considered that the cause of the leakage current generated in the capacitor dielectric film is mainly a void existing at a crystal grain boundary in the capacitor dielectric film. When the upper electrode is formed on the capacitor dielectric film, it is considered that the material of the upper electrode is buried in the gap and a leak path is formed in the capacitor dielectric film.

  Therefore, by reducing the size of such a gap, it becomes difficult for the material of the upper electrode to enter the gap, and the leakage current of the capacitor dielectric film is reduced.

  In view of this point, a method has been proposed in which a crystallized first ferroelectric film and an amorphous second ferroelectric film are formed in this order, and the laminated film is used as a capacitor dielectric film. (Patent Document 1). In this method, after forming a conductive film for the upper electrode on the second ferroelectric film, crystallization annealing is performed on the amorphous second ferroelectric film, thereby obtaining the second The ferroelectric film is crystallized.

  According to this, since the gap in the first ferroelectric film is filled with the second ferroelectric film, the leakage current generated due to the gap in the first ferroelectric film can be reduced. In addition, since the second ferroelectric film is amorphous when the conductive film for the upper electrode is formed, the material of the conductive film hardly enters the second ferroelectric film. Leakage current in the ferroelectric film can also be reduced.

  Thus, the leakage current is improved by using the capacitor dielectric film having a two-layer structure. However, in order to further improve the reliability of FeRAM, it is necessary to investigate and improve the problems associated with forming the two-layered ferroelectric film.

  For example, after annealing the first ferroelectric film to release impurities such as moisture contained in the first ferroelectric film to the outside, the first ferroelectric film There has also been proposed a method of improving the switching charge amount of the capacitor dielectric film by forming a second ferroelectric film thereon (Patent Document 2).

  However, in this method, when the semiconductor substrate is exposed to the atmosphere between the annealing and the formation of the second ferroelectric film, impurities in the atmosphere are adsorbed on the first ferroelectric film, There is a possibility that the impurity release by annealing cannot be effectively performed.

In addition, a technique related to the present application is also disclosed in Patent Document 3.
JP 2006-318941 A JP 2008-10775 A JP-A-11-54721

  An object of the present invention is to improve the reliability of a semiconductor device in a method of manufacturing a semiconductor device provided with a ferroelectric capacitor.

  According to one aspect of the disclosure below, a step of forming an insulating film over a semiconductor substrate, a step of forming a first conductive film on the insulating film, and a step of forming on the first conductive film, Forming a crystallized first ferroelectric film; performing a first annealing on the first ferroelectric film; and after the first annealing, bringing the semiconductor substrate into the atmosphere. Forming an amorphous second ferroelectric film on the first ferroelectric film so as not to expose; and forming a second conductive film on the second ferroelectric film After forming the second conductive film, annealing the second ferroelectric film to crystallize, the first conductive film, the first ferroelectric film, A method of manufacturing a semiconductor device comprising: a second ferroelectric film; and a step of patterning the second conductive film to form a ferroelectric capacitor There is provided.

  According to the present invention, impurities such as atmospheric moisture contained in the first ferroelectric film are released out of the film by the first annealing. Therefore, it is possible to prevent film peeling from occurring at the interface between the second ferroelectric film and the second conductive film due to this impurity, and it is possible to improve the reliability of the semiconductor device.

(1) Investigation Results Prior to the description of the embodiments of the present invention, the inventor of the present application will explain the investigation regarding ferroelectric capacitors.

  First, a method for preparing a sample used for the investigation will be described.

  1 to 2 are cross-sectional views showing a sample manufacturing method in the order of steps.

  First, as shown in FIG. 1A, a platinum film having a thickness of 150 nm is formed on a silicon substrate 1 by sputtering, and the platinum film is used as a first conductive film 3 for a capacitor lower electrode. .

Then, on the first conductive film 3, the first strength PZT as the dielectric film _{5 (Pb (Zr x, Ti} 1-x) O 3: 0 ≦ x ≦ 1) layer of RF (Radio Frequency) A thickness of about 90 nm is formed by sputtering. The first ferroelectric film 5 formed by sputtering is amorphous immediately after film formation and is not crystallized.

  Therefore, in the next step, as shown in FIG. 1B, the first ferroelectric film 5 is crystallized by annealing. Such annealing is called crystallization annealing, and is performed at a substrate temperature of 575 ° C. in an RTA (Rapid Thermal Anneal) chamber having an oxygen-containing atmosphere. By this crystallization annealing, PZT crystal grains oriented in the (111) direction grow in the film of the first ferroelectric film 5, and the ferroelectric such as the residual polarization charge amount of the first ferroelectric film 5. The characteristics are enhanced.

  Subsequently, as shown in FIG. 1C, a PZT film having a thickness of about 30 nm is formed on the first ferroelectric film 5 by sputtering, and the PZT film is formed as the second ferroelectric film 7. And

  The second ferroelectric film 7 formed by sputtering is not crystallized at the time of film formation and is in an amorphous state. For this reason, crystallization annealing for the second ferroelectric film 7 is necessary in the subsequent process.

  However, when the deposition temperature of the second ferroelectric film 7 is set to a high temperature of 100 ° C. or higher, the orientation of PZT in the second ferroelectric film 7 after the crystallization annealing is random in the (101) direction or the like. The orientation in the (111) direction, which is advantageous for improving the ferroelectric properties, may decrease. Therefore, the deposition temperature of the second ferroelectric film 7 is preferably 150 ° C. or lower, for example, 50 ° C.

  Here, the formation of the second ferroelectric film 7 is ideally performed after the first ferroelectric film 5 is crystallized and annealed (FIG. 1B), and then the first ferroelectric film 7 is formed. It is preferable to carry out without exposing the film 5 to the atmosphere. In this way, impurities such as atmospheric moisture and carbon dioxide are prevented from adsorbing on the surface of the first ferroelectric film 5, and the second ferroelectric film 7 and its It can suppress that adhesiveness with the film | membrane formed later on falls.

  However, in an actual mass production process, a sputtering chamber for forming the second ferroelectric film 7 and an RTA chamber for crystallization annealing may be provided in different semiconductor manufacturing apparatuses. In that case, the silicon substrate 1 must be transferred between the chambers, and the first ferroelectric film 5 is exposed to the atmosphere during the transfer, and impurities in the atmosphere are adsorbed on the surface.

  It is considered that the impurities are separated from the first ferroelectric film 5 to some extent by heat applied to the silicon substrate 1 during manufacture. An example of such heat is heat when the second ferroelectric film 7 is formed.

  However, since the second ferroelectric film 7 is formed at a low temperature of about 50 ° C. as described above, it cannot be expected that the impurities are sufficiently separated when the second ferroelectric film 7 is formed. .

  Therefore, in this example, as shown in FIG. 2A, annealing is performed after the second ferroelectric film 7 is formed. Thereby, the impurities 10 in the atmosphere attached to the surface of the first ferroelectric film 5 are desorbed to the outside through the second ferroelectric film 7, and the second ferroelectric substance is caused by the impurities 10. This prevents the adhesion between the film 7 and a film to be formed later on the film 7 from being lowered.

  This annealing is performed for about 60 seconds at a substrate temperature of 150 ° C. in an annealing chamber in a reduced pressure atmosphere.

  Next, as shown in FIG. 2B, an iridium oxide film having a thickness of about 50 nm is formed on the second ferroelectric film 7 as a second conductive film 9 for the upper electrode by sputtering.

  At the time when the second conductive film 9 is formed, the second ferroelectric film 7 is amorphous and the gap in the film is very small. Therefore, the iridium oxide of the second conductive film 9 enters the gap. It is difficult to prevent a leakage path from being formed in the second ferroelectric film 7 by iridium oxide.

  Thereafter, as shown in FIG. 2C, crystallization annealing is performed on the second ferroelectric film 7 in a state where the second conductive film 9 is formed. The PZT in the second ferroelectric film 7 is crystallized.

  This crystallization annealing is performed for about 120 minutes at a substrate temperature of about 710 ° C. in an RTA chamber having an oxygen-containing atmosphere.

  Further, by performing crystallization annealing in the oxygen-containing atmosphere in this manner, oxygen is supplied to the first and second ferroelectric films 5 and 7 through the second conductive film 9, and these ferroelectric films It is also possible to compensate for oxygen deficiency.

  If this crystallization annealing is performed before the second conductive film 9 is formed, a large gap is formed between the PZT crystal grains in the second ferroelectric film 7, and the second gap is formed in the gap. The iridium oxide of the conductive film 9 enters. Therefore, a leakage path is formed in the second ferroelectric film 7 by the iridium oxide, and the leakage current cannot be reduced.

  Thereafter, as shown in FIG. 3, an iridium oxide film is formed on the second conductive film 9 as a third conductive film 11 for the upper electrode by a sputtering method to a thickness of about 200 nm. The second conductive film 11 constitutes an upper electrode together with the second conductive film 9 and plays a role of increasing the film thickness of the upper electrode.

  Thus, the basic structure of this sample was obtained.

  According to the sample manufacturing method described above, the impurities in the atmosphere contained in the first ferroelectric film 5 are released by the annealing described with reference to FIG. 2A, so that the film peeling due to the impurities is not caused. Should not occur.

  However, when this sample was investigated, many defects were found.

  FIG. 4 is a wafer map obtained by inspecting this sample using a defect inspection apparatus.

  In the drawing, a portion indicated by a black mark represents a defect, and a large number of defects are generated in the silicon substrate 1.

  FIG. 5 is a plan view obtained by observing one of these defects with an SEM (Scanning Electron Microscope).

  As shown, the defect has a circular bulge.

  FIG. 6A is a drawing drawn based on a cross-sectional TEM (Transmission Electron Microscope) image of this defect. Moreover, FIG.6 (b) is an expanded sectional view of Fig.6 (a).

  As shown in FIGS. 6A and 6B, it has been clarified that this defect is film peeling that occurs at the interface between the second ferroelectric film 7 and the second conductive film 9. .

  The inventor of the present application conducted the following investigation in order to investigate the cause of such film peeling despite the annealing shown in FIG.

  FIG. 7 is a cross-sectional view of the sample used in this study.

  As shown in FIG. 7, this sample is obtained by forming a PZT film 21 with a thickness of 120 nm on a silicon substrate 20 by sputtering.

  FIG. 8 is a graph obtained by measuring the amount of water contained in the PZT film 21 by TDS (Thermal Desorption Spectroscopy). The horizontal axis of this graph indicates the substrate temperature during measurement, and the vertical axis indicates the strength of water ions.

  In this investigation, the amount of water in the film was investigated for each of the PZT film 21 that was amorphous immediately after film formation and the PZT film 21 that was crystallized by crystallization annealing.

  As a result, as shown in FIG. 8, it was found that the PZT film 21 crystallized by crystallization annealing has a larger amount of water than the case where it is amorphous immediately after the film formation.

  FIG. 9 is a graph obtained by investigating the amount of carbon dioxide in the membrane by the TDS method for the same sample as FIG. The meanings of the vertical axis and horizontal axis of the graph are the same as those in FIG.

  As shown in FIG. 9, as in the case of water (FIG. 8), in the case of carbon dioxide, the crystallized PZT film 21 has a larger amount of carbon dioxide than in the case of amorphous.

  Thus, more impurities such as water and carbon dioxide are generated from the crystallized PZT film 21 than from the amorphous PZT film 21. This is presumably because the PZT film 21 was crystallized to form larger voids at the PZT crystal grain interface than when amorphous, and impurities in the atmosphere entered the voids.

  On the other hand, in the sample manufacturing method described with reference to FIGS. 1 to 3, the amorphous second ferroelectric film 7 is annealed in the step of FIG. However, the first ferroelectric film 8 in the crystallized state is not annealed in a separate process.

  Therefore, impurities in the atmosphere adsorbed on the first ferroelectric film 8 are not sufficiently desorbed outside the film, and this causes film peeling as shown in FIGS. 6 (a) and 6 (b). It is thought that.

  FIG. 10 is a schematic diagram showing the mechanism of film peeling.

  10, the same elements as those described in FIGS. 1 to 3 are denoted by the same reference numerals as those in FIGS.

  As shown in FIG. 10, after the crystallization annealing is performed on the first ferroelectric film 5, impurities 10 such as moisture and carbon dioxide in the atmosphere are adsorbed on the first ferroelectric film 5. .

  The impurity 10 is desorbed from the first ferroelectric film 5 by heat of crystallization annealing (FIG. 2C) for the second ferroelectric film 7, for example. The detached impurities 10 pass through the second ferroelectric film 7 and reach the lower surface of the second conductive film 9, and the second conductive film 9 and the second ferroelectric film 7 are peeled off. Conceivable.

  Moreover, since the stress of the second conductive film 9 made of iridium oxide is stronger than that of other films, it is considered that this facilitates film peeling.

  In view of such investigation results, the inventor of the present application has conceived an embodiment of the present invention as described below.

(2) First Embodiment FIGS. 11 to 24 are cross-sectional views in the course of manufacturing a semiconductor device according to a first embodiment of the present invention. This semiconductor device is a planar type FeRAM and is manufactured as follows.

  First, steps required until a sectional structure shown in FIG.

  First, a trench for element isolation is formed in an n-type or p-type silicon (semiconductor) substrate 30. Then, an element isolation insulating film 31 is formed in the trench, and the element isolation insulating film 31 defines an active region of the transistor. Such an element isolation structure is called STI (Shallow Trench Isolation), but LOCOS (Local Oxidation of Silicon) may be adopted instead.

  Next, a p-type impurity such as boron is introduced into the active region of the silicon substrate 30 to form a p-well 32, and then the surface of the active region is thermally oxidized to form a thermal oxide film serving as the gate insulating film 33 with about 6 pieces. Form a thickness of ˜7 nm.

  Subsequently, an amorphous silicon film having a thickness of about 50 nm and a tungsten silicide film having a thickness of about 150 nm are sequentially formed on the entire upper surface of the silicon substrate 30. Note that a polycrystalline silicon film may be formed instead of the amorphous silicon film. Thereafter, these films are patterned by photolithography and etching to form the gate electrode 34 on the silicon substrate 30.

  On the p-well 32, two gate electrodes 34 are arranged substantially in parallel with a space therebetween, each of which becomes a part of a word line.

  Next, phosphorus is introduced as an n-type impurity into the silicon substrate 30 beside the gate electrode 34 by ion implantation using the gate electrode 34 as a mask to form first and second source / drain extensions 35a and 35b.

  Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 30, and the insulating film is etched back to leave an insulating spacer 37 beside the gate electrode 34. As the insulating film, a silicon oxide film is formed by, for example, a CVD method.

  Subsequently, n-type impurities such as arsenic are ion-implanted again into the silicon substrate 30 while using the insulating spacers 37 and the gate electrode 34 as a mask, so that the first and second silicon substrates 30 on the side of the gate electrode 34 are first and second-implanted. Two source / drain regions 36a and 36b are formed. Among these, the second source / drain region 36b between the two gate electrodes 34 becomes a part of the bit line.

  Further, a refractory metal film such as a cobalt film is formed on the entire upper surface of the silicon substrate 30 by sputtering. Then, the refractory metal film is heated and reacted with silicon to form a refractory silicide layer 38 such as a cobalt silicide layer on the silicon substrate 30 in the first and second source / drain regions 36a and 36b. The resistance of each source / drain region 36a, 36b is reduced. Such a refractory metal silicide layer is also formed on the surface layer of the gate electrode 34.

  Thereafter, the refractory metal layer which has not reacted on the element isolation insulating film 31 or the like is removed by wet etching.

  Through the steps so far, the MOS transistor TR having the gate insulating film 33, the gate electrode 34, the first and second source / drain regions 36a, 36b, and the like is formed in the active region of the silicon substrate 30. .

  Next, as shown in FIG. 11B, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed on the entire upper surface of the silicon substrate 30 by plasma CVD, and this is used as a cover insulating film 41.

Further, a silicon oxide (SiO ₂ ) film having a thickness of about 1000 nm is formed on the cover insulating film 41 as a first interlayer insulating film 42 by plasma CVD using a TEOS (Tetraethoxysilane) gas. Then, the upper surface of the first interlayer insulating film 42 is polished and planarized by CMP (Chemical Mechanical Polishing), and the thickness of the first interlayer insulating film 42 is set to about 785 nm.

  Subsequently, as shown in FIG. 11C, the cover insulating film 41 and the first interlayer insulating film 42 are patterned by photolithography and etching, and are formed on the first and second source / drain regions 36a, 36. A contact hole 42a is formed.

  Thereafter, as shown in FIG. 12A, first conductive plugs 43 electrically connected to the first and second source / drain regions 36a, 36 are formed in the contact holes 42a.

  In order to form the first conductive plug 43, for example, a titanium film having a thickness of about 30 nm and a titanium nitride film having a thickness of about 20 nm are formed as glue films in this order in the contact hole 42a by the sputtering method. To do. Then, a tungsten film is formed on the glue film by a CVD method to a thickness of about 300 nm, and the contact hole 42a is completely buried with the tungsten film. Thereafter, excess glue film and tungsten film on the first interlayer insulating film 42 are removed by polishing by the CMP method, and these films are left in the contact holes 42 a as the first conductive plugs 43.

  Since the first conductive plug 43 formed in this way is mainly made of tungsten that is easily oxidized, there is a possibility that it will be easily oxidized in an oxygen-containing atmosphere and cause contact failure.

  Therefore, in the next step, as shown in FIG. 12B, the first conductive plug 43 and the first interlayer insulating film 42 are used as an anti-oxidation insulating film 45 that prevents oxidation of the first conductive plug 43. A silicon oxynitride film having a thickness of about 100 nm is formed on each of these by CVD.

  Then, a silicon oxide film having a thickness of about 130 nm is formed on the oxidation-preventing insulating film 45 by a CVD method using TEOS gas, and this silicon oxide film is used as the insulating adhesion film 46.

  Thereafter, the insulating adhesive film 46 is degassed by annealing the insulating adhesive film 46 for 30 minutes in a nitrogen atmosphere at a substrate temperature of about 650 ° C.

  Next, as shown in FIG. 12C, an alumina film is formed on the insulating adhesion film 46 as a lower electrode adhesion film 47 by sputtering to a thickness of about 20 nm. Thereafter, the alumina of the lower electrode adhesion film 47 is sufficiently oxidized by RTA (Rapid Thermal Anneal). The lower electrode adhesion film 47 is formed in order to improve adhesion between a capacitor lower electrode, which will be described later, and the insulating adhesion film 46.

Subsequently, as shown in FIG. 13A, a platinum film is formed to a thickness of about 150 nm as the first conductive film 48 by sputtering. Instead of the platinum film, a single layer film of any one of an iridium film, a ruthenium film, a ruthenium oxide (RuO ₂ ) film, and a SrRuO ₃ film, or a laminated film thereof is formed as the first conductive film 48. Also good.

  Here, since the lower electrode adhesion film 47 is formed in advance before the first conductive film 48 is formed, the adhesion between the first conductive film 48 and the insulating adhesion film 46 is enhanced.

Next, as shown in FIG. 13B, PZT (Pb (Zr _x , Ti _{1−) is formed} as a first ferroelectric film 49 on the first conductive film 48 by RF sputtering using a PZT target. _x ) O ₃ : 0 ≦ x ≦ 1) A film is formed to a thickness of about 90 nm.

  The deposition temperature of the first ferroelectric film 49 is not particularly limited. However, when the film forming temperature is 150 ° C. or higher, the orientation of PZT in the first ferroelectric film 49 after crystallization annealing described later is randomly oriented in the (101) direction, etc. The orientation in the (111) direction, which is advantageous for improvement, may decrease. On the other hand, it is difficult to accurately control the film formation temperature at a low temperature. In view of these, the deposition temperature of the first ferroelectric film 49 is preferably 0 ° C. to 150 ° C., for example, 50 ° C.

Further, the first ferroelectric film 49 is not limited to the PZT film. A film made of a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT may be formed as the first ferroelectric film 49. Further, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and Bi layered compounds such as SrBi ₄ Ti ₄ O ₁₅ The film may be formed as the first ferroelectric film 49.

  Further, the method for forming the first ferroelectric film 49 is not limited to the sputtering method, and the first ferroelectric film 49 may be formed by a sol-gel method or a MOCVD (Metal Organic CVD) method.

  Among these film formation methods, the first ferroelectric film 49 formed by sputtering is not crystallized immediately after the film formation and is amorphous and has poor ferroelectric properties.

  Therefore, in the next step, as shown in FIG. 14A, crystallization annealing is performed on the first ferroelectric film 49 in an oxygen-containing atmosphere, and PZT in the first ferroelectric film 49 is changed. Crystallize.

  The crystallization annealing is performed by RTA in an atmosphere of oxygen and argon adjusted so that the oxygen concentration is 1.25%, the substrate temperature is about 600 ° C., and the processing time is about 90 seconds. .

  In the case where the first ferroelectric film 49 is formed by the MOCVD method, the first ferroelectric film 49 is crystallized at the time of film formation, and thus the above crystallization annealing is not necessary.

  By the way, after the crystallization annealing, the process proceeds to a step of forming a subsequent film on the crystallized first ferroelectric film 49. The film forming chamber for forming the film is used for crystallization annealing. In some cases, it is provided in a semiconductor manufacturing apparatus different from the RTA chamber.

  In that case, it is necessary to remove the silicon substrate 30 from the RTA chamber after the crystallization annealing, transport the silicon substrate 30 in the atmosphere, and transfer it to another semiconductor device.

  At this time, the surface of the first ferroelectric film 49 is exposed to impurities such as moisture and carbon dioxide in the atmosphere, and these impurities penetrate into the film of the first ferroelectric film 49.

  In particular, as described with reference to FIGS. 8 and 9, the PZT film after crystallization absorbs more of these impurities than when it is amorphous. Then, as described with reference to FIG. 10, the film is peeled off in a later process due to the impurities thus absorbed in the film.

  In order to prevent such film peeling, in the present embodiment, as shown in FIG. 14B, first annealing is performed on the first ferroelectric film 49 after being transported in the atmosphere. Then, impurities contained in the first ferroelectric film 49 are desorbed out of the film.

The annealing is performed for about 60 seconds in a reduced pressure atmosphere of about 5 × 10 ⁻⁶ to 1 × 10 ⁻³ Pa, for example. By performing annealing under reduced pressure in this way, impurities in the first ferroelectric film 49 are easily released from the film.

  If the substrate temperature at the time of annealing is too high, it is necessary to wait for a long time until the silicon substrate 30 naturally cools after annealing, resulting in poor mass production efficiency. Therefore, this annealing is preferably performed at a temperature lower than the crystallization temperature (450 ° C.) of the first ferroelectric film 49, for example, a substrate temperature of 350 ° C. or less. In this embodiment, annealing is performed at 150 ° C. for about 60 seconds. I do.

  The annealing chamber is not particularly limited, and a heating chamber such as a degas chamber may be used, or annealing may be performed using a heater stage of a sputtering chamber. When the heater stage is used, it is preferable not to apply sputtering power to the chamber in order to prevent unnecessary film formation on the first ferroelectric film 49 by sputtering. Alternatively, such first annealing may be performed using an RTA chamber or a furnace.

  The annealing atmosphere is not particularly limited, and may be either a non-plasma atmosphere or a plasma atmosphere.

However, if the annealing atmosphere contains hydrogen, the first ferroelectric film 49 is reduced by the hydrogen and the ferroelectric characteristics are deteriorated. Accordingly, in both the non-plasma atmosphere and the plasma atmosphere, it is preferable to use an atmosphere excluding hydrogen, and it is not preferable to use H ₂ plasma or NH ₃ plasma.

Examples of the non-plasma atmosphere from which hydrogen is excluded include Ar, N ₂ , and O ₂ . The non-plasma atmosphere causes less damage to the first ferroelectric film 49 than the plasma atmosphere, and is suitable for the FeRAM manufacturing process.

On the other hand, examples of the plasma atmosphere include O ₂ plasma and N ₂ O plasma.

Among these, annealing by O ₂ plasma is performed using, for example, an ashing chamber for ashing and removing the resist. In this case, the pressure in the chamber is set to 133 Pa, for example.

  In both the non-plasma atmosphere and the plasma atmosphere, if oxygen exists in the atmosphere, oxygen deficiency in the first ferroelectric film 49 can be compensated by oxygen, and the advantage that the ferroelectric characteristics are improved is obtained. It is done.

  After annealing in this manner, in order to prevent re-adsorption of impurities in the atmosphere to the first ferroelectric film 49, the next process is performed without exposing the first ferroelectric film 49 to the atmosphere. I do.

  In the present embodiment, the silicon substrate 30 is transferred to an RF sputtering chamber provided in the same semiconductor manufacturing apparatus as the annealing chamber used for performing the first annealing on the first ferroelectric film 49. Since the RF sputtering chamber is provided in the same semiconductor device as the annealing chamber, the first ferroelectric film 49 is not exposed to the atmosphere and does not absorb impurities.

  Then, as shown in FIG. 15A, a PZT film having a thickness of about 10 to 30 nm is formed on the first ferroelectric film 49 using the RF sputtering chamber. The ferroelectric film 50 is used.

  If the thickness of the second ferroelectric film 50 is too thick, the residual polarization charge (QSW) of the first and second ferroelectric films 49 and 50 decreases, so the first ferroelectric film It is preferable to form the second ferroelectric film 50 to a thickness of 40% or less of the film 49.

The second ferroelectric film 50 is not limited to a PZT film. A film made of a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT may be formed as the second ferroelectric film 50. Further, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and Bi layered compounds such as SrBi ₄ Ti ₄ O ₁₅ The film may be formed as the second ferroelectric film 50.

  As described above, PZT formed by sputtering is not crystallized immediately after film formation. Therefore, at this time, the second ferroelectric film 50 is in an amorphous state.

  Similarly to the first ferroelectric film 49, the second ferroelectric film 50 is formed at a low substrate temperature of about 0 ° C. to 150 ° C., so that the second strong film after crystallization annealing described later is formed. It is preferable to align the PZT orientation of the dielectric film 50 in the (111) direction.

  When the second ferroelectric film 50 is formed at a temperature close to 150 ° C. within the range of 0 ° C. to 150 ° C., heat is applied to the first ferroelectric film 49 at the time of film formation. Therefore, even if the first annealing of FIG. 14B is omitted, impurities are desorbed to some extent from the first ferroelectric film 49 in this step. Therefore, in order to effectively remove impurities by the first annealing, the substrate temperature at the time of annealing is set to a temperature higher than the substrate temperature at the time of forming the second ferroelectric film 50, for example, 150 ° C. or more. Is preferred.

  However, if the substrate temperature is set to 100 ° C. or more, which is the boiling point of water, in a reduced pressure atmosphere, it is considered that moisture and organic substances are sufficiently desorbed from the first ferroelectric film 49. Therefore, the first annealing is performed in the reduced pressure atmosphere. When performing, the substrate temperature at that time may be 100 ° C. or higher.

  After forming the second ferroelectric film 50 in this way, the process proceeds to a step of forming a second conductive film for the upper electrode thereon.

  However, the chamber for forming the second conductive film may be provided in a semiconductor manufacturing apparatus different from the chamber used for forming the second ferroelectric film 50 described above. In this case, after forming the second ferroelectric film 50, it is necessary to transport the silicon substrate 30 in the atmosphere and transfer it to the semiconductor manufacturing apparatus.

  For this reason, the second ferroelectric film 50 absorbs impurities in the air during the conveyance, and there is a possibility that film peeling may occur due to the impurities.

  Therefore, in this embodiment, as shown in FIG. 15B, after the silicon substrate 30 is transferred to the semiconductor manufacturing apparatus for forming the second conductive film, the annealing provided in the semiconductor manufacturing apparatus is performed. Second annealing is performed on the second ferroelectric film 50 using the chamber. Thereby, impurities such as moisture and carbon dioxide contained in the second ferroelectric film 50 are desorbed outside the film, and film peeling due to the impurities can be prevented.

As conditions for the second annealing, conditions similar to those for the first annealing for the first ferroelectric film 49 can be adopted. For example, this annealing can be performed in a reduced pressure atmosphere of about 5 × 10 ⁻⁶ to 1 × 10 ⁻³ Pa with a treatment time of about 60 seconds.

  If the substrate temperature during the second annealing is higher than the crystallization temperature (450 ° C.) of the second ferroelectric film 50, the second ferroelectric film 50 is crystallized by the second annealing, Voids are formed at the crystal grain boundaries. However, if the material of the upper electrode is buried in the gap later, a leak path is formed, and the leak current of the second ferroelectric film 50 increases.

  Therefore, the substrate temperature during the second annealing is preferably lower than the crystallization temperature of the second ferroelectric film 50, for example, 350 ° C. or less.

  On the other hand, if the substrate temperature is too low, the effect of impurity desorption cannot be obtained. Therefore, the second annealing is preferably performed at a substrate temperature of 100 ° C. or higher.

Atmosphere of the second annealing is not particularly limited, Ar, N _2, and any non-plasma atmosphere O _2, or in an atmosphere of O ₂ plasma or N ₂ O plasma may perform this anneal.

  Further, the annealing chamber is not particularly limited, and a heating chamber such as a degas chamber may be used, or annealing may be performed using a heater stage of a sputtering chamber. Alternatively, annealing may be performed using an RTA chamber or a furnace.

  Thereafter, as shown in FIG. 16A, the amorphous second ferroelectric film 50 is formed in a sputtering chamber provided in the same semiconductor manufacturing apparatus as the annealing chamber in which the second annealing is performed. A second conductive film 51 for the upper electrode is formed thereon by sputtering.

  As described above, since the same semiconductor manufacturing apparatus as in the second annealing is used, the second ferroelectric film 50 is not exposed to the atmosphere before the second conductive film 51 is formed. Therefore, the impurities in the atmosphere are not absorbed by the second ferroelectric film 50, and it is possible to secure the actual benefit of the second annealing performed to remove the impurities first.

  However, even if the second ferroelectric film 50 is exposed to the atmosphere, if the film peeling due to the impurities incorporated in the film does not occur remarkably, the silicon substrate 30 is transported in the atmosphere and the second annealing is performed. The second conductive film 51 may be formed in a different semiconductor manufacturing apparatus.

  As the second conductive film 51, for example, an iridium oxide film having a thickness of about 50 nm can be formed by sputtering an iridium target in a mixed atmosphere of argon gas and oxygen gas.

  The film formation temperature of the second conductive film 51 affects both the residual polarization charge amount and the leakage current of the first and second ferroelectric films 49 and 50.

  For example, as the film forming temperature of the second conductive film 51 increases, the leakage current increases while the residual polarization charge amount increases. On the contrary, when the film forming temperature is lowered, the leakage current is reduced and the residual polarization charge amount is increased.

  The film formation temperature of the second conductive film 51 is determined depending on which of the residual polarization charge amount and the leakage current is prioritized. In the present embodiment, priority is given to the reduction of leakage current, and the second conductive film 51 is formed at a film formation temperature of about room temperature (20 ° C.).

  As described above, since the upper limit of the substrate temperature in the second annealing (FIG. 15B) is lowered to 350 ° C., the room temperature suitable for the film formation temperature of the second conductive film 51 after the annealing is suitable for the silicon substrate 30. Therefore, it does not take a long time to naturally cool the semiconductor device, and it is possible to prevent a decrease in mass production efficiency of the semiconductor device.

  Subsequently, as shown in FIG. 16B, crystallization annealing is performed on the amorphous second ferroelectric film 50 in an oxygen-containing atmosphere, so that PZT in the second ferroelectric film 50 is obtained. Is crystallized, and the crystallinity of the first ferroelectric film 49 thereunder is further enhanced.

  The conditions for this crystallization annealing are not particularly limited, but in this embodiment, the substrate temperature is about 710 ° C. and the processing time is 120 seconds. Furthermore, as the annealing atmosphere, a mixed atmosphere of oxygen gas and argon gas whose oxygen concentration is adjusted to 1% by flow rate ratio is used.

  Since the second ferroelectric film 50 is not crystallized and is amorphous at the initial stage of the crystallization annealing, iridium oxide of the second conductive film 51 becomes a grain boundary of the second ferroelectric film 50. Difficult to spread. Thereby, it is possible to suppress the occurrence of a leak path in the second ferroelectric film 50 due to the diffused iridium oxide.

  In this embodiment, in the steps of FIGS. 14B and 15B, the first ferroelectric film 49 is annealed to previously desorb impurities contained in the film. I was allowed to. Therefore, when the crystallization annealing is performed on the second ferroelectric film 50, the second ferroelectric film 50 and the second conductive film 51 are prevented from peeling off due to the impurities described above. Is possible.

  Furthermore, this crystallization annealing also provides an advantage that oxygen in the annealing atmosphere is supplied to the second ferroelectric film 50 through the second conductive film 51, and oxygen vacancies in the second ferroelectric film 50 are compensated. can get. In order to obtain such advantages, the thickness of the second conductive film 51 is preferably as thin as possible so that oxygen can easily permeate, for example, 10 to 100 nm.

  However, if the thin second conductive film 51 is formed on the second ferroelectric film 50 in this way, damage in the subsequent etching process cannot be absorbed by the second conductive film 51 alone, and the first In addition, the second ferroelectric films 49 and 50 may be deteriorated.

  Therefore, in the next step, as shown in FIG. 17A, a conductive protective film 52 for protecting the first and second ferroelectric films 49 and 50 is formed on the second conductive film 51. Then, an iridium oxide film having a thickness of about 200 nm is formed by sputtering.

  Thereafter, the PZT adhering to the back surface of the silicon substrate 30 when the first and second ferroelectric films 49 and 50 are formed is cleaned and removed.

  Subsequently, as shown in FIG. 17B, a titanium nitride film is formed to a thickness of about 34 nm as a hard mask 53 by sputtering.

  This titanium nitride film can be formed, for example, by sputtering a titanium target in a mixed atmosphere of argon gas having a substrate temperature of 200 ° C. and a flow rate of 30 sccm and a nitrogen gas having a flow rate of 90 nm.

  The hard mask 53 is not limited to the titanium nitride film, and a hard film made of any of TaN, TiON, TiOx, TaOx, TaON, TiAlOx, TaAlOx, TiAlON, TaAlON, TiSiON, TaSiON, TiSiOx, AlOx, and ZrOx is hard. A mask 53 may be formed.

  Thereafter, a photoresist is applied on the hard mask 53, and is exposed and developed to form a first resist pattern 57.

  Next, as shown in FIG. 18A, the hard mask 53 is patterned in an island shape using the first resist pattern 57 as a mask.

  Then, as shown in FIG. 18B, the second conductive film 51 and the conductive protective film 52 are dry-etched using the island-shaped hard mask 53 as a mask, and these films 51 remaining without being etched. , 52 are upper electrodes 63.

  By using the hard mask 53 in this manner, these films can be patterned more finely than when the films 51 and 52 are etched only by the first resist pattern 57.

  Thereafter, the first resist pattern 57 is removed, and the hard mask 53 is further removed by dry etching.

  Next, as shown in FIG. 19A, in order to recover the damage received by the first and second ferroelectric films 49 and 50 in the steps so far, the ferroelectric films 49 and 50 are formed on the ferroelectric films 49 and 50. On the other hand, annealing is performed in an oxygen-containing atmosphere.

  Such annealing is called recovery annealing, and in this embodiment is performed at a substrate temperature of 600 to 700 ° C., for example, 650 ° C., for about 40 minutes.

  Next, as shown in FIG. 19B, a photoresist is applied to the entire upper surface of the silicon substrate 30, and is exposed and developed to form a second resist pattern 58.

  Then, as shown in FIG. 20A, the first and second ferroelectric films 49 and 50 are dry-etched using the second resist pattern 58 as a mask. As a result, a capacitor dielectric film 62 having these ferroelectric films 49 and 50 is formed under the upper electrode 63.

  Thereafter, the second resist pattern 58 is removed.

  Note that recovery annealing may be performed on the capacitor dielectric film 62 after the second resist pattern 58 is removed. The recovery annealing is performed in an oxygen-containing atmosphere at a substrate temperature of 300 to 400 ° C. and a processing time of 30 to 120 minutes.

  Next, as shown in FIG. 20B, an alumina film is formed on each of the first conductive film 48, the capacitor dielectric film 62, and the upper electrode 63 by a CVD method or a sputtering method to a thickness of about 20 to 50 nm. The alumina film is used as a first hydrogen barrier insulating film 65.

  The first hydrogen barrier insulating film 65 prevents reducing substances such as hydrogen and moisture from entering the capacitor dielectric film 62, and the capacitor dielectric film 62 is reduced and deteriorated by these substances. Play a role to prevent.

  Then, recovery annealing is performed on the capacitor dielectric film 62 at a substrate temperature of 400 to 600 ° C. and a processing time of about 30 to 120 minutes in an oxygen-containing atmosphere.

  Thereafter, a photoresist is applied on the first hydrogen barrier insulating film 65, and is exposed and developed to form a third resist pattern 66.

  Next, as shown in FIG. 21A, the first hydrogen barrier insulating film 65 and the first conductive film 48 are dry-etched using the third resist pattern 66 as a mask to form the capacitor dielectric film 62. A lower electrode 61 is formed below.

  In this dry etching, the portion of the lower electrode adhesion film 47 not covered with the lower electrode 61 is also etched away.

  Then, after removing the third resist pattern 66, recovery annealing is performed on the capacitor dielectric film 62 under conditions of a substrate temperature of 300 to 400 ° C. and a processing time of 30 to 60 minutes.

  Through the steps so far, the ferroelectric capacitor Q having the lower electrode 61, the capacitor dielectric film 62, and the upper electrode 63 is formed in the cell region of the silicon substrate 30.

  Next, as shown in FIG. 21B, an alumina film is formed to a thickness of about 20 nm on the entire upper surface of the silicon substrate 30 by sputtering or CVD, and the alumina film is used as the second hydrogen barrier insulating film 70. .

  Similar to the first hydrogen barrier insulating film 65, the second hydrogen barrier insulating film 70 plays a role of protecting the capacitor dielectric film 62 from reducing substances such as hydrogen and moisture.

  Thereafter, recovery annealing is performed on the capacitor dielectric film 62 under conditions where the substrate temperature is 500 to 700 ° C. and the processing time is 30 to 60 minutes in an oxygen-containing atmosphere. By such recovery annealing, oxygen in the capacitor dielectric film 62 is supplemented by oxygen in the annealing atmosphere, and the ferroelectric characteristics of the capacitor dielectric film 62 are recovered.

  Next, steps required until a sectional structure shown in FIG.

  First, a silicon oxide film having a thickness of about 1400 nm is formed on the second hydrogen barrier insulating film 70 as the second interlayer insulating film 71 by plasma CVD using TEOS gas.

Then, the upper surface of the second interlayer insulating film 71 is polished and flattened by the CMP method, and then the second interlayer insulating film 71 is dehydrated by N ₂ O plasma treatment or N ₂ plasma treatment, and the upper surface thereof is removed. Nitrid to prevent moisture re-adsorption.

  The conditions for this dehydration treatment are not particularly limited, but for example, the substrate temperature is about 350 ° C. and the treatment time is about 2 minutes.

  Next, an alumina film having a thickness of about 20 to 50 nm is formed on the second interlayer insulating film 71 as the third hydrogen barrier insulating film 72 by sputtering or CVD.

  Further, a silicon oxide film having a thickness of about 20 to 50 nm is formed on the third hydrogen barrier insulating film 72 by a plasma CVD method using TEOS gas, and this silicon oxide film is used as a cap insulating film 73.

  Next, as shown in FIG. 22B, the insulating films 45, 46, 65, and 70 to 73 are dry-etched by photolithography and etching. As a result, a first hole 71a is formed on the first conductive plug 43, and second and third holes 71b and 71c are formed on the upper electrode 63 and the lower electrode 61 of the capacitor Q, respectively. Is done.

  Thereafter, recovery annealing is performed in an oxygen-containing atmosphere at a substrate temperature of 400 to 600 ° C. and a processing time of 30 to 120 minutes. This recovery annealing compensates for oxygen vacancies in the capacitor dielectric film 62 and restores the ferroelectric characteristics of the capacitor dielectric film 62.

  Note that this recovery annealing may be performed in an ozone atmosphere instead of the oxygen-containing atmosphere.

  Next, as shown in FIG. 23A, a titanium nitride film as a glue film 75 is formed to a thickness of about 50 to 150 nm on the inner surfaces of the holes 71a to 71c and the upper surface of the cap insulating film 73 by sputtering.

  Here, the first hole 71a on the first conductive plug 43 has a higher aspect ratio than the other holes 71b and 71c. Therefore, it is preferable to form the glue film 75 by a sputtering method capable of forming a film with good coverage in a hole having a high aspect ratio, such as a sputtering method using SIP (Self Ionized Plasma) technology.

  Note that before the glue film 75 is formed, the second interlayer insulating film 71 may be annealed and degassed in an inert atmosphere or a reduced pressure atmosphere. Furthermore, the natural oxide film on the upper surface of the first conductive plug 43 may be removed by RF etching the inner surfaces of the holes 71a to 71c after the degassing.

  The glue film 75 is not limited to a titanium nitride film. Instead of titanium nitride film, TaN, CrN, HfN, ZrN, TiAlN, TaAlN, TiSiN, TaSiN, CrAlN, HfAlN, ZrAlN, TiON, TaON, CrON, HfON, ZrON, TiAlON, TaAlON, CrAlON, HfAlON, ZrAlON, TiSiON A film made of any of TaSiON, Ir, Ru, IrOx, and RuOx may be formed as the glue film 75. Further, a laminated film of a Ti film and a TiN film, a laminated film of a Ti film and a TaN film, a laminated film of a Ta film and a TiN film, or a laminated film of a Ta film and a TaN film may be formed as the glue film 75. Good.

  Next, steps required until a sectional structure shown in FIG.

  First, a tungsten film 76 having a thickness of about 300 nm is formed on the glue film 75 by a CVD method, and the holes 71a to 71c are completely filled with the tungsten film. Instead of the tungsten film 76, a polysilicon film may be formed.

  Then, excess tungsten film 76 and glue film 75 on cap insulating film 73 are removed by polishing with CMP, and these films are left as second conductive plugs 77 only in holes 71a to 71c.

  Thereafter, the natural oxide film on the upper surface of the second conductive plug 77 is removed by etching using argon plasma.

  Next, as shown in FIG. 24, a metal laminated film is formed on the second conductive plug 77 and the cap insulating film 73, and this metal laminated film is patterned to form a first metal wiring 78.

  As the metal laminated film, for example, a titanium nitride film having a thickness of about 50 nm, a copper-containing aluminum film having a thickness of about 550 nm, a titanium film having a thickness of about 5 nm, and a titanium nitride film having a thickness of about 50 nm are formed in this order by sputtering. Form.

  Further, on this first layer metal wiring 78, as shown in the figure, third to sixth interlayer insulating films 83 to 86 and second to fifth layer metal wirings 79 to 82 are alternately laminated to form a multilayer wiring structure. Form.

  Then, a first passivation film 87 made of silicon oxide and a second passivation film 88 made of silicon nitride are formed in this order on the uppermost fifth-layer metal wiring 82.

  Thereafter, a polyimide coating film is formed on the second passivation film 88 and thermally cured to form a protective insulating film 89.

  Thus, the basic structure of the semiconductor device according to this embodiment is completed.

  FIG. 25 is a flowchart showing the main steps of the manufacturing process of the semiconductor device described above.

  As shown in this, in the present embodiment, an amorphous first ferroelectric film 49 is formed in step S1 (FIG. 13B), and the first ferroelectric is formed by crystallization annealing in step S2. The body film 49 is crystallized (FIG. 14A). If the first ferroelectric film 49 that has already been crystallized at the time of film formation is formed by the MOCVD method, step S2 is not necessary.

  In step S3, the first annealing is performed on the crystallized first ferroelectric film 49 (FIG. 14B), so that the first ferroelectric film 49 absorbs the air in the atmosphere. Remove impurities such as moisture and carbon dioxide.

  Thereafter, the process proceeds to step S4, and an amorphous second ferroelectric film 50 is formed on the first ferroelectric film 49 (FIG. 15A).

  Steps S3 and S4 are continuously processed by using the same semiconductor manufacturing apparatus, and the first ferroelectric film 49 is not exposed to the atmosphere between the steps.

  Next, the process proceeds to step S5, where the amorphous second ferroelectric film 50 is annealed (FIG. 15B), so that it remains in the first and second ferroelectric films 49 and 50. To remove impurities in the atmosphere.

  Then, the process proceeds to step S6, and the second conductive film 51 is formed on the second ferroelectric film 50 (FIG. 16A).

  Steps S5 and S6 are continuously processed by using the same semiconductor manufacturing apparatus, and the second ferroelectric film 50 is not exposed to the atmosphere between the steps.

  Thereafter, crystallization annealing is performed on the second ferroelectric film 50 in step S7 (FIG. 16B).

  Thus, in the present embodiment, in step S3 (FIG. 14B), impurities in the atmosphere adsorbed on the crystallized first ferroelectric film 49 are desorbed by the first annealing. Thereby, in the crystallization annealing in step S7 (FIG. 16B), film peeling occurs at the interface between the second ferroelectric film 50 and the second ferroelectric film 51 due to the impurities. Can be prevented. As a result, the number of defects due to film peeling can be reduced, and the reliability of the semiconductor device can be improved.

  By the way, as the annealing for desorbing impurities, in addition to the first annealing in step S3 (FIG. 14B), there is also the second annealing in step S5 (FIG. 15B).

  As described above, the first annealing is performed on the crystallized first ferroelectric film 49. The second annealing is performed on the amorphous second ferroelectric film 50.

  The inventor of the present application conducted the following investigation as to which of these annealings is effective in reducing defects.

  FIG. 26 is a graph obtained by investigating the number of defects due to film peeling in the plane of 25 silicon substrates 30.

  The horizontal axis of the figure shows the number of the wafer (silicon substrate) in one lot. The vertical axis indicates the number of defects due to film peeling.

  Here, neither the first annealing shown in FIG. 14B nor the second annealing shown in FIG. 15B was performed on the wafer shown by the hatched graph.

  On the other hand, only the second annealing was performed on the graph without hatching, and the first annealing was not performed.

  For any of the 25 wafers, after the crystallization annealing is performed on the first ferroelectric film 49 as shown in FIG. The second ferroelectric film 50 was formed after the time exposure to the atmosphere. Then, after forming the second ferroelectric film 50, the silicon substrate 30 was left in the atmosphere for one day.

  As a result, as shown in FIG. 26, a wafer that does not undergo either of the two annealings has many defects due to film peeling, and some of the wafers have more than 300 defects in the plane. is there.

  On the other hand, the number of defects is reduced in the wafer subjected to the second annealing (FIG. 15B) for the amorphous second ferroelectric film 50 as compared with the case where the annealing is not performed.

  Table 1 below is a table obtained by calculating the average value and standard deviation (σ) of the number of defects in the wafer surface based on this investigation.

これに示されるように、非晶質の第２の強誘電体膜５０に対してアニールを行うことで、アニールをしない場合よりも欠陥数の平均値が少なくなる。

As shown in the figure, by performing the annealing on the amorphous second ferroelectric film 50, the average number of defects is reduced as compared with the case where the annealing is not performed.

  However, even if the second annealing is performed, an average of 13.4 defects are generated per sheet, and the defects cannot be sufficiently reduced by this annealing alone.

  FIG. 27 is a wafer map of wafer number 11 among the wafers investigated in FIG. In this wafer map, black marks indicate defects due to film peeling.

  This wafer is obtained by subjecting the amorphous second ferroelectric film 50 to the second annealing, but has a defect at the center of the wafer.

  FIG. 28 is a planar image obtained by observing one of the defects by SEM. As shown in the figure, this defect is a film bulge caused by film peeling.

  On the other hand, FIG. 29 shows the first annealing (FIG. 14B) for the crystallized first ferroelectric film 49 and the amorphous second ferroelectric film 50 as in the present embodiment. 16 is a wafer map when both of the second annealing (FIG. 15B) are performed.

  In this investigation, after the crystallization annealing is performed on the first ferroelectric film 49 as shown in FIG. 14A, the first ferroelectric film 49 is exposed to the atmosphere for three days, and thereafter, FIG. The first annealing of (b) was performed. Then, after the first annealing, a second ferroelectric film 50 is formed, and after the silicon substrate 30 is once exposed to the atmosphere, the second ferroelectric film 50 is further formed with respect to the second ferroelectric film 50 as shown in FIG. A second anneal was performed.

  As shown in FIG. 29, when both the first annealing and the second annealing were performed, defects due to film peeling did not occur in the wafer surface.

  From this result, it was confirmed that the first annealing (FIG. 14B) for the crystallized first ferroelectric film 49 is effective in preventing film peeling.

  As described with reference to FIG. 8 and FIG. 9, the crystallized PZT is easier to absorb impurities in the atmosphere than the amorphous PZT. It is presumed that the annealing is promoted to remove impurities.

  Therefore, the second annealing (FIG. 15B) for the amorphous second ferroelectric film 50 is omitted, and the first annealing for the crystallized first ferroelectric film 49 (FIG. 14B). )) Alone, it is expected that defects due to film peeling can be reduced to some extent.

  Next, a modification of this embodiment will be described.

First Modification FIG. 30 is a flowchart according to a first modification of the present embodiment.

  In FIG. 30, the same steps as those in FIG. 25 are denoted by the same reference numerals as those in FIG. 25, and description thereof will be omitted below.

  In the present modification, step S8 of washing the surface of the crystallized first ferroelectric film 49 with water is performed before the above-described step S3. The rest is the same as in the first embodiment.

  By such washing with water, impurities in the air adhering to the surface of the first ferroelectric film 49 are washed, and film peeling due to the impurities can be further suppressed.

  The method of washing with water is not particularly limited, and a batch-type washing apparatus that immerses a plurality of silicon substrates 30 in a liquid tank in which pure water is stored may be used, or silicon rotating on a spinner A single wafer cleaning apparatus that drops pure water onto the substrate 30 for cleaning may be used.

  When a batch type cleaning apparatus is used, the immersion time of the silicon substrate 30 in pure water is, for example, 30 seconds.

  Further, after washing with water in this way, the first ferroelectric film 49 is dried in an atmosphere containing, for example, IPA (isopropyl alcohol). Such a drying method is also called IPA drying. Instead of IPA drying, natural drying in the air or heat drying in which the silicon substrate 30 is heated to 150 ° C. in the air may be performed. Further, before drying, a brush scrubber process may be performed in which water remaining on the first ferroelectric film 49 is scraped off with a brush.

Second Modification FIG. 31 is a flowchart according to a second modification of the present embodiment.

  In FIG. 31, the same steps as those in FIG. 25 are denoted by the same reference numerals as those in FIG. 25, and description thereof will be omitted below.

  In this modification, all of steps S3, S4, and S6 are continuously processed in the same semiconductor device, so that the silicon substrate 30 is not exposed to the atmosphere between these steps.

  In this case, since the second ferroelectric film 50 formed in step S4 is not exposed to the atmosphere, impurities in the atmosphere are not absorbed by the second ferroelectric film 50. Therefore, step S5 performed in the first embodiment for removing impurities in the second ferroelectric film 50 by the second annealing is not necessary, and the process can be simplified as compared with the first embodiment. .

(3) Second Embodiment In the first embodiment, the planar type FeRAM has been described.

  On the other hand, in this embodiment, a stack type FeRAM in which a conductive plug is formed immediately below the lower electrode will be described. The stack type FeRAM has a smaller capacitor occupation area than the planar type, and is advantageous for high integration.

  32 to 43 are cross-sectional views of the semiconductor device according to the first embodiment of the present invention during manufacture. In these drawings, the same elements as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted below.

  This semiconductor device is manufactured as follows.

  First, as shown in FIG. 32A, according to the steps of FIGS. 11A and 11B of the first embodiment, a MOS transistor TR is formed on the silicon substrate 30, and the MOS transistor TR is covered with a cover insulating film. 41 and a first interlayer insulating film 42.

  Next, as shown in FIG. 32B, contact holes are formed in the insulating films 41 and 42 by photolithography and etching, and a first conductive plug 43 is formed therein.

  As described in the first embodiment, the first conductive plug 43 has tungsten as a main component, and easily oxidizes in an oxygen-containing atmosphere to easily cause a contact failure.

  Therefore, in the next step, as shown in FIG. 32C, a silicon oxynitride film is formed to a thickness of about 130 nm by the CVD method as the anti-oxidation insulating film 92 for preventing the first conductive plug 43 from being oxidized. .

  Note that a silicon nitride film or an alumina film may be formed as the antioxidant insulating film 92 instead of the silicon oxynitride film.

  Further, a silicon oxide film having a thickness of about 300 nm is formed on the oxidation-preventing insulating film 92 by plasma CVD using TEOS gas, and this silicon oxide film is used as a second interlayer insulating film 93.

  Then, a first hole 93a is formed in each of the insulating films 92 and 93 above the first source / drain region 36a by photolithography and etching, and is electrically connected to the first conductive plug 43. Two conductive plugs 91 are formed in the first contact hole 93a.

  The method for forming the second conductive plug 91 is not particularly limited.

  In the present embodiment, a titanium nitride film and a tungsten film are formed in this order on the upper surface of the second interlayer insulating film 93 and the inner surface of the first hole 93a, and these are polished by the CMP method to be in the first hole 93a. Is left as the second conductive plug 91 only.

  In the CMP, a slurry in which the polishing rate of the titanium nitride film and the tungsten film to be polished is higher than the polishing rate of the second interlayer insulating film 93, for example, SSW2000 manufactured by Cabot Microelectronics Corporation is used. In order not to leave a polishing residue on the second interlayer insulating film 93, the CMP polishing amount is set to be larger than the total thickness of the titanium nitride film and the tungsten film, and this CMP is over-polished. .

  As a result, the height of the upper surface of the second conductive plug 91 becomes lower than that of the second interlayer insulating film 93, and a recess is formed in the second interlayer insulating film 93 around the second conductive plug 91. Sometimes formed. The depth of the recess is 20 to 50 nm, typically about 50 nm.

Next, as shown in FIG. 33A, NH ₃ plasma treatment is performed on the surface of the second interlayer insulating film 93 to bond NH groups to oxygen atoms on the surface of the second interlayer insulating film 93. .

The NH ₃ plasma process, for example, using a parallel plate type plasma processing chamber having a counter electrode to about 9mm spaced position with respect to the silicon substrate 30, a substrate temperature of 400 ° C. under a pressure of 266 Pa, NH ₃ into the chamber The gas is supplied at a flow rate of 350 sccm. In this case, high frequency power of 13.56 MHz is supplied to the silicon substrate 30 side with a power of 100 W, and high frequency power of 350 kHz is supplied to the counter electrode with a power of 55 W for 60 seconds.

  Next, as shown in FIG. 33B, a titanium film having a thickness of 100 to 300 nm, for example, by sputtering as a base conductive film 94 on each of the second interlayer insulating film 93 and the second conductive plug 91, for example, Formed to 100 nm.

  The conditions for forming the titanium film are not particularly limited. In this embodiment, the substrate temperature is set to 20 ° C. in an argon atmosphere of 0.15 Pa in a sputtering chamber in which the distance between the titanium target and the silicon substrate 30 is set to 60 mm. Then, 2.6 kW of DC power is applied to the sputtering atmosphere for 35 seconds to form the titanium film.

  The base conductive film 94 is not limited to a titanium film, and any of a tungsten film, a silicon film, and a copper film may be formed as the base conductive film 94.

Here, in the step of FIG. 33A, NH groups are previously bonded to oxygen atoms on the surface of the second interlayer insulating film 93 by NH ₃ plasma treatment, so that titanium in the base conductive film 94 becomes oxygen atoms. It becomes difficult to be captured. Therefore, titanium can freely move on the surface of the second interlayer insulating film 93, and the base conductive film 94 made of titanium self-organized in the (002) direction is obtained.

  Thereafter, the base conductive film 94 is annealed in a nitrogen atmosphere to nitride the titanium of the base conductive film 94. The titanium nitride obtained by nitriding in this way preferably has a (111) orientation in order to align PZT described later in the (111) direction.

  Although the annealing conditions are not particularly limited, in this embodiment, the annealing is performed by RTA at a substrate temperature of about 650 ° C. and a processing time of about 60 seconds.

  By the way, the above-described recess is formed around the second conductive plug 91 on the upper surface of the second interlayer insulating film 93 by performing the CMP in the process of FIG. May have been. Therefore, irregularities reflecting this recess may be formed on the upper surface of the base conductive film 94.

  However, if there are such irregularities, the crystallinity of a ferroelectric film formed later above the underlying conductive film 94 may deteriorate.

  Therefore, in the next step, as shown in FIG. 33C, the upper surface of the underlying conductive film 94 is polished and planarized by the CMP method. The slurry used in the CMP is not particularly limited, but in this embodiment, SSW2000 manufactured by Cabot Microelectronics Corporation is used.

  The thickness of the underlying conductive film 94 after this CMP varies within the plane of the silicon substrate 30 and between the plurality of silicon substrates 30 due to polishing errors. In consideration of the variation, in this embodiment, the target value of the thickness of the underlying conductive film 94 after CMP is set to 50 to 100 nm, more preferably 50 nm, by controlling the polishing time.

  Thus, after CMP is performed on the base conductive film 94, the crystal in the vicinity of the upper surface of the base conductive film 94 is distorted by polishing. However, if the lower electrode of the capacitor is formed above the underlying conductive film 94 in which the crystal is distorted as described above, the distortion is picked up by the lower electrode, and the crystallinity of the lower electrode is deteriorated. The ferroelectric characteristics of the ferroelectric film will deteriorate.

In order to avoid such an inconvenience, in the next step, as shown in FIG. 34A, NH ₃ plasma treatment is performed on the base conductive film 94, so that the crystal distortion of the base conductive film 94 is reduced. Do not reach the upper membrane.

The NH ₃ plasma processing conditions are the same as those in the NH ₃ plasma processing of FIG.

Next, as shown in FIG. 34 (b), a titanium film is formed to a thickness of approximately about 95 nm by sputtering as the crystalline conductive film 95 on the base conductive film 94 from which the crystal distortion has been eliminated by the NH ₃ plasma treatment. Formed to 20 nm. Further, RTA with a substrate temperature of 650 ° C. and a processing time of 60 seconds is performed on the crystalline conductive film 95 in a nitrogen atmosphere to nitride the crystalline conductive film 95.

  Thereby, a crystalline conductive film 95 made of titanium nitride oriented in the (111) direction is obtained.

  The crystalline conductive film 95 has a function as an adhesion film in addition to the function of increasing the orientation of a film formed later on the crystalline conductive film 95 by the action of its own orientation.

  The crystalline conductive film 95 is not limited to a titanium nitride film. For example, a noble metal film such as a thin iridium film or platinum film of about 20 nm may be formed as the crystalline conductive film 95.

  Next, as shown in FIG. 34C, a titanium aluminum nitride (TiAlN) film is formed on the crystalline conductive film 95 as a conductive oxygen barrier film 96 to a thickness of about 100 nm.

  This titanium aluminum nitride film can be formed by a reactive sputtering method in which a target made of an alloy of titanium and aluminum is sputtered in a mixed atmosphere of argon gas and nitrogen gas. In that case, the argon gas flow rate is set to about 40 sccm, and the nitrogen gas flow rate is about 10 sccm. The pressure is about 253.3 Pa, the substrate temperature is 400 ° C., and the sputtering power is 1.0 kW.

  Next, as illustrated in FIG. 35A, an iridium film is formed on the conductive oxygen barrier film 96 by sputtering, and the iridium film is used as a first conductive film 97.

  This iridium film is formed to a thickness of about 100 nm with a sputtering power of 0.5 kW at a substrate temperature of 500 ° C. under a pressure of 0.11 Pa, for example.

Note that the first conductive film 97 is not limited to an iridium film, and may be a noble metal film other than the iridium film, for example, a platinum film. Further, a film made of a conductive metal oxide such as PtO, IrOx, SrRuO ₃ may be formed as the first conductive film 97.

  Next, as shown in FIG. 35B, a PZT film having a thickness of about 100 nm is formed as a first ferroelectric film 98 on the first conductive film 97 by MOCVD.

  The MOCVD method is performed as follows.

First, Pb (DPM) ₂ (chemical formula Pb (C ₁₁ H ₁₉ O ₂ ) ₂ )), Zr (dmhd) ₄ (chemical formula Zr (C ₉ H ₁₅ O ₂ ) ₄ ), and Ti (O-iOr) ₂ ( Each of DPM) ₂ (chemical formula Ti (C ₃ H ₇ O) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ ) is 0.3 mol / l in THF (Tetra Hydro Furan: C ₄ H ₈ O) solvent. Dissolve at a concentration to create Pb, Zr, and Ti liquid raw materials. Next, these liquid raw materials are supplied to the vaporizer of the MOCVD apparatus at a flow rate of 0.326 ml / min, 0.200 ml / min, and 0.200 ml / min, respectively, to vaporize them, so that Pb, Zr, and Ti are vaporized. A raw material gas is obtained. The vaporizer is supplied with a THF solvent having a flow rate of 0.474 ml / min together with each liquid raw material.

  Further, while supplying the source gas to the chamber, the pressure in the chamber is set to 665 Pa, and the substrate temperature is maintained at 620 ° C. Then, by maintaining such a state for 620 seconds, the PZT film described above is formed to a thickness of 100 nm.

  Since the first ferroelectric film 98 formed by the MOCVD method is crystallized at the time of film formation, crystallization annealing is not necessary.

  The film formation method of the first ferroelectric film 98 is not limited to the MOCVD method, but a sputtering method, a sol-gel method, a metal organic decomposition (MOD) method, a CSD (Chemical Solution Deposition) method, Further, the first ferroelectric film 98 may be formed by an epitaxial growth method. Among these, in the case of sputtering, for example, the first ferroelectric film 98 is not crystallized at the time of film formation, so crystallization annealing is performed after the film formation as in the first embodiment.

Further, the first ferroelectric film 98 is not limited to PZT. A film made of a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT may be formed as the first ferroelectric film 98. Further, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and Bi layered compounds such as SrBi ₄ Ti ₄ O ₁₅ The film may be formed as the first ferroelectric film 98.

  Incidentally, after this, the process proceeds to a step of forming a subsequent film on the first ferroelectric film 98. The film forming chamber for forming the film is an MOCVD for the first ferroelectric film 98. In some cases, it is provided in a semiconductor manufacturing apparatus different from the chamber.

  In that case, it is necessary to remove the silicon substrate 30 from the MOCVD chamber after forming the first ferroelectric film 98, transport the silicon substrate 30 in the atmosphere, and transfer it to another semiconductor device.

  At this time, the surface of the first ferroelectric film 49 is exposed to impurities such as moisture and carbon dioxide in the atmosphere, and these impurities penetrate into the film of the first ferroelectric film 49. The impurities cause film peeling in a later process.

  In order to prevent such film peeling, in the present embodiment, as shown in FIG. 35C, the first ferroelectric film 98 after being transported in the atmosphere is annealed, and the first The impurities contained in the ferroelectric film 98 are desorbed out of the film.

The annealing is performed for about 60 seconds in a reduced pressure atmosphere of about 5 × 10 ⁻⁶ to 1 × 10 ⁻³ Pa, for example. By performing annealing under reduced pressure in this way, impurities in the first ferroelectric film 49 are easily released from the film. The substrate temperature during annealing is 100 to 350 ° C., for example 150 ° C.

  The chamber used for this annealing is not particularly limited, and a heating chamber such as a degas chamber may be used, or annealing may be performed using a heater stage of a sputtering chamber. Alternatively, annealing may be performed using an RTA chamber or a furnace.

  The annealing atmosphere is not particularly limited, and may be either a non-plasma atmosphere or a plasma atmosphere.

Among these, the non-plasma atmosphere includes, for example, any of Ar, N ₂ , and O ₂ . On the other hand, examples of the plasma atmosphere include O ₂ plasma and N ₂ O plasma.

  After annealing in this way, in order to prevent re-adsorption of atmospheric impurities to the first ferroelectric film 98, the next process is performed without exposing the first ferroelectric film 98 to the atmosphere. I do.

  In the present embodiment, the silicon substrate 30 is transferred to an RF sputtering chamber provided in the same semiconductor manufacturing apparatus as the annealing chamber used for annealing the first ferroelectric film 98. Since the RF sputtering chamber is provided in the same semiconductor device as the annealing chamber, the first ferroelectric film 98 is not exposed to the atmosphere.

  Then, as shown in FIG. 36A, using the RF sputtering chamber, a PZT film is formed on the first ferroelectric film 98 to a thickness of about 1 to 30 nm, for example, 20 nm, and this PZT film is formed as a second film. The ferroelectric film 99 of FIG. Since the PZT formed by the sputtering method is not crystallized immediately after the film formation, the second ferroelectric film 99 is amorphous at this point.

  Further, as described in the first embodiment, the second ferroelectric film 99 is formed in order to align the second ferroelectric film after crystallization later in the (111) direction. The film temperature is preferably about 0 ° C to 150 ° C.

  Next, as shown in FIG. 36B, an iridium oxide film having a thickness of 10 to 75 nm, for example, 50 nm, is formed as a second conductive film 100 on the second ferroelectric film 99 by sputtering.

  In the sputtering method, an iridium target is sputtered with a mixed gas of argon gas and oxygen gas, whereby iridium scattered from the iridium target is oxidized in a sputtering atmosphere to form the iridium oxide film.

  At this time, the ratio of oxygen gas to the total sputtering gas is preferably 10 to 60% in flow rate ratio. In the present embodiment, the flow rates of argon gas and oxygen gas are both 100 sccm.

  Regarding the substrate temperature, the second conductive film 100 can be formed within a range of 20 to 400 ° C. Which one of the high temperature side and the low temperature side is selected within the range is selected from the residual polarization charge amount and the leakage current of the first and second ferroelectric films 98 and 99 as described in the first embodiment. Depending on whether to prioritize.

  In the first embodiment, the second conductive film 100 is formed at a substrate temperature of 300 ° C. in order to prioritize the residual polarization charge amount in the present embodiment. . In this case, the sputtering power is about 1 to 2 kW. By adopting such conditions, an iridium oxide film crystallized at the time of film formation is formed.

  When the second conductive film 100 is formed at a high temperature of about 300 ° C., impurities in the atmosphere contained in the first and second ferroelectric films 99 and 100 are formed in the film formation atmosphere during the film formation. Detach. For this reason, in this embodiment, it is possible to reduce impurities without performing the second annealing (FIG. 15B) on the second ferroelectric film 50 as described in the first embodiment.

  However, in order to ensure reduction of impurities, the second ferroelectric film 100 may be annealed in the same manner as in the first embodiment.

  Note that the second conductive film 100 is not limited to an iridium oxide film. The second conductive film 100 may be formed by using a sputtering target made of any one of platinum, ruthenium, rhodium, rhenium, osmium, and palladium and performing sputtering under conditions in which these metals are oxidized.

  Subsequently, as shown in FIG. 37A, crystallization annealing is performed on the second ferroelectric film 99 in a state where the second conductive film 100 is formed, so that the second ferroelectric film is formed. Crystallize 99 PZT.

  Since this crystallization annealing is performed in an oxygen-containing atmosphere, oxygen is supplied from the annealing atmosphere to the second ferroelectric film 99, and oxygen vacancies in the second ferroelectric film 99 are compensated. Furthermore, this crystallization annealing can also provide an advantage that the plasma damage received by the second ferroelectric film 99 during the formation of the second conductive film 100 can be recovered.

  In this embodiment, this annealing is performed by RTA in a mixed gas atmosphere of oxygen gas and argon gas. In this case, the ratio of oxygen gas in the entire annealing atmosphere is set to 1 to 50% in flow rate ratio. For example, the flow rate of oxygen gas is 20 sccm, and the flow rate of argon gas is 2000 sccm. The processing time is 60 seconds, and the substrate temperature is 650 to 750 ° C., for example, 725 ° C.

  Thereafter, as shown in FIG. 37B, an iridium oxide film having a thickness of about 100 to 300 nm is formed on the second conductive film 100 by sputtering, and the iridium oxide film is formed into a first conductive protective film. The film 101 is used.

  The film forming conditions of the first conductive protective film 101 are not particularly limited.

  In the present embodiment, argon gas and oxygen gas are used as the sputtering gas, and the film forming pressure is 0.8 Pa. Then, the first conductive protective film 101 made of iridium oxide having a thickness of about 200 nm is formed by setting the film formation time to 79 seconds with a sputtering power of 1.0 kW.

  When oxygen is insufficient in the first conductive protective film 101, the proportion of iridium having a reducing action in the first conductive protective film 101 increases. In this case, moisture or the like is reduced by the first conductive protective film 101 to become hydrogen, and the first and second ferroelectric films 98 and 99 may be deteriorated by the hydrogen.

Therefore, as the iridium oxide of the first conductive protective film 101, by using the iridium oxide whose composition is as close as possible to the stoichiometric composition (IrO ₂ ) of iridium, the proportion of iridium in the film is reduced. It is preferable to prevent deterioration of the ferroelectric films 98 and 99 due to hydrogen. The composition of the iridium oxide can be controlled to some extent by adjusting the flow rate ratio of the oxygen gas in the sputtering gas.

Note that the material of the first conductive protection film 101 is not limited to iridium oxide. Instead of iridium oxide, a film of any one of iridium, ruthenium, rhodium, rhenium, osmium, and palladium, a film made of these oxides, or a single layer film of any of SrRuO ₃ films or a laminated film thereof The first conductive protective film 101 may be formed.

  Next, as shown in FIG. 38A, an iridium film is formed as a second conductive hydrogen barrier film 102 on the first conductive protective film 101 to a thickness of about 100 nm by sputtering.

  In the sputtering method, argon gas is used as the sputtering gas, the film forming pressure is 1 Pa, and the sputtering power is 1.0 kW.

Note that a platinum film or a SrRuO ₃ film may be formed as the second conductive hydrogen barrier film 102 instead of the iridium film.

  Thereafter, the PZT attached to the back surface of the silicon substrate 30 when the first and second ferroelectric films 98 and 99 are formed is cleaned and removed.

  Next, steps required until a sectional structure shown in FIG.

  First, a titanium nitride film is formed on the second conductive hydrogen barrier film 102 by sputtering, and the titanium nitride film is used as the first hard mask 103.

  The first hard mask 103 is not limited to a titanium nitride film. A single layer film of a titanium aluminum nitride film, a tantalum aluminum nitride (TaAlN) film, a tantalum nitride (TaN) film, or a stacked film thereof may be formed as the first hard mask 103.

  Then, a silicon oxide film is formed as the second hard mask 104 on the first hard mask 103 by a plasma CVD method using TEOS gas.

  Thereafter, the first and second hard masks 103 and 104 are patterned by photolithography and etching, and these masks are formed into island shapes as shown in the drawing.

Next, as shown in FIG. 39A, the first and second hard masks 103 and 104 are covered by plasma etching using a mixed gas of HBr, O ₂ , Ar, and C ₄ F ₈ as an etching gas. The non-exposed portions of the films 97 to 102 are dry-etched.

  Thus, the first conductive film 97 and the second conductive film 100 become the lower electrode 97a and the upper electrode 100a, respectively, and the first and second ferroelectric films 98 and 99 become the capacitor dielectric film 98a.

  Through the steps up to here, the ferroelectric capacitor Q including the lower electrode 97a, the capacitor dielectric film 98a, and the upper electrode 100a is formed in the cell region of the silicon substrate 30.

  Next, as shown in FIG. 39B, the second hard mask 104 is removed by dry etching or wet etching.

  Then, as shown in FIG. 40A, portions of the underlying conductive film 94, the crystalline conductive film 95, and the conductive oxygen barrier film 96 that are not covered with the capacitor Q are removed by dry etching.

This etching is performed using, for example, a down flow type plasma etching chamber and using a mixed gas of 5% CF ₄ gas and 95% O ₂ gas as an etching gas. Further, high frequency power having a frequency of 2.45 GHz and a power of 1400 W is supplied to the upper electrode of the chamber, and the substrate temperature is set to 200 ° C.

  Note that the first hard mask 103 remains on the capacitor Q without being removed by this etching.

  Subsequently, as shown in FIG. 40B, an alumina film having a thickness of about 20 nm is formed as a first hydrogen barrier insulating film 110 on the entire upper surface of the silicon substrate 30 by sputtering. Note that an alumina film having a thickness of about 2 to 5 nm may be formed by MOCVD instead of sputtering.

  Thereafter, recovery annealing is performed on the capacitor dielectric film 98a in an oxygen-containing atmosphere for the purpose of recovering the damage received by the capacitor dielectric film 98a in the steps so far. The conditions for this recovery annealing are not particularly limited. In this embodiment, the recovery annealing is performed at a substrate temperature of 550 to 700 ° C., for example, 600 ° C. in the furnace.

  The recovery annealing also oxidizes the first hard mask 103 made of titanium nitride remaining on the upper electrode 100a. The first hard mask 103 thus oxidized has a higher oxygen content in the upper layer than in the lower layer.

  Subsequently, as shown in FIG. 41A, an alumina film having a thickness of about 38 nm is formed on the first hydrogen barrier insulating film 110 as a second hydrogen barrier insulating film 111 by MOCVD.

  The first and second hydrogen barrier insulating films 110 and 111 are made of alumina that has an excellent function of blocking the permeation of reducing substances such as hydrogen and moisture, and the capacitor dielectric film is reduced by the reducing substances and its strongness. It plays a role of preventing deterioration of dielectric characteristics.

  As the film having such a function, in addition to the alumina film, there are a titanium oxide film, a tantalum oxide film, a zirconium oxide film, an aluminum nitride film, a tantalum nitride film, and an aluminum oxynitride film. The first and second hydrogen barrier insulating films 110 and 111 may be formed.

  Next, steps required until a sectional structure shown in FIG.

  First, a silicon oxide film is formed to a thickness of about 1500 nm on the second hydrogen barrier insulating film 111 by plasma CVD, and the silicon oxide film is used as the third interlayer insulating film 112. In the plasma CVD method, for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used as a film forming gas.

  Thereafter, the upper surface of the third interlayer insulating film 112 is polished and planarized by the CMP method.

Next, by annealing the third interlayer insulating film 112 in an atmosphere of N ₂ O plasma or N ₂ plasma, the third interlayer insulating film 112 is dehydrated and its upper surface is nitrided to prevent re-adsorption of moisture. To do.

  Next, an alumina film having a thickness of about 20 to 100 nm is formed on the third interlayer insulating film 112 as the third hydrogen barrier insulating film 113 by sputtering or MOCVD.

  Further, a silicon oxide film having a thickness of about 800 to 1000 nm is formed on the third hydrogen barrier insulating film 113 by plasma CVD using TEOS gas, and this silicon oxide film is used as the cap insulating film 114.

  Note that a silicon oxynitride film or a silicon nitride film may be formed as the cap insulating film 114 instead of the silicon oxide film.

  Next, as shown in FIG. 42A, the insulating films 110 to 114 are patterned by photolithography and etching to form second holes 112a in these insulating films above the upper electrode 100a.

  Then, in order to recover the damage received by the capacitor dielectric film 98a in the steps so far, recovery annealing is performed at a substrate temperature of about 450 ° C. in an oxygen-containing atmosphere.

  Next, as shown in FIG. 42B, third holes 112b are formed in the insulating films 92, 93, 110 to 114 above the second source / drain regions 36b by photolithography and etching.

  Thereafter, the third interlayer insulating film 113 and the like are dehydrated by annealing. The annealing is preferably performed in an inert gas atmosphere or a reduced pressure atmosphere in order to prevent oxidation of the first conductive plug 43 exposed from the third hole 112b.

  Next, steps required until a sectional structure shown in FIG.

  First, the inner surfaces of the holes 112a and 112b are etched and cleaned by RF etching.

  A titanium nitride film having a thickness of about 125 nm is formed as a glue film on the inner surfaces of the holes 112a and 112b and the upper surface of the cap insulating film 114 by a sputtering method.

  The aspect ratio of the third hole 112b above the second source / drain region 36b is higher than that of the second hole 112a. Therefore, it is preferable to form a glue film with good coverage in each of the holes 112a and 112b by using the sputtering method using the SIP (Self Ionized Plasma) technique described in the first embodiment.

  The glue film is not limited to the titanium nitride film. Instead of titanium nitride film, TaN, CrN, HfN, ZrN, TiAlN, TaAlN, TiSiN, TaSiN, CrAlN, HfAlN, ZrAlN, TiON, TaON, CrON, HfON, ZrON, TiAlON, TaAlON, CrAlON, HfAlON, ZrAlON, TiSiON A film made of any of TaSiON, Ir, Ru, IrOx, and RuOx may be formed as a glue film. Further, a laminated film of a Ti film and a TiN film, a laminated film of a Ti film and a TaN film, a laminated film of a Ta film and a TiN film, or a laminated film of a Ta film and a TaN film may be formed as a glue film. .

  Then, a tungsten film is formed with a thickness of about 300 nm on this glue film by CVD, and the holes 112a and 112b are completely filled with the tungsten film. Note that a copper film may be formed instead of the tungsten film.

  Then, excess tungsten film and glue film on the upper surface of the cap insulating film 114 are removed by polishing by the CMP method, and these films are removed in the holes 112a and 112b by the third and fourth conductive plugs 116 and 117, respectively. Leave as.

  Of these conductive plugs, the third conductive plug 116 is electrically connected to the upper electrode 100a of the capacitor Q. On the other hand, the fourth conductive plug 117 is electrically connected to the first conductive plug 43 on the second source / drain region 36b.

  The structure of each conductive plug 116, 117 is not particularly limited. For example, the above tungsten film is further etched back, the upper surface thereof is lowered to a depth in the middle of each of the holes 112a and 112b, and a copper film is further formed thereon, whereby the upper portions of the holes 112a and 112b are formed on the copper film. You may make it fill with. In that case, a polysilicon film may be formed instead of tungsten.

  Next, in order to remove the natural oxide film on the upper surfaces of the conductive plugs 116 and 117, the upper surfaces are etched by sputter etching with argon plasma.

  Then, a metal laminated film is formed on each of the conductive plugs 116 and 117 and the cap insulating film 114 by a sputtering method, and is patterned to form a first-layer metal wiring 115.

  As the metal laminated film, for example, a titanium nitride film having a thickness of about 50 nm, a copper-containing aluminum film having a thickness of about 550 nm, a titanium film having a thickness of about 5 nm, and a titanium nitride film having a thickness of about 50 nm are formed in this order.

  Thereafter, the second to fifth layer metal wirings and the interlayer insulating film are alternately laminated to obtain a multilayer wiring structure, but details thereof are omitted.

  In the present embodiment described above, as described with reference to FIG. 35C, the crystallized first ferroelectric film 98 is annealed. The crystallized ferroelectric film absorbs impurities such as carbon dioxide and moisture in the atmosphere more easily than the amorphous film. The impurities are desorbed from the first ferroelectric film 98 by the above annealing. As a result, it is possible to prevent film peeling from occurring at the interface between the second ferroelectric film 99 and the second conductive film 100 due to impurities, and the reliability of the semiconductor device including the ferroelectric capacitor Q can be improved. improves.

  The aspects of the present invention are summarized in the following supplementary notes.

(Additional remark 1) The process of forming an insulating film above a semiconductor substrate,
Forming a first conductive film on the insulating film;
Forming a crystallized first ferroelectric film on the first conductive film;
Performing a first annealing on the first ferroelectric film;
After the first annealing, forming an amorphous second ferroelectric film on the first ferroelectric film so as not to expose the semiconductor substrate to the atmosphere;
Forming a second conductive film on the second ferroelectric film;
After forming the second conductive film, annealing the second ferroelectric film to crystallize;
Patterning the first conductive film, the first ferroelectric film, the second ferroelectric film, and the second conductive film to form a ferroelectric capacitor;
A method for manufacturing a semiconductor device, comprising:

  (Supplementary note 2) The method of manufacturing a semiconductor device according to supplementary note 1, wherein a substrate temperature in the first annealing is set higher than a substrate temperature when the second ferroelectric film is formed.

  (Supplementary Note 3) The method of manufacturing a semiconductor device according to Supplementary Note 1 or 2, wherein a substrate temperature in the first annealing is lower than a crystallization temperature of the first ferroelectric film.

  (Additional remark 4) The substrate temperature in said 1st annealing shall be 150 degreeC-350 degreeC, The manufacturing method of the semiconductor device in any one of Additional remarks 1-3 characterized by the above-mentioned.

  (Additional remark 5) The manufacturing method of the semiconductor device in any one of Additional remarks 1-4 characterized by performing said 1st annealing in the atmosphere where hydrogen was excluded.

  (Supplementary Note 6) The method for manufacturing a semiconductor device according to any one of Supplementary notes 1 to 5, wherein the first annealing is performed in an atmosphere containing oxygen.

(Supplementary Note 7) The first annealing, a method of manufacturing a semiconductor device according to any one of appendixes 1 to 6, characterized in that in an atmosphere of O ₂ plasma or N ₂ O plasma.

(Supplementary Note 8) The first annealing, Ar, a method of manufacturing a semiconductor device according to any one of appendixes 1 to 6, characterized in that in N _2, and the non-plasma atmosphere of O _2.

  (Supplementary note 9) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 8, further comprising a step of washing the surface of the first ferroelectric film with water before the first annealing. .

  (Supplementary Note 10) After the step of forming the second ferroelectric film and before the step of forming the second conductive film, the second ferroelectric film has a second The method for manufacturing a semiconductor device according to any one of appendix 1 to appendix 9, further comprising a step of annealing.

  (Additional remark 11) The substrate temperature in said 2nd annealing is made lower than the crystallization temperature of said 2nd ferroelectric film, The manufacturing method of the semiconductor device of Additional remark 10 characterized by the above-mentioned.

  (Supplementary Note 12) The supplementary note 10 or the supplementary note 11, wherein after the second annealing, the process proceeds to a step of forming the second conductive film without exposing the second ferroelectric film to the atmosphere. The manufacturing method of the semiconductor device as described in any one of.

  (Supplementary Note 13) By performing each of the step of performing the first annealing, the step of forming the second ferroelectric film, and the step of forming the second conductive film with the same semiconductor manufacturing apparatus, 10. The method for manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein the semiconductor substrate is not exposed to the atmosphere between these steps.

  (Supplementary Note 14) The step of forming the crystallized first ferroelectric film includes the step of forming the amorphous first ferroelectric film and the step of annealing the first ferroelectric film. The method for manufacturing a semiconductor device according to any one of appendices 1 to 13, further comprising a step of crystallizing the semiconductor device.

  (Additional remark 15) The process of forming the said crystallized 1st ferroelectric film is performed by forming the ferroelectric film crystallized at the time of film-forming by MOCVD method, It is characterized by the above-mentioned. The manufacturing method of the semiconductor device in any one of -13.

  (Appendix 16) At least one of the first ferroelectric film and the second ferroelectric film is formed by a sputtering method at a substrate temperature of 0 ° C. to 150 ° C. The manufacturing method of the semiconductor device in any one.

  (Supplementary note 17) The method for manufacturing a semiconductor device according to supplementary note 1, wherein the first ferroelectric film is exposed to the atmosphere before the first annealing step.

FIGS. 1A to 1C are cross-sectional views (part 1) showing a method for producing a sample used for the investigation in the order of steps. FIGS. 2A to 2C are cross-sectional views (part 2) showing the method of preparing the sample used for the investigation in the order of steps. FIG. 3 is a cross-sectional view (part 3) showing a method for producing a sample used in the investigation in the order of steps. FIG. 4 is a wafer map obtained by inspecting a sample using a defect inspection apparatus. FIG. 5 is a plan view obtained by observing one of the defects in FIG. 4 with an SEM. 6A is a diagram drawn based on the cross-sectional TEM image of the defect in FIG. 5, and FIG. 6B is an enlarged cross-sectional view of FIG. 6A. FIG. 7 is a cross-sectional view of a sample used for the investigation by TDS. FIG. 8 is a graph obtained by measuring the amount of water contained in the PZT film by TDS. FIG. 9 is a graph obtained by examining the amount of carbon dioxide in the PZT film by the TDS method for the same sample as FIG. FIG. 10 is a schematic diagram showing the mechanism of film peeling. 11A to 11C are cross-sectional views (part 1) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. 12A to 12C are cross-sectional views (part 2) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 13A and 13B are cross-sectional views (part 3) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 14A and 14B are cross-sectional views (part 4) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 15A and 15B are cross-sectional views (part 5) in the course of manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 16A and 16B are cross-sectional views (part 6) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. 17A and 17B are cross-sectional views (part 7) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. 18A and 18B are cross-sectional views (part 8) in the middle of the manufacture of the semiconductor device according to the first embodiment of the present invention. 19A and 19B are cross-sectional views (part 9) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 20A and 20B are cross-sectional views (part 10) in the middle of the manufacture of the semiconductor device according to the first embodiment of the present invention. 21A and 21B are cross-sectional views (part 11) in the middle of the manufacture of the semiconductor device according to the first embodiment of the present invention. 22A and 22B are cross-sectional views (No. 12) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. 23A and 23B are cross-sectional views (No. 13) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 24 is a cross-sectional view (No. 14) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 25 is a flowchart showing the main steps of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 26 is a graph obtained by investigating the number of defects due to film peeling in the plane of 25 silicon substrates. FIG. 27 is a wafer map of one of the wafers investigated in FIG. FIG. 28 is a planar image obtained by observing one of the defects in FIG. 26 with an SEM. FIG. 29 is a wafer map when both the first annealing and the second annealing are performed. FIG. 30 is a flowchart according to a first modification of the first embodiment of the present invention. FIG. 31 is a flowchart according to a second modification of the first embodiment of the present invention. 32A to 32C are cross-sectional views (part 1) in the middle of manufacturing the semiconductor device according to the second embodiment of the present invention. 33A to 33C are cross-sectional views (part 2) in the middle of manufacturing the semiconductor device according to the second embodiment of the present invention. 34A to 34C are cross-sectional views (part 3) in the middle of the manufacture of the semiconductor device according to the second embodiment of the present invention. FIGS. 35A to 35C are cross-sectional views (part 4) in the middle of manufacturing the semiconductor device according to the second embodiment of the present invention. FIGS. 36A and 36B are cross-sectional views (part 5) in the middle of manufacturing the semiconductor device according to the second embodiment of the present invention. 37A and 37B are cross-sectional views (part 6) in the middle of manufacturing the semiconductor device according to the second embodiment of the present invention. 38A and 38B are cross-sectional views (part 7) in the middle of manufacturing the semiconductor device according to the second embodiment of the present invention. 39A and 39B are cross-sectional views (part 8) in the middle of manufacturing the semiconductor device according to the second embodiment of the present invention. FIGS. 40A and 40B are cross-sectional views (part 9) in the middle of manufacturing the semiconductor device according to the second embodiment of the present invention. 41 (a) and 41 (b) are cross-sectional views (part 10) in the middle of the manufacture of the semiconductor device according to the second embodiment of the present invention. 42A and 42B are cross-sectional views (part 11) in the middle of the manufacture of the semiconductor device according to the second embodiment of the present invention. FIG. 43 is a cross-sectional view (No. 12) of the semiconductor device according to the second embodiment of the present invention which is being manufactured.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 20, 30 ... Silicon substrate, 3 ... 1st electrically conductive film, 5 ... 1st ferroelectric film, 7 ... 2nd ferroelectric film, 10 ... Impurity, 11 ... 3rd electrically conductive film, 21 ... PZT film, 31 ... element isolation insulating film, 32 ... p well, 33 ... gate insulating film, 34 ... gate electrode, 35a, 35b ... first and second source / drain extensions, 36a, 36b ... first, first 2 ... source / drain regions, 37 ... insulating spacer, 38 ... refractory silicide layer, 41 ... cover insulating film, 42 ... first interlayer insulating film, 42a ... contact hole, 43 ... first conductive plug, 45 ... Antioxidation insulating film 46. Insulating adhesive film 47. Lower electrode adhesive film 48. First conductive film 49. First ferroelectric film 50. Second ferroelectric film 51. Second conductive film 52 ... conductive protective film 53 ... hard mask 57 ... 1st resist pattern, 61 ... lower electrode, 62 ... capacitor dielectric film, 63 ... upper electrode, 65 ... first hydrogen barrier insulating film, 70 ... second hydrogen barrier insulating film, 71 ... second interlayer insulation Films 71a to 71c ... first to third holes 72 ... third hydrogen barrier insulating film 73 ... cap insulating film 75 ... glue film 76 ... tungsten film 77 ... second conductive plug 78 -62 ... 1st-5th layer metal wiring, 83-86 ... 3rd-6th interlayer insulation film, 87, 88 ... 1st, 2nd passivation film, 91 ... 2nd electroconductive plug, 92 ... Antioxidation insulating film, 93 ... second interlayer insulating film, 93a ... first hole, 94 ... underlying conductive film, 95 ... crystalline conductive film, 96 ... conductive oxygen barrier film, 97 ... first conductive film, 98: First ferroelectric film, 99: Second ferroelectric film, 100 2nd conductive film 101 ... 1st conductive protective film 102 ... 2nd conductive hydrogen barrier film | membrane 103 ... 1st hard mask 104 ... 2nd hard mask 110 ... 1st hydrogen barrier Insulating film, 111 ... second hydrogen barrier insulating film, 112 ... third interlayer insulating film, 112a, 112b ... second and third holes, 113 ... third hydrogen barrier insulating film, 114 ... cap insulating film, 115: First layer metal wiring, 116, 117: Third and fourth conductive plugs.

Claims (4)

Forming an insulating film above the semiconductor substrate;
Forming a first conductive film on the insulating film;
Forming a crystallized first ferroelectric film on the first conductive film;
Performing a first annealing on the first ferroelectric film;
After the first annealing, forming an amorphous second ferroelectric film on the first ferroelectric film so as not to expose the semiconductor substrate to the atmosphere;
Forming a second conductive film on the second ferroelectric film;
After forming the second conductive film, annealing the second ferroelectric film to crystallize;
Patterning the first conductive film, the first ferroelectric film, the second ferroelectric film, and the second conductive film to form a ferroelectric capacitor;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of washing the surface of the first ferroelectric film with water before the first annealing.   A step of performing a second annealing on the second ferroelectric film after the step of forming the second ferroelectric film and before the step of forming the second conductive film. The method of manufacturing a semiconductor device according to claim 1, further comprising:   By performing each of the step of performing the first annealing, the step of forming the second ferroelectric film, and the step of forming the second conductive film with the same semiconductor manufacturing apparatus, the steps between these steps are performed. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is not exposed to the atmosphere.

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