JP2008277659A - Manufacturing method of semiconductor device - Google Patents

Abstract

A semiconductor device manufacturing method capable of improving the yield of a semiconductor device provided with a ferroelectric capacitor.
A step of forming a first conductive film on a first interlayer insulating film; a step of forming a crystallized first ferroelectric film on the first conductive film; The step of forming an amorphous second ferroelectric film 24c on the first ferroelectric film 24b, the step of removing impurities adhering to the second ferroelectric film 24c, and removing the impurities A step of forming a second conductive film 25 on the second ferroelectric film 24c; a step of crystallizing the second ferroelectric film 24c after forming the second conductive film 25; Forming the capacitor Q including the lower electrode 23a, the capacitor dielectric film 24a, and the upper electrode 25a by patterning the second conductive films 23 and 25 and the first and second ferroelectric films 24b and 24c; According to a method for manufacturing a semiconductor device having
[Selection] Figure 8

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, with the advancement of digital technology, development of a nonvolatile memory capable of storing and reading a large amount of data at high speed has been advanced.

  As such a nonvolatile memory, a flash memory and a ferroelectric memory are known.

  Among these, the ferroelectric memory is also called FeRAM (Ferroelectric Random Access Memory), which stores information using the hysteresis characteristics of the ferroelectric film provided in the ferroelectric capacitor, and operates at a lower voltage than the flash memory. It has the advantage of being possible.

  There are a 1T1C system and a 2T2C system as the circuit system of the ferroelectric memory, but the 1T1C system is superior in that the capacitor area is reduced to achieve high integration.

  Even when the capacitor area is reduced as described above, in order to further reduce the operating voltage of the ferroelectric capacitor, it is necessary to make the capacitor dielectric film thinner and to lower the polarization inversion voltage of the ferroelectric capacitor. is there.

  However, if the capacitor dielectric film is simply thinned and the same voltage as the current voltage is applied to the capacitor, the electric field applied to the capacitor dielectric film may be larger than the current voltage, which may increase the leakage current in the capacitor dielectric film. .

  It is considered that the cause of the leakage current generated in the capacitor dielectric film is mainly a void existing at a crystal grain boundary in the capacitor dielectric film.

  In general, in a method for forming a ferroelectric capacitor having a ferroelectric film, crystallization annealing is performed to crystallize the ferroelectric film. The ferroelectric film subjected to crystallization annealing has voids at crystal grain boundaries in the film. Then, when the upper electrode is formed, the upper electrode is embedded in the gap, so that the effective film thickness of the ferroelectric film is reduced, and the leakage current is increased.

  Therefore, by reducing the gap, the leakage current is reduced, and a ferroelectric film with a leakage current reduced to such an extent that it can withstand actual use even if the thickness is reduced can be obtained.

  In view of this point, in Patent Document 1, a laminated film of a crystallized first ferroelectric film and an amorphous second ferroelectric film is used as a capacitor dielectric film. Then, after forming a conductive film for the upper electrode on the second ferroelectric film, the second ferroelectric film is subjected to crystallization annealing for the amorphous second ferroelectric film. Is crystallized.

  According to this, since the gap in the first ferroelectric film is filled with the amorphous second ferroelectric film, the leakage current generated due to the gap in the first ferroelectric film can be reduced.

  However, the amorphous second ferroelectric film easily absorbs substances in the atmosphere and has a large shrinkage rate due to annealing. Therefore, due to contamination of the surface layer of the second ferroelectric film, degassing generated from the second ferroelectric film during crystallization annealing, and stress generated in the second ferroelectric film during crystallization annealing, etc. The adhesion between the second ferroelectric film and the upper electrode is lowered, and the upper electrode is peeled off or floated. As a result, defects such as capacitor shape defects and pattern jumps occur, and as a result, the yield of the semiconductor device decreases.

  In order to avoid such a problem, it is conceivable to crystallize the second ferroelectric film before forming the upper electrode.

  However, in this case, a gap is formed in the crystal grain boundary of the crystallized second ferroelectric film, and the upper electrode material is embedded in the gap to form a leak path. Thus, the original purpose of preventing the leakage current cannot be achieved.

  In addition, techniques related to the present application are also disclosed in Patent Documents 2 and 3 below.

  Among them, in Patent Document 2, the lower electrode film, the ferroelectric film, and the upper electrode film are formed in an atmosphere cut off from the atmosphere to prevent the ferroelectric film from being contaminated by the atmosphere ( Paragraph number 0026).

In Patent Document 3, the ferroelectric film is received during the process while annealing is performed in a state where the protective film is formed on the upper electrode to prevent hillocks from being formed on the upper electrode. Damage has been recovered (paragraph number 0034).
JP 2006-318941 A JP-A-11-54721 JP 2006-222227 A

  An object of the present invention is to provide a semiconductor device manufacturing method capable of improving the yield of a semiconductor device provided with a ferroelectric capacitor.

  According to one aspect of the present invention, a step of forming an insulating film over a semiconductor substrate, a step of forming a first conductive film on the insulating film, and crystallization on the first conductive film A step of forming a first ferroelectric film; a step of forming an amorphous second ferroelectric film on the first ferroelectric film; and a crystallization temperature of the second ferroelectric film. Annealing the second ferroelectric film at a lower substrate temperature, forming a second conductive film on the second ferroelectric film, and after forming the second conductive film, There is provided a method of manufacturing a semiconductor device including a step of crystallizing a second ferroelectric film.

  By annealing the second ferroelectric film in this way, impurities in the atmosphere adsorbed on the second ferroelectric film are removed, or impurities are difficult to adsorb on the second ferroelectric film. The lowering of the adhesion between the lower electrode and the capacitor dielectric film caused by impurities can be prevented, and the lower electrode can be prevented from peeling off during the process.

  The annealing is preferably performed, for example, in a non-plasma atmosphere or a plasma atmosphere from which hydrogen is excluded.

  In this case, if the substrate temperature at the time of annealing is equal to or higher than the crystallization temperature of the second ferroelectric film, the second ferroelectric film is crystallized before the lower electrode is formed, and the lower electrode is formed when the lower electrode is formed. The material enters the crystal grain boundary of the second ferroelectric film and a leak path is formed. Therefore, it is necessary to set the substrate temperature during annealing to a temperature lower than the crystallization temperature of the second ferroelectric film.

  According to another aspect of the present invention, a step of forming an insulating film above a semiconductor substrate, a step of forming a first conductive film on the insulating film, and on the first conductive film, A step of forming a crystallized first ferroelectric film, a step of forming an amorphous second ferroelectric film on the first ferroelectric film, and a step of forming the second ferroelectric film. A step of washing the surface with water, a step of forming a second conductive film on the second ferroelectric film after the water washing, and a step of forming the second conductive film, and then forming the second ferroelectric film. There is provided a method of manufacturing a semiconductor device including a step of crystallizing.

  By washing the second ferroelectric film with water in this way, impurities in the atmosphere adsorbed on the second ferroelectric film are removed, so that the lower electrode is prevented from peeling during the process due to the impurities. It becomes possible to do.

  According to the present invention, since the second ferroelectric film is annealed or washed with water, it is possible to prevent the adhesion between the capacitor dielectric film and the upper electrode from being deteriorated due to impurities in the second ferroelectric film. It is possible to suppress a decrease in yield due to peeling of the upper electrode.

  Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(1) First Embodiment FIGS. 1 to 7 are cross-sectional views in the course of manufacturing a semiconductor device according to a first embodiment of the present invention.

  This semiconductor device is a planar-type FeRAM and is manufactured as follows.

  First, steps required until a sectional structure shown in FIG.

  First, an element isolation insulating film 2 is formed by thermally oxidizing the surface of an n-type or p-type silicon (semiconductor) substrate 1, and an active region of the transistor is defined by the element isolation insulating film 2. Such an element isolation structure is called LOCOS (Local Oxidation of Silicon), but STI (Shallow Trench Isolation) may be adopted instead.

  Next, after a p-type impurity such as boron is introduced into the active region of the silicon substrate 1 to form the p-well 3, the surface of the active region is thermally oxidized, so that a thermal oxide film that becomes the gate insulating film 4 is reduced to about It is formed to a thickness of 6-7 nm.

  Subsequently, an amorphous silicon film having a thickness of about 50 nm and a tungsten silicide film having a thickness of about 150 nm are sequentially formed on the entire upper surface of the silicon substrate 1. Note that a polycrystalline silicon film may be formed instead of the amorphous silicon film. Thereafter, these films are patterned by photolithography to form the gate electrode 5 on the silicon substrate 1.

  Two gate insulating films 5 are formed in parallel to each other on the p-well 3, each of which constitutes a part of a word line.

  Further, phosphorus is introduced as an n-type impurity into the silicon substrate 1 beside the gate electrode 5 by ion implantation using the gate electrode 5 as a mask to form first and second source / drain extensions 6a and 6b.

  Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1, and the insulating film is etched back to leave an insulating sidewall 7 beside the gate electrode 5. As the insulating film, a silicon oxide film is formed by, for example, a CVD (Chemical Vapor Deposition) method.

  Subsequently, n-type impurities such as arsenic are ion-implanted again into the silicon substrate 1 while using the insulating sidewalls 7 and the gate electrode 5 as a mask, so that the first, Second source / drain regions 8a and 8b are formed.

  Further, a refractory metal film such as a cobalt film is formed on the entire upper surface of the silicon substrate 1 by sputtering. Then, the refractory metal film is heated and reacted with silicon to form a refractory metal silicide layer 9 such as a cobalt silicide layer on the silicon substrate 1 in the first and second source / drain regions 8a and 8b. The resistance of each source / drain region 8a, 8b is reduced.

  Thereafter, the refractory metal film which has not reacted on the element isolation insulating film 2 or the like is removed by wet etching.

Through the steps so far, the active region of the silicon substrate 1 includes the first and second MOS transistors TR _{1 including} the gate insulating film 4, the gate electrode 5, and the first and second source / drain regions 8 a and 8 b. , TR ₂ is formed.

  Next, as shown in FIG. 1B, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed on the entire upper surface of the silicon substrate 1 by a plasma CVD method. .

Further, a silicon oxide (SiO ₂ ) film having a thickness of about 600 nm is formed as a first interlayer insulating film 11 on the antioxidant insulating film 10 by plasma CVD using TEOS (tetra ethoxy silane) gas.

  Thereafter, the first interlayer insulating film 11 is polished by CMP (Chemical Mechanical Polishing) to flatten the upper surface. By this CMP, the film thickness from the surface of the silicon substrate 1 to the surface of the first interlayer insulating film 11 becomes about 785 nm.

  Next, the first interlayer insulating film 11 is degassed by annealing the first interlayer insulating film 11 for 30 minutes in a nitrogen atmosphere at a substrate temperature of 650 ° C.

Further, an alumina (Al ₂ O ₃ ) film having a thickness of about 20 nm is formed on the first interlayer insulating film 11 as the lower electrode adhesion film 12 by sputtering.

Next, as shown in FIG. 1C, a platinum film having a thickness of about 150 nm is formed on the lower electrode adhesion film 12 as a first conductive film 23 by sputtering. Instead of the platinum film, the first conductive film 23 may be composed of a single layer film of any of an iridium film, a ruthenium film, a ruthenium oxide (RuO ₂ ) film, and a SrRuO ₃ film, or a laminated film thereof. Good.

  In addition, since the lower electrode adhesion film 12 is formed before the first conductive film 23 is formed, the adhesion between the first conductive film 23 and the first interlayer insulating film 11 is enhanced.

Next, as shown in FIG. 2A, PZT (Pb (Zr _x , Ti) is formed as a first ferroelectric film 24b on the first conductive film 23 by RF (Radio Frequency) sputtering using a PZT target. _{A 1-x} ) O ₃ (0 ≦ x ≦ 1)) film is formed to a thickness of about 90 nm.

The first ferroelectric film 24b is not limited to PZT. The first ferroelectric film 24b may be made of a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT. Further, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and Bi layered compounds such as SrBi ₄ Ti ₄ O ₁₅ The first ferroelectric film 24b may be configured.

  The film formation method of the first ferroelectric film 24b is not limited to the sputtering method, and the first ferroelectric film 24b may be formed by a sol-gel method or a MOCVD (Metal Organic CVD) method.

  By the way, the first ferroelectric film 24b formed by the sputtering method as described above is not crystallized immediately after the film formation and is in an amorphous state and has poor ferroelectric characteristics.

  Therefore, in order to crystallize the first ferroelectric film 24b, as shown in FIG. 2B, crystallization annealing is performed on the first ferroelectric film 24b. The crystallization annealing is performed by RTA (Rapid Thermal Anneal) in an oxygen-containing atmosphere, for example, an atmosphere composed of oxygen and argon adjusted to have an oxygen concentration of 1.25%, the substrate temperature is 600 ° C., and the processing time. Is 90 seconds.

  As a result, the first ferroelectric film 24b is crystallized, and a large number of PZT crystal grains are formed in the film.

  When the first ferroelectric film 24b is formed by the MOCVD method, the first ferroelectric film 24b is crystallized at the time of film formation, and thus the above crystallization annealing is not necessary.

  Next, as shown in FIG. 3A, an amorphous PZT film having a thickness of about 30 nm is formed on the first ferroelectric film 24b as the second ferroelectric film 24c by RF sputtering. .

The second ferroelectric film 24c is not limited to a PZT film, and the first ferroelectric film 24b is made of a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT. Also good. Further, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and Bi layered compounds such as SrBi ₄ Ti ₄ O ₁₅ The first ferroelectric film 24b may be configured.

  Of these materials, the second ferroelectric film 24c is preferably made of the same material as the first ferroelectric film 24b.

  After the second ferroelectric film 24c is thus formed, the process proceeds to a process of forming a second conductive film for the upper electrode on the second ferroelectric film 24c.

  In this example, a sputtering chamber for forming the second ferroelectric film 24c and a sputtering chamber for forming the second conductive film are provided in separate semiconductor manufacturing apparatuses in the clean room. It is assumed that

  Therefore, after forming the second ferroelectric film 24c, the silicon substrate 1 is once exposed to the atmosphere in order to be transferred to the sputtering chamber for the second conductive film.

  However, when the silicon substrate 1 is exposed to the atmosphere in this way, impurities such as organic substances in the atmosphere are adsorbed to the amorphous second ferroelectric film 24c, and the second ferroelectric film 24c and the above-described first 2 Adhesiveness with the conductive film may be reduced.

  Therefore, in the present embodiment, as shown in FIG. 3B, the second ferroelectric film 24c is formed in a non-plasma atmosphere in order to remove impurities attached to the second ferroelectric film 24c during atmospheric transfer. Anneal.

The annealing is performed for 60 seconds in a reduced-pressure atmosphere having a pressure of about 5.0 × 10 ⁻⁶ Pa at a substrate temperature of 100 to 350 ° C., for example, 150 ° C.

This annealing atmosphere is not particularly limited. However, when a reducing substance such as hydrogen is present in the atmosphere, the first and second ferroelectric films 24b and 24c are reduced by these substances, and the ferroelectric characteristics thereof are deteriorated. Therefore, it is preferable to perform the above annealing in an atmosphere from which hydrogen is excluded. As such an atmosphere, for example, there is any atmosphere of Ar, N ₂ , and O ₂ . Among these, if annealing is performed in an O ₂ atmosphere, there is also an advantage that oxygen vacancies in the first and second ferroelectric films 24b and 24c are compensated.

  The atmospheric pressure may be atmospheric pressure, but it is easier to remove impurities such as organic substances adhering to the second ferroelectric film 24c when annealing is performed under reduced pressure as described above.

  Here, if the substrate temperature during the annealing is equal to or higher than the crystallization temperature of PZT, the second ferroelectric film 24c is crystallized by the annealing. In this case, when a second conductive film described later is formed on the second ferroelectric film 24c, a leak path is formed by the material of the second conductive film that has entered the crystal grain boundary of the second ferroelectric film 24c. .

  Therefore, in order to reduce the leakage current in the second ferroelectric film 24c, the substrate temperature of this annealing needs to be lower than the crystallization temperature of the second ferroelectric film 24c. When the second ferroelectric film 24c is formed of PZT as in this embodiment, it is necessary to anneal at a temperature lower than 450 ° C., which is the crystallization temperature of PZT.

  Further, the annealing method is not particularly limited. For example, annealing may be performed using a stage of a heating chamber or a sputtering chamber, or annealing may be performed using an RTA chamber or a furnace.

  Subsequently, after this annealing is finished, as shown in FIG. 4A, an iridium oxide film is formed on the second ferroelectric film 24c as a second conductive film 25 by sputtering to a thickness of about 50 nm. .

  In the present embodiment, since the atmospheric impurities absorbed by the second ferroelectric film 24c in the step of FIG. 3B are previously removed by annealing, the second ferroelectric film 24c and the second ferroelectric film 24c are removed by the impurities. It can prevent that adhesiveness with 2 electrically conductive film 25 falls.

  Thereafter, crystallization annealing is performed on the second ferroelectric film 24c in an oxygen-containing atmosphere to crystallize the amorphous second ferroelectric film 24c, and the first ferroelectric film below the second ferroelectric film 24c is crystallized. The crystallinity of 24b is further increased.

  Although the annealing conditions are not particularly limited, in this embodiment, the substrate temperature is 708 ° C. and the processing time is 20 seconds. Further, as an oxygen-containing atmosphere in which annealing is performed, a mixed atmosphere of oxygen gas and argon gas whose oxygen concentration is adjusted to 1% is used.

  When the second ferroelectric film 24c is crystallized in the state where the second conductive film 25 is formed in this way, iridium oxide constituting the second conductive film 25 becomes a crystal grain boundary of the second ferroelectric film 24c. Intrusion can be prevented, and the formation of a leak path in the second ferroelectric film 24c due to iridium oxide can be suppressed.

  Further, this annealing also provides an advantage that oxygen is supplied to the second ferroelectric film 24c through the second conductive film 25 and oxygen deficiency of the second ferroelectric film 24c is compensated.

  In order to obtain such advantages, the thickness of the second conductive film 25 is preferably thin so that oxygen can easily pass through, for example, 10 to 100 nm.

  However, if the thin second conductive film 25 is formed on the second ferroelectric film 24c in this way, damage in the subsequent etching process or the like cannot be absorbed by the second conductive film 25 alone, and the first and second films The ferroelectric films 24b and 24c may be deteriorated.

  Therefore, in the next step, as shown in FIG. 4B, sputtering is performed on the second conductive film 25 as the conductive protective film 26 for protecting the first and second ferroelectric films 24b and 24c. By this method, an iridium oxide film is formed to a thickness of about 200 nm.

  Next, as shown in FIG. 5A, the first conductive film 23, the first and second ferroelectric films 24b and 24c, and the second conductive film 25 are separately patterned.

  Thus, a capacitor Q is formed in the cell region of the silicon substrate 1 by laminating the lower electrode 23a, the capacitor dielectric film 24a, and the upper electrode 25a in this order.

  The lower electrode 23a has a contact region CR that protrudes from the capacitor dielectric film 24a. In the contact region CR, a metal wiring described later and the lower electrode 23a are electrically connected.

  In this patterning, the lower electrode adhesion film 12 is also etched, and the lower electrode adhesion 12 is left only under the lower electrode 23a.

  Subsequently, as shown in FIG. 5B, an alumina film is formed on the entire upper surface of the silicon substrate 1 by a sputtering method as a capacitor protective insulating film 32 for protecting the capacitor Q from a reducing substance such as hydrogen. Formed to 50 nm.

  In addition, after the capacitor protection insulating film 32 is formed, the capacitor dielectric film 24a may be annealed in an oxygen-containing atmosphere in order to recover the damage received by the capacitor dielectric 24a during the process. Such annealing is also called recovery annealing.

Next, as shown in FIG. 6A, a silicon oxide film having a thickness of about 1500 nm is formed on the capacitor protection insulating film 32 by HDPCVD (High Density Plasma CVD) using silane (SiH ₄ ) gas. The silicon oxide film is used as the second interlayer insulating film 41. Furthermore, the upper surface of the second interlayer insulating film 41 is polished and planarized by the CMP method.

Thereafter, by performing N ₂ O plasma treatment on the second interlayer insulating film 41, the second interlayer insulating film 41 is dehydrated, and the upper surface of the second interlayer insulating film 41 is slightly nitrided to rehydrate moisture. Prevent adsorption.

  Next, steps required until a sectional structure shown in FIG.

  First, the respective films 10, 11, 32, 41 are patterned by photolithography and dry etching, and the first and second holes 41a, 41a are formed in these films on the first and second source / drain regions 8a, 8b. 41b is formed.

  Thereafter, a titanium film and a titanium nitride film are formed on the inner surfaces of the first and second contact holes 41a and 41b and the upper surface of the second interlayer insulating film 41 by sputtering to a thickness of 20 nm and 50 nm, respectively. Is a glue film (adhesion film). Next, a tungsten film is formed on the glue film by a CVD method using tungsten hexafluoride gas, and the first and second contact holes 41a and 41b are completely filled with the tungsten film.

  Thereafter, excess glue film and tungsten film on the second interlayer insulating film 41 are removed by polishing by the CMP method, and these films are first and second only in the first and second contact holes 41a and 41b. Two conductive plugs 61a and 61b are left. The conductive plugs 61a and 61b are electrically connected to the first and second source / drain regions 8a and 8b, respectively.

  Here, since the first and second conductive plugs 61a and 61b are mainly composed of tungsten that is easily oxidized, there is a possibility that the first and second conductive plugs 61a and 61b are easily oxidized in an oxygen-containing atmosphere and cause contact failure.

  Therefore, in the next step, as shown in FIG. 7A, a silicon oxynitride film is formed as an anti-oxidation insulating film 55 on the entire upper surface of the silicon substrate 1 to a thickness of about 100 nm by the CVD method. The film 55 prevents the first and second conductive plugs 61a and 61b from being oxidized.

  Thereafter, the layers from the antioxidant insulating film 55 to the capacitor protective insulating film 32 are patterned by photolithography and dry etching. As a result, a third hole 41c is formed in these insulating films on the contact region CR of the lower electrode 23a, and a fourth hole 41d is formed on the upper electrode 25a.

  Thereafter, in order to recover the damage received by the capacitor dielectric film 24a in the steps so far, the silicon substrate 1 is put into a vertical furnace having an oxygen-containing atmosphere, the substrate temperature is 500 ° C., and the processing time is 60 minutes. Under conditions, recovery annealing is performed on the capacitor dielectric film 24a.

  Next, steps required until a sectional structure shown in FIG.

  First, a metal laminated film is formed on the upper surfaces of the second interlayer insulating film 41 and the first and second conductive plugs 61a and 61b by sputtering. In the present embodiment, the metal laminated film includes a titanium nitride film having a thickness of about 150 nm, a copper-containing aluminum film having a thickness of about 550 nm, a titanium film having a thickness of about 5 nm, and a titanium nitride having a thickness of about 150 nm. A film is formed in this order. This metal laminated film is also formed in the third and fourth holes 41c and 41d on the capacitor Q.

  Then, by patterning this metal laminated film by photolithography and dry etching, the metal wiring 62 electrically connected to the capacitor Q and the conductive plugs 61a and 61b is formed.

Thereafter, using a vertical furnace in a nitrogen atmosphere, for example, the second interlayer insulating film 41 is annealed and dehydrated under conditions of a substrate temperature of 350 ° C., an N ₂ flow rate of 20 liters / minute, and a processing time of 30 minutes.

  Thus, the basic structure of the semiconductor device according to this embodiment is completed.

  FIG. 8 is a flowchart of the method for manufacturing the semiconductor device. However, in the figure, only the main processes S1 to S5 are shown among various processes.

  As shown in FIG. 8, in the present embodiment, in step S3, the amorphous second ferroelectric film 24c is annealed in a non-plasma atmosphere to thereby form the second ferroelectric film 23c. Impurities such as adhering atmospheric organic substances were removed.

  As a result, the second ferroelectric film 24c is cleaned, and degassing generated from the second ferroelectric film 24c during the crystallization annealing (step S5) for the second ferroelectric film 24c is reduced. Is done. As a result, the adhesion between the second conductive film 25 and the second ferroelectric film 24c is improved, and defects such as film peeling and floating of the upper electrode 25a can be prevented, thereby improving the yield of the semiconductor device. Can do.

  The inventor of the present application investigated how much defects are actually reduced by such annealing. The wafer map obtained by the investigation is as shown in FIGS. 9 (a) and 9 (b).

  Among these, FIG. 9A is a wafer map according to a comparative example, and FIG. 9B is a wafer map according to the present embodiment.

  In the comparative example shown in FIG. 9A, after forming the amorphous second ferroelectric film 24c, the annealing in step S3 is omitted, and the second ferroelectric film 24c is left in the atmosphere for three days. Thereafter, the second conductive film 25 was formed.

  As shown in the figure, in this case, an extremely large number of defects indicated by black circles are formed on the silicon substrate 1. Most of these defects are caused by the film peeling of the upper electrode 25a as described above.

  On the other hand, in the present embodiment shown in FIG. 9B, the number of defects is considerably smaller than that of the comparative example described above. The defect shown in the figure is due to a factor different from the film peeling of the upper electrode 25a.

  From these results, it was actually confirmed that the yield of the semiconductor device is improved by removing the impurities of the second ferroelectric film 24c before the formation of the second conductive film 25.

  Although various impurities are contained in the atmosphere, according to the investigation by the inventors of the present application, when the second conductive film 25 is peeled off, carbonate or the like is present on the surface of the second ferroelectric film 24c. It became clear that it might exist. From this, it is considered that one of the causes of the peeling of the second conductive film 25 is that an organic substance in the atmosphere reacts with a metal in the ferroelectric film to generate carbonate. Therefore, by performing the above annealing in an atmosphere from which a carbon source such as carbon dioxide is excluded, impurities such as organic substances adhering to the second ferroelectric film 24c can be effectively removed. It can be expected that the effect of preventing the peeling of the two conductive films 25 is increased. The same applies to first and second modified examples and the second embodiment described later.

  Next, a modification of the present embodiment will be described.

(A) First Modification FIG. 10 is a flowchart showing a method for manufacturing a semiconductor device according to this modification. In FIG. 10, the same steps as those in FIG. 8 are denoted by the same steps as those in FIG.

  In this modification, step S3 and step S4 are performed continuously without exposing the silicon substrate 1 to the atmosphere. Such a process can be performed, for example, by continuously forming the second conductive film 25 in step S4 in a sputtering chamber provided in the same semiconductor manufacturing apparatus as the annealing chamber used in step S3.

  This prevents atmospheric impurities and the like from reattaching to the second ferroelectric film 24c after annealing in step S3, and the adhesion between the second ferroelectric film 24c and the second conductive film 25 is prevented. It becomes possible to further improve the property.

  In the case where the step S3 and the step S4 are continuously performed as described above, the effect of preventing the upper electrode 25a from peeling off can be seen even if the substrate temperature in the annealing in the step S3 is slightly lower than the above. According to the experience of the present inventor, the substrate temperature at which such an effect is seen is 100 to 250 ° C.

(B) Second Modification FIG. 11 is a flowchart showing a method for manufacturing a semiconductor device according to this modification. In FIG. 11, the same steps as those in FIG. 8 are denoted by the same steps as those in FIG.

  In the present modification, in step S3, the second ferroelectric film 24c is annealed in a plasma atmosphere, thereby removing impurities in the air adsorbed by the second ferroelectric film 24c.

As such a plasma atmosphere, for example, there is an O ₂ plasma atmosphere or an N ₂ O plasma atmosphere.

Among these, annealing in an O ₂ plasma atmosphere can be performed using, for example, an ashing chamber for ashing and removing the resist. The annealing conditions are not particularly limited. For example, a substrate temperature of 150 ° C., a pressure of 133 Pa, and a processing time of 30 seconds can be employed.

In order to prevent the reduction of the first and second ferroelectric films 24b and 24c with hydrogen, it is preferable to perform this annealing in a plasma atmosphere from which hydrogen is excluded, and it is preferable to use H ₂ plasma or NH ₃ plasma. Absent.

(C) Third Modification FIG. 12 is a flowchart showing a method for manufacturing a semiconductor device according to this modification. In FIG. 12, the same steps as those in FIG. 8 are denoted by the same steps as those in FIG.

  In the present modification, in step S3, the surface of the second ferroelectric film 24c is washed with water to remove impurities in the atmosphere adsorbed by the second ferroelectric film 24c.

  The method of washing with water is not particularly limited, and a batch-type washing apparatus that immerses a plurality of silicon substrates 1 in a liquid tank in which pure water is stored may be used, or a silicon substrate rotating on a spinner A single-wafer type cleaning apparatus that drops pure water to 1 for cleaning may be used.

  After washing with water in this way, for example, after performing IPA drying in which the second ferroelectric film 24c is dried in an atmosphere containing IPA (isopropyl alcohol), the process proceeds to step S4. 2 The second conductive film 25 is formed on the ferroelectric film 24c.

  In addition to the IPA drying described above, the drying method of the second ferroelectric film 24c after cleaning includes natural drying in the air and heat drying in which the silicon substrate 1 is heated to about 150 ° C. in the air. .

(2) Second Embodiment The above-described first embodiment and its modification are based on the idea that impurities in the atmosphere absorbed by the second ferroelectric film 24c are removed by annealing or the like.

  On the other hand, the present embodiment is different from the first embodiment in that the second ferroelectric film 24c is subjected to a process that makes it difficult to absorb impurities even when exposed to the atmosphere. The rest is the same as in the first embodiment, and the basic structure of FeRAM can be formed according to the steps described with reference to FIGS.

  FIG. 13 is a flowchart in which only the main steps of the semiconductor device manufacturing method according to the present embodiment are extracted. The same steps as those described in the first embodiment are denoted by the same step numbers as those in the first embodiment. It is.

  As shown in this figure, in the present embodiment, after the amorphous second ferroelectric film 24c is formed in step S2, the second ferroelectric film 24c is exposed to the atmosphere without being exposed to the atmosphere. The ferroelectric film 24c is annealed.

Such a continuous treatment of the formation of the second ferroelectric film 24c and the annealing is performed, for example, after the second ferroelectric film 24c is formed in the sputtering chamber, and then the sputtering chamber is continuously used in the sputtering chamber. This can be done by annealing. In this case, no voltage is applied between the PZT target in the sputtering chamber and the stage during annealing. Then, the stage temperature is set to 350 ° C., for example, the pressure in the chamber is reduced to a pressure of about 5.0 × 10 ⁻⁶ Pa, and this state is maintained for 60 seconds, thereby annealing the second ferroelectric film 24c. Can be performed in a non-plasma atmosphere.

  However, if the substrate temperature during this annealing is equal to or higher than the crystallization temperature of the second ferroelectric film 24c, as described in the first embodiment, the second strong conductive film 25 is formed before the second conductive film 25 is formed by this annealing. Since the dielectric film 24c is crystallized, a leak path is formed by the second conductive film 25 entering the crystal grain boundary of the second ferroelectric film 24c. Therefore, the substrate temperature in this annealing needs to be set to a temperature lower than the crystallization temperature of the second ferroelectric film 24c. For example, when the second ferroelectric film 24c is made of PZT, it is necessary to perform this annealing at a substrate temperature lower than the crystallization temperature (450 ° C.) of PZT.

  Further, if hydrogen is contained in the annealing atmosphere, the first and second ferroelectric films 24b and 24c are reduced by the hydrogen and the ferroelectric characteristics are deteriorated. Among these, it is preferable to perform this annealing.

  When annealing is performed in this manner, the amorphous second ferroelectric film 24c becomes difficult to absorb impurities such as carbon in the atmosphere.

  Therefore, even if the second ferroelectric film 24c is exposed to the atmosphere between the annealing and the formation of the second conductive film 25 in step S4, the second ferroelectric is caused by impurities in the atmosphere. It can prevent that the adhesiveness of the film | membrane 24c and the 2nd electrically conductive film 25 falls.

  In the first embodiment, when the second ferroelectric film 24c is annealed in a non-plasma atmosphere, the substrate temperature at the time of annealing is set to 100 to 350 ° C. so that the second ferroelectric film 24c is adsorbed to the second ferroelectric film 24c. Impurities in the atmosphere could be removed.

  On the other hand, the effect of preventing adsorption of impurities as in the present embodiment can be easily obtained by setting the substrate temperature during annealing in step S3 to 200 to 400 ° C. higher than the above.

  Further, in the present embodiment, when the amorphous second ferroelectric film 24c is annealed as described above, if carbon is contained in the annealing atmosphere, the carbon of the second ferroelectric film 24c is caused by the carbon. There is a possibility that the surface will be contaminated and the adhesion between the second ferroelectric film 24c and the second conductive film 25 may be reduced. Therefore, similarly to the first embodiment, in this embodiment, it is preferable to perform annealing in an atmosphere in which a carbon source such as carbon dioxide is excluded.

  The features of the present invention are added below.

(Additional remark 1) The process of forming an insulating film above a semiconductor substrate,
Forming a first conductive film on the insulating film;
Forming a crystallized first ferroelectric film on the first conductive film;
Forming an amorphous second ferroelectric film on the first ferroelectric film;
Annealing the second ferroelectric film at a substrate temperature lower than the crystallization temperature of the second ferroelectric film;
Forming a second conductive film on the second ferroelectric film;
After forming the second conductive film, crystallizing the second ferroelectric film;
A method for manufacturing a semiconductor device, comprising:

  (Supplementary Note 2) After the step of crystallizing the second ferroelectric film, the first and second conductive films and the first and second ferroelectric films are patterned to form a lower electrode and a capacitor dielectric film. The method for manufacturing a semiconductor device according to appendix 1, further comprising a step of forming a capacitor including an upper electrode.

  (Additional remark 3) The said annealing is performed in the non-plasma atmosphere or plasma atmosphere from which hydrogen was excluded, The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.

(Supplementary note 4) The method for manufacturing a semiconductor device according to supplementary note 3, wherein the non-plasma atmosphere is an atmosphere of Ar, N ₂ , or O ₂ , or a reduced-pressure atmosphere.

(Supplementary Note 5) The plasma atmosphere, a method of manufacturing a semiconductor device according to note 3, characterized in that the O ₂ plasma atmosphere or an N ₂ O plasma atmosphere.

  (Supplementary note 6) The supplementary notes 1 to 5, wherein the second ferroelectric film is exposed to air between the step of forming the second ferroelectric film and the step of annealing. The manufacturing method of the semiconductor device in any one.

  (Additional remark 7) The said substrate temperature in the said annealing is set to the range of 100 to 350 degreeC, The manufacturing method of the semiconductor device of Additional remark 6 characterized by the above-mentioned.

  (Supplementary note 8) The semiconductor device according to any one of supplementary notes 1 to 7, wherein after the annealing, the process proceeds to a step of forming the second conductive film without exposing the second ferroelectric film to the atmosphere. Manufacturing method.

  (Additional remark 9) The said substrate temperature in the said annealing is set to the range of 100-250 degreeC, The manufacturing method of the semiconductor device of Additional remark 8 characterized by the above-mentioned.

  (Additional remark 10) After forming the said 2nd ferroelectric film, the said annealing process is performed, without exposing this 2nd ferroelectric film to air | atmosphere, The additional description 1-5 characterized by the above-mentioned. A method for manufacturing a semiconductor device.

  (Supplementary note 11) The supplementary note, wherein the second ferroelectric film is exposed to the atmosphere between the step of annealing the second ferroelectric film and the step of forming the second conductive film. 10. A method for manufacturing a semiconductor device according to 10.

  (Supplementary note 12) The method for manufacturing a semiconductor device according to supplementary note 11, wherein the step of annealing the second ferroelectric film is performed in a reduced-pressure atmosphere from which hydrogen is excluded.

(Additional remark 13) The process of forming an insulating film above a semiconductor substrate,
Forming a first conductive film on the insulating film;
Forming a crystallized first ferroelectric film on the first conductive film;
Forming an amorphous second ferroelectric film on the first ferroelectric film;
Washing the surface of the second ferroelectric film with water;
After the water washing, forming a second conductive film on the second ferroelectric film;
After forming the second conductive film, crystallizing the second ferroelectric film;
A method for manufacturing a semiconductor device, comprising:

1A to 1C are cross-sectional views (part 1) of the semiconductor device according to the first embodiment of the present invention in the middle of manufacture. 2A and 2B are cross-sectional views (part 2) of the semiconductor device according to the first embodiment of the present invention during manufacture. 3A and 3B are cross-sectional views (part 3) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. 4A and 4B are cross-sectional views (part 4) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 5A and 5B are cross-sectional views (part 5) in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. 6A and 6B are cross-sectional views (part 6) of the semiconductor device according to the first embodiment of the present invention during manufacture. 7A and 7B are cross-sectional views (part 7) of the semiconductor device according to the first embodiment of the present invention in the middle of manufacture. FIG. 8 is a flowchart of the semiconductor device manufacturing method according to the first embodiment of the present invention. FIGS. 9A and 9B are wafer maps obtained by investigating how much defects are reduced in the first embodiment of the present invention. FIG. 10 is a flowchart showing a method for manufacturing a semiconductor device according to a first modification of the first embodiment of the present invention. FIG. 11 is a flowchart showing a method for manufacturing a semiconductor device according to a second modification of the first embodiment of the present invention. FIG. 12 is a flowchart showing a method for manufacturing a semiconductor device according to a third modification of the first embodiment of the present invention. FIG. 13 is a flowchart of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating film, 3 ... p well, 4 ... gate insulating film, 5 ... gate electrode, 6a, 6b ... 1st, 2nd source / drain extension, 7 ... insulating side wall, 8a 8b: first and second source / drain regions, 10: antioxidation insulating film, 11: first interlayer insulating film, 12: lower electrode adhesion film, 23: first conductive film, 23a: lower electrode, 24a: capacitor Dielectric film, 24b ... first ferroelectric film, 24c ... second ferroelectric film, 25 ... second conductive film, 25a ... upper electrode, 26 ... conductive protective film, 32 ... capacitor protective insulating film, 41 ... the second interlayer insulating film, 41a to 41c ... first to fourth holes, 55 ... oxidation-preventing insulating film, 61a, 61b ... first and second conductive plugs, 62 ... metal wiring, Q ... capacitor, TR _1, TR ₂ : First and second MOS transistors.

Claims (6)

Forming an insulating film above the semiconductor substrate;
Forming a first conductive film on the insulating film;
Forming a crystallized first ferroelectric film on the first conductive film;
Forming an amorphous second ferroelectric film on the first ferroelectric film;
Annealing the second ferroelectric film at a substrate temperature lower than the crystallization temperature of the second ferroelectric film;
Forming a second conductive film on the second ferroelectric film;
After forming the second conductive film, crystallizing the second ferroelectric film;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the annealing is performed in a non-plasma atmosphere or a plasma atmosphere from which hydrogen is excluded. The method of manufacturing a semiconductor device according to claim 2, wherein the non-plasma atmosphere is an atmosphere of any one of Ar, N ₂ , and O ₂ , or a reduced pressure atmosphere.   4. The method according to claim 1, wherein after the annealing, the process proceeds to a step of forming the second conductive film without exposing the second ferroelectric film to the atmosphere. A method for manufacturing a semiconductor device.   4. The method according to claim 1, wherein after the formation of the second ferroelectric film, the annealing step is performed without exposing the second ferroelectric film to the atmosphere. The manufacturing method of the semiconductor device of description. Forming an insulating film above the semiconductor substrate;
Forming a first conductive film on the insulating film;
Forming a crystallized first ferroelectric film on the first conductive film;
Forming an amorphous second ferroelectric film on the first ferroelectric film;
Washing the surface of the second ferroelectric film with water;
After the water washing, forming a second conductive film on the second ferroelectric film;
After forming the second conductive film, crystallizing the second ferroelectric film;
A method for manufacturing a semiconductor device, comprising:

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