JP2009239184A - Multilayer printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-density multilayer printed wiring board which can achieve compatibility between a via filling performance or getting through performance to the inside of a via hole and interlayer insulation reliability along with a finer wiring pattern and a via of a decreased diameter. <P>SOLUTION: In the multilayer printed wiring board having inner layer circuits, a via receiving land to be connected with an upper layer and a wiring circuit are provided on at least one of the inner layer circuits. The inner layer circuits satisfy a relationship, Tr>Tv>Tl, when the via receiving land has a thickness of Tv, the wiring circuit has a thickness of Tl, and an interlayer insulating resin laminated on the inner circuit has a thickness of Tr. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a high density multilayer printed wiring board.

In recent years, with the increase in functionality, miniaturization and thinning of electronic devices, high-density mounting of electronic components is rapidly progressing. In response to these demands, printed wiring boards are required to have higher wiring density, smaller size, thinner thickness, and higher reliability. There are two methods for forming a circuit of a printed wiring board, a subtractive method and a semi-additive method. With the recent increase in wiring density, particularly in a printed wiring board having a fine circuit, a semi-additive method is advantageous. Law is becoming mainstream.

The manufacturing method of the multilayer printed wiring board by a semi-additive construction method is demonstrated. First, a printed wiring board in which only two layers on the front and back sides or one or more layers of wiring circuits are formed on the interior of the printed wiring board, and a two-layer or multi-layer core board in which electrical connection between layers is made using a known method is used. prepare. An interlayer insulating resin layer is formed on the core substrate plane. By irradiating the via receiving land formed in the core substrate circuit with the UV or carbon dioxide gas laser and penetrating the via receiving land surface, the interlayer is formed between the insulating resin layers. Conductive blind via holes are formed. Subsequent immersion in an alkaline hot solution containing a resin oxidant removes the laser processing residue adhering to the via hole (desmear treatment) and improves the adhesion between the insulating resin surface and the laminating resin or chemical copper plating. The intended roughening treatment is performed. After a step of applying a catalyst for chemical copper plating on the roughened resin, after forming a chemical copper plating layer having a thickness of about 0.1 to 3 μm in the insulating resin flat portion and the via hole, a dry film resist is formed. Heat laminate. Subsequently, the dry film resist layer is exposed and developed using a desired mask pattern to form a dry film resist pattern opposite to the conductor circuit. Further, electrolytic copper plating is performed using a chemical copper plating layer as a power feeding layer and a resist pattern as a mold, thereby forming a wiring circuit and via receiving land, and the interlayer connection via and via land. Subsequently, the resist is peeled off, and flash etching is performed to remove an unnecessary chemical copper plating layer, thereby forming a circuit. A multilayer printed wiring board is manufactured by using a built-up method in which these steps are repeatedly laminated several times.

In order to reduce the size of the printed wiring board, the via structure is an important factor as well as the narrowing of the wiring width and wiring interval and the diameter of vias and via receiving lands for interlayer connection. In the case of a filled via structure in which electrolytic copper plating is filled in the via hole, it is possible to further form a via immediately above the via (via on via), or to provide a mounting pad directly on the via (via on pad) if it is the outermost layer of the substrate. It becomes. In other words, in the filled via structure, it is possible to connect multiple layers by stacked vias stacked on the same normal line and to form a mounting pad, so that the degree of freedom in routing the upper and lower interlayers increases, which is a very effective means for space saving. It has become. On the other hand, in a conformal via structure in which the inside of the via is not filled with electrolytically plated copper and a conductor layer is formed along the bottom and side walls of the via, it is difficult to stack vias, and even if stacked, reliable interlayer connection reliability It is difficult to ensure sex. Therefore, after the conductor circuit is newly routed in a place that avoids the position of the lower via, the via receiving land must be provided, and further lamination and via formation must be repeated (stacked via). There was a limit. Therefore, the interlayer connection of the filled via structure has great merits such as higher density, smaller size, and interlayer connection reliability of the printed wiring board.

Filled via plating is achieved by a filled via plating bath that has a function of suppressing copper plating deposition on the plane portion of the substrate and promoting copper deposition into the via hole. The filled via plating bath contains copper sulfate, sulfuric acid, chloride ions and organic additives such as polymer, brightener and leveler. It is said that the leveler is mostly adsorbed on the flat part of the substrate during plating, the adsorbed amount in the via hole is small, and has an action of suppressing the plating film deposition. The leveler is generally an organic dye and is selected from quaternary ammonium compounds. Since it has a cationic property, it preferentially adsorbs at a location where the current density where the amount of electrodeposition increases increases, and it has a uniform electrodeposition (leveling action). Is effective. The brightener is generally selected from sulfur-containing organic compounds and has a function of promoting plating deposition. Since the adsorption of Brightner to the substrate flat portion is hindered by the preferential adsorption of the leveler and the polymer, the effect of promoting plating deposition on the substrate flat portion is suppressed. On the other hand, the leveler with a relatively large molecular weight inside the via hole and the adsorption amount of the polymer component are small, and the brightener which is a relatively low molecule easily diffuses into the hole, so it diffuses and adsorbs inside the via hole. To promote plating deposition. As plating deposits in the via holes, the surface area of the recesses further decreases, so that the adsorbed brightener concentrates and concentrates in the via recesses, and is further promoted to perform via filling. The polymer is generally selected from water-soluble polymers such as polyethylene glycol and has a high molecular weight like the leveler, and therefore has an action of suppressing electrodeposition of the plating film due to preferential adsorption on the substrate surface. Numerous inventions relating to filled via plating baths that make use of the effects of the above components to achieve both via filling and uniform electrodeposition have been made.

In the case of manufacturing a high-density multilayer printed wiring board having a filled via structure by the semi-additive method, in the electrolytic plating process, the wiring circuit portion formed on the substrate plane and the via receiving land portion from the upper layer are located below the substrate plane. A via hole that penetrates the insulating resin layer and reaches the lower via receiving land and a via land portion formed immediately above the via hole are collectively formed by one filled via plating. That is, the required plating thickness of the filled via and the via land formation portion immediately above is thicker than the wiring and via receiving land portion of the substrate flat portion by the thickness of the penetrating resin, and therefore, sufficient via filling properties are indispensable.

In Patent Documents 1 to 5 below, many inventions for improving both the via filling property and the uniform electrodeposition property by examining an organic additive having a filled via plating solution composition have been studied. However, in order to inevitably complete the filling, it was necessary to secure the amount of electrolytic plating. Therefore, the variation in the plating thickness increases as the amount of electrolytic plating increases. In particular, in a large workpiece having a size of 500 × 600 mm, which is the manufacturing substrate size of a multilayer wiring board, it cannot be said that the throwing power is still sufficient, and this problem becomes remarkable particularly when a fine wiring having a pitch of 30 μm or less is formed. Furthermore, since the leveler component has a relatively large molecular weight, the mass transfer from the plating solution to the substrate surface affects the suppressing action. Accordingly, the higher the liquid flow rate in the bath and the more liquid supply, the stronger the adsorption suppressing action. That is, it cannot be denied that the throwing power is changed by the liquid flow. Furthermore, when the blending ratio of the polymer with the inhibitory action of the organic additive of filled via plating, the brighter with the promoting action and the leveler is optimized in the direction of improving the filling property, the uniform electrodeposition property in the work surface is lowered. There was a trend and there was a trade-off relationship.

JP 2000-297395 A JP 2002-249891 JP 2004-346381 JP 2006-249478 A JP2007-107074

Due to the above reasons, via filling via plating and via land formation directly above, and wiring circuit on the substrate plane and via receiving land from the upper layer are formed on the substrate when filling via plating is performed at once. As a result, the variation in the plating height of the conductor circuit was inevitably increased. Therefore, in actual production, it is necessary to determine the dry film resist thickness to be the mold in consideration of the via filling properties and the plating conditions for completing the via land formation, the wiring thickness finish at that time, and the plating thickness variation range. In order to avoid overplating, a dry film resist having a sufficient thickness was selected so that a margin was taken. For this reason, it has been difficult to easily reduce the thickness of the dry film resist. Furthermore, in the case of conformal vias, if the via aspect becomes high due to a reduction in diameter, etc., the copper coverage in the hole will decrease, so if you try to maintain a certain thickness of via conductor in the via, As a result, the plating of the circuit portion and the via receiving land portion becomes thick and the variation increases.

The miniaturization of wiring in the semi-additive method is almost determined by the resolution and fine line adhesion of the resist as a mold. Furthermore, the resolution and fine line adhesion of the resist greatly depend on the thickness of the dry film resist, and the thinner the dry film resist, the better the resolution and fine line adhesion. In wiring formation in the conventional semi-additive method, the thickness of the dry film resist must be set to cope with the plating thickness variation caused by ensuring the via fillability or the wearability within the hole of conformal via plating. Therefore, a thick dry film resist has to be used, which has been an obstacle to miniaturization of wiring. In particular, it is extremely difficult to form fine wiring with a wiring pitch of 30 μm or less, and further 20 μm or less.

In order to reduce the size of the multilayer printed wiring board, it is necessary to reduce the via structure, the via diameter, the via land diameter, and the lower via receiving land diameter. Technical issues to achieve via diameter reduction include laser processing, as well as desmearing, via filling, and conformal via plating, ensuring in-hole wearability, interlayer connection reliability, and interlayer insulation. Is mentioned. In laser processing, the processing difficulty generally increases as the processing depth increases. The shape is a taper shape having a large opening diameter on the resin surface and a small diameter on the bottom surface and the surface of the lower via receiving land. Interlayer connection reliability improves as the via grounding area increases, so the thinner the insulating resin thickness, the more advantageous. It is equally important to remove processing residues by desmearing, sufficiently clean the underlying via receiving land copper surface, and ensure adhesion of via plating. In the desmear treatment in the via hole, the higher the via aspect ratio, the harder the chemical solution enters and the harder the treatment. Therefore, the desmear treatment is more advantageous as the interlayer insulating resin layer is thinner.

Regarding the via filling property or the wearability within the hole, the via aspect ratio increases when the via diameter is reduced while the resin thickness is kept constant. As the via aspect increases, the brightener and copper ion supply to the bottom of the hole tends to stagnate, so the degree of difficulty in via filling tends to increase, causing embedding defects such as voids and seams inside the via, and Reliability is reduced. As for via filling properties, when the diameter of the via is reduced, it is generally advantageous to make the insulating resin thin as well. Similarly, as the via aspect increases, the wearability within the conformal via hole tends to decrease due to insufficient supply of copper ions.

From the above, the laser processability, desmear property, interlayer connection reliability, via filling property, or reachability inside the via hole are more advantageous as the laminated insulating resin thickness is thinner, while the interlayer insulation reliability The thicker the thickness, the wider the margin for migration. Therefore, it is necessary to ensure a certain thickness of interlayer insulating resin. That is, a technology that can satisfy these two problems is indispensable for miniaturization of a multilayer printed wiring board by miniaturization of a via by reducing the diameter of the via. An object of the present invention is to provide a high-density multilayer printed wiring board that solves these problems.

As a result of intensive studies on the above-mentioned problems, the present inventors have reached the present invention. That is, in a multilayer printed wiring board having at least an inner layer circuit, a via receiving land for a via connecting to an upper layer is provided on at least one inner layer circuit, and a wiring circuit is provided on the same layer. A multilayer printed wiring board having an inner circuit where Tr>Tv> Tl, where Tv is the thickness of the wiring circuit, Tl is the thickness of the wiring circuit, and Tr is the thickness of the interlayer insulating resin laminated on the internal circuit, To do.
Further, the via receiving land has a first layer having a thickness substantially the same as that of the wiring circuit and a second layer on the first layer, and is a multilayer printed wiring board.
Further, the second layer is a metal plating layer, and is a multilayer printed wiring board.

Furthermore, as a method for producing a multilayer printed wiring board, there is provided a via receiving land for vias connected to the upper layer on at least one inner layer circuit, and a method for producing a multilayer printed wiring board provided with a wiring circuit, In the manufacturing process of the inner layer circuit, a wiring circuit and a via receiving land first layer are formed on an insulating resin, and a via receiving land second layer is selectively formed on the first via receiving land by electrolytic plating. A process for producing a multilayer printed wiring board.

In the multilayer printed wiring board according to the present invention, the thickness of the via receiving land for achieving interlayer conduction with the upper layer provided on the inner layer circuit is set to be thicker than the thickness of the wiring circuit formed on the inner layer circuit. The thickness is set to be equal to or less than the thickness of the interlayer insulating resin laminated. If the via receiving land for interlayer conduction is set thicker than other circuits, and the interlayer insulating resin is laminated on the circuit to form a via hole, the aspect ratio of the via hole depth / opening width can be greatly reduced. It becomes possible. Even when the diameter of the via is reduced, the via filling property during electrolytic plating, and the case of conformal via plating do not lead to a decrease in the wearability in the via hole, and the via diameter is not reduced. As a result, the via filling property and the in-hole wearability are improved. Therefore, the via land formation immediately above the filled via is finished faster than the conventional method because the via filling property is improved. In the case of conformal vias, the finish of plating in the hole is improved, so that the finish is similarly quick. However, in the prior art, a sufficient amount of electrolytic plating was ensured to ensure via filling properties or reachability in the holes. However, according to the present invention, the amount of electrolytic copper plating can be reduced. Since electrolytic plating increases the wiring height variation as the plating amount increases, according to the present invention, variations in electrolytic plating can be greatly reduced.

In the prior art, the thickness of the dry film resist had to be set in consideration of the via filling properties, the hole wearability and the electrolytic copper plating thickness variation, but according to the present invention, the via filling properties, the hole wearability were increased. Therefore, it is possible to reduce the amount of electrolytic copper plating and improve the variation in electrolytic copper plating thickness, so that the dry film resist thickness can be set thin. In the conventional method, a dry film resist having a thickness of 25 to 30 μm has to be used for a wiring having a pitch of 40 μm. However, according to the method of the present invention, a dry film of 20 μm or less can be used. Furthermore, since the resolution and fine line adhesion of the resist are remarkably improved, it becomes possible to produce a multilayer printed wiring board having a fine wiring layer with a pitch of 30 μm or less.

In the multilayer printed wiring board according to the present invention, since the aspect ratio of the via can be reduced, the laser processing is improved and the productivity is improved, and the laser processing that adheres to the lower via receiving land portion copper surface after the laser processing The desmear process for removing the residue can be performed sufficiently cleanly. That is, a multilayer printed wiring board with high interlayer connection reliability can be manufactured. In the method according to the prior art, since the via aspect ratio is high, the desmear process must be sufficiently performed, and an excessive desmear process causes an increase in the resin dissolution amount in the via part and the substrate plane part. Excessive desmear treatment degrades wiring adhesion by dissolving even fine irregularities effective for adhesion of the resin surface, inhibition of diameter reduction by excessively dissolving the via part, hydrophilic function to the resin surface The electrical reliability is lowered due to the progress of the basicization. Therefore, the multilayer printed wiring board according to the present invention can avoid these problems. This effect is not limited to filled vias, but can also be applied to conformal vias.

Further, since the thickness of the interlayer insulating resin to be laser processed can be set thin, it is easy to reduce the via diameter, and the multilayer printed wiring board can be easily downsized by increasing the wiring density. This effect can be mentioned not only for filled vias but also conformal vias.

In order to reduce the via aspect ratio, it is conceivable to simply reduce the thickness of the interlayer insulating resin to be laminated. However, a decrease in the interlayer insulating resin thickness results in a decrease in interlayer insulating reliability. Therefore, in the multilayer printed wiring board according to the present invention, it is possible to reduce only the via aspect ratio while securing the conventional insulating resin thickness, so that the insulation reliability is not lowered. This effect can be mentioned not only for filled vias but also conformal vias.

As described above, according to the present invention, it is possible to form a fine circuit and a small-diameter via, and it is easy and highly reliable because the printed wiring board has a small-diameter via, a high-density by miniaturization of the wiring circuit by fine wiring, and a small size. A multilayer printed wiring board can be provided.

An example of the multilayer printed wiring board of the present invention is shown in FIG.
The multilayer printed wiring board of the present invention has at least one inner layer circuit, and on the inner layer circuit, a via 151 connected to the upper layer and an via receiving land 111 electrically connected at the via end of the lower layer, The wiring circuit 154 is provided. When the via receiving land has a thickness Tv, the wiring circuit has a thickness Tl, and the thickness of the interlayer insulating resin laminated on the interior circuit is Tr, the present invention has an inner layer circuit that satisfies the relationship Tr>Tv> Tl. It is characterized by. Although FIG. 1A has been described with an example of a multilayer printed wiring board having two inner layer circuits, the present invention can be applied to any inner layer circuit by repeating such an inner layer circuit configuration. Can do.

FIG. 1B is an explanatory diagram of a multilayer printed wiring board according to the present invention in which the periphery of the via 151 and the via receiving land 111 is partially extracted and enlarged. In one embodiment of the present invention, the via receiving land includes a first layer 111a having a thickness substantially the same as that of the wiring circuit, and a second layer 11b on the first layer. For example, as shown in an example of a method for manufacturing a multilayer printed wiring board of the present invention described later, if the wiring circuit and the first layer of the via receiving land are formed in the same process, they have substantially the same thickness. Then it can be considered. Further, by using the metal plating layer as the second layer, the thickness of the via receiving land can be easily controlled, and a multilayer printed wiring board having a desired via receiving land thickness can be obtained.

An example of a method for producing a multilayer printed wiring board according to the present invention will be described based on the steps shown in FIGS. The present invention can also be applied to a multilayer printed wiring board of conformal via plating and is within the scope of the present invention. Here, interlayer conduction by filled via plating will be described as an example. First, a core substrate is prepared, and the core substrate is created using a known method. An example of a method for creating a core substrate is shown, but the method of the present invention is not limited to the method described, and other methods may be used. First, a copper-clad double-sided board or an inner layer circuit is formed, and a through-hole is formed by drilling a copper-clad laminate in which copper foil is laminated on the entire surface of both substrates. The inside of the through hole is desmeared with an alkaline permanganate solution, and a chemical copper plating catalyst such as palladium is applied to the inner wall of the through hole and the substrate surface. Interlayer conduction between the front and back layers of the substrate is performed by panel plating using chemical copper plating and electrolytic copper plating. Further, depending on the case, a filling resin may be printed in the through-hole hole and the lid plating may be performed. Further, physical polishing or chemical polishing is performed to form an alkali-soluble etching resist. A photomask on which a desired wiring pattern is drawn is used to perform front-and-back alignment exposure and development processing to form a resist pattern, and then etching processing is performed to remove the resist, and via receiving lands 111 ( A core substrate having the first layer 111a), the wiring circuit 112, and the interlayer conduction through-hole 113 is formed (FIG. 2A). Thereafter, the method of the present invention to be described later is applied to the via receiving land portion 111 on the core substrate, and only the via receiving land portion 111 is selectively formed to be higher than the other circuit height (FIG. 2 (A-2)). . Or it is in the category of this invention even if it implements from the upper buildup layer, without implementing the method by this invention to a core board | substrate.

Next, as shown in FIG. 1B, an interlayer insulating resin 121 is formed on the core substrate by thermocompression, and a thermosetting process is performed. The resin to be laminated may be a commercially available build-up resin that does not contain glass cloth, or may be prepared by simultaneously laminating a prepreg containing glass cloth and copper foil, and can be formed by any known method. is there. When the prepreg and the copper foil are laminated, the copper foil may be etched out to leave only the resin layer, or the copper foil may be thinned to about 0.3 to 3 μm and used as a semi-additive seed layer. Following formation of the interlayer insulating resin on the core substrate, a blind via hole 122 is formed on the via receiving land formed on the core substrate surface by UV or carbon dioxide gas racer, and a chemical copper plating layer formed on the desmear and the resin Is applied to the interlayer insulating resin portion on the substrate surface and the side surface of the via hole.

Although it is a via diameter, according to the present invention, the thickness of the interlayer insulating resin is reduced only in the portion where the via is formed as compared with the other portions, so that the via aspect can be reduced. Therefore, it is possible to easily reduce the diameter of via processing. According to the present invention, the via processing diameter is desirably 5 μm or more and 200 μm or less. If it is 5 μm or less, via filling is not impossible, but there is a possibility that a sufficient ground contact area with the lower via receiving land cannot be secured. When the thickness is 200 μm or more, the sufficient effect of reducing the diameter according to the present invention cannot be obtained. More preferably, it is 10 μm or more and 150 μm or less. More preferably, it is 20 μm or more and 100 μm or less. Subsequently, as shown in FIG. 2C, a chemical copper plating catalyst is applied, and a chemical copper plating layer 131 is formed on the inner wall of the via hole and the interlayer insulating resin.

Subsequently, as shown in FIG. 2 (D), a dry film resist is thermally laminated on the substrate surface, a first resist layer is provided, and a desired wiring pattern is exposed and developed to thereby reverse the resist pattern to the wiring pattern. 141 is formed. Although it is the thickness of the 1st dry film resist used by this invention, it becomes possible to use a thing thinner than what was used conventionally as above-mentioned. In the conventional method, if the wiring pitch is 40 μm, it is necessary to use a dry film resist having a thickness of about 30 μm. However, in the present invention, even a pitch of 25 μm or less can be handled with the same pitch. When the wiring has a pitch of 40 μm or less, it is more preferable that the wiring is 20 μm or less and 5 μm or more. If it is 5 μm or less, the height of the wiring circuit to be formed is 5 μm or less, so that the cross-sectional area of the wiring is reduced and the electrical reliability of the conductor circuit becomes insufficient. When the thickness is larger than 25 μm, the effect of increasing the wiring density by reducing the resist thickness according to the present invention cannot be obtained. More preferably, it is 20 μm or less and 10 μm or more.

Next, as shown in FIG. 2E, wiring formation by electrolytic copper plating and filled via plating are performed at once to form a via 151, a land 152 immediately above the via 151, a via receiving land 153, and a wiring circuit 154. The electrolytic copper plating conditions according to the present invention are within 95% to 30% of the resist pattern thickness in which the electrolytic plating thickness of the via receiving land portion for interlayer connection with the wiring circuit portion or the upper layer formed on the substrate flat portion is formed. It is desirable that If it is 95% or more, the plating thickness variation in the substrate results in overplating in which the plating is deposited thicker than the flat portion on the resist, and the resist cannot be stripped in a subsequent stripping step. When it is 50% or less, a sufficient wiring cross-sectional area cannot be obtained, and the electrical reliability of the conductor circuit becomes insufficient. More preferably, it is 90% or less and 60% or more of the resist thickness. As the electrolytic plating bath of the present invention, a known filled via bath can be used. In some cases, it is within the scope of the present invention to use a filled bath and other plating baths in combination. When the via receiving land portion of the conductor circuit on the core substrate is not less than the wiring circuit height and the laminated resin thickness according to the present invention, the via fill is accelerated by reducing the aspect of the via, and the via fill and immediately above it. The formation of the via land and the formation of the wiring circuit portion formed on the surface of the insulating resin and the via receiving pad portion are finished to the same thickness. At this point, the substrate is taken out of the plating bath, washed with water and dried.

A second alkali-soluble photosensitive plating resist layer is formed on the entire upper substrate that has been washed and dried after pattern plating. The plating resist can be selected from a negative liquid resist, a positive liquid resist, and a dry film resist. If it is a liquid resist, a resist layer can be formed on the entire surface of the substrate by any one of curtain coating, slit coating, screen printing, die coating, spray coating, and electrostatic coating. If it is a dry film resist, it can be formed by a laminating method. The liquid resist can be applied by spin coating, but the circuit pattern is uneven on the substrate, the liquid resist stays in the concave portion, and further flows out into the spin coat sequentially by the centrifugal force of rotation. This is not preferable because radial film thickness unevenness occurs starting from the portion.

Furthermore, although not applied to the entire upper substrate, a resist film may be formed only on the electrolytic copper plating portion by using an electrodeposition resist as a second plating resist formation method. When an electrodeposition resist is used as the second resist according to the present invention, the second resist film is formed only on the electrically conductive wiring pattern portion. Examples of the electrodeposition resist used here include a positive electrodeposition resist and a negative electrodeposition resist. More preferably, it is an anion electrodeposition resist having high resistance to acidic plating solution.

The thickness of the second resist to be formed is desirably 5 μm or more and 50 μm or less. After the application of the second resist, the via receiving land portion is selectively exposed by exposure and development, and the copper thickness of the via receiving land portion is increased again by electrolytic plating. When the thickness is 5 μm or less, the via according to the present invention is used. Not only is it impossible to increase the thickness of the insulating resin to the thickness of the insulating resin on which the receiving lands are laminated, but the number of overplating portions increases due to variations in plating thickness. If the thickness is 50 μm or more, the resist thickness is too thick and the via receiving land portion may not be clearly resolved. More preferably, it is 10 μm or more and 40 μm or less.

A via receiving land portion for performing interlayer conduction with the upper layer is exposed and developed using a mask pattern for the substrate on which the second plating resist layer is formed, and as shown in FIG. The copper surface of the via receiving land portion 161 is exposed. Further, a via receiving land portion having a copper height higher than that of the wiring layer is formed by electrolytic plating. The plating solution at this time may be a filled via plating solution, or other electrolytic copper plating baths may be used, or in some cases, dissimilar metal plating may be performed. Finally, the resist is peeled off, and the chemical copper plating layer is dissolved and removed by flash etching, so that the inner wiring layer in which the via receiving land portion 111 according to the present invention shown in FIG. Form. The copper circuit surface is subjected to a roughening process such as a CZ process to improve the adhesion of the interlayer insulating resin formed on the upper layer. The multilayer printed wiring board of the present invention is created by repeating the above inner layer wiring circuit creation step a plurality of times. Since the outermost layer portion of the multilayer printed wiring board of the present invention does not require lamination, there is no need to form via receiving lands having a wiring height or more and a laminated resin thickness of the method of the present invention or less. Furthermore, when a buildup layer is formed on the core substrate, the present invention may be carried out on a via receiving land portion on a circuit on the outermost layer of the core substrate. That is, the second resist pattern is formed on the surface of the core substrate on which the conductor circuit is formed by the above method, and pattern plating is performed to make the via receiving land portion thicker than the thickness of the other wiring circuit layer.

In the above description, the increase in the thickness of the via receiving land portion by plating is described as an example. However, the present invention is not limited to this, and the multilayer printed wiring board according to the present invention has a via receiving land portion thicker than the wiring circuit portion and is laminated. Any means can be used as long as it achieves the thickness of the interlayer insulating resin or less. Otherwise, the via receiving land portion may be thickened by forming a conductive metal paste by a screen printing method, and further, the conductive metal paste is applied on the via receiving land using a dispenser or an ink jet method. Thus, a multilayer printed wiring board according to the present invention may be prepared. Furthermore, other conceivable methods may be used. As described above, the present invention can be applied to a multilayer printed wiring board having a conformal via structure and falls within the scope of the present invention.

Hereinafter, a part of the present invention will be described with reference to FIG. 2 and FIG.

<Example 1>
・ How to create a core substrate
610 × 510mm square glass-epoxy insulating substrate MCL-E-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) is prepared by providing a conductor wiring pattern and through holes for conduction on both sides on both sides by a known method. (FIG. 2 (A)). A liquid negative resist PMER N-HC40PY (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied to the entire surface by slit coating on the core substrate, followed by pre-baking to form a resist layer 30 μm thick from the core substrate resin surface (the resist thickness on the via receiving pad upper surface is 15 μm). ). Next, after exposing the via receiving land portion with ultraviolet light using a light-shielded glass mask, the via receiving land portion is selectively opened by developing with a dedicated developer (PMER N-A5, manufactured by Tokyo Ohka Kogyo Co., Ltd.). Then, electrolytic copper plating was applied to the resist non-formed portion in a high-throw bath under the following conditions to form an electrolytic copper plating film having a thickness of 10 μm.
(Electrolytic plating aqueous solution)
Sulfuric acid 180g / L
Copper sulfate 80g / L
Additive (Kaparaside GL, manufactured by Atotech Japan) 1mL / L
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 40 minutes Temperature After the room temperature plating, the resist was peeled off to produce a core substrate having a wiring height Tl = 15 μm and a via receiving land portion height Tv = 25 μm (FIG. 2 (A-2)).

-Creation of build-up inner layer circuit Subsequently, interlayer insulation resin ABF-GX code 13 (trade name, manufactured by Ajinomoto Fine Techno Co., Ltd.) having a thickness of Tr = 35 µm. Was laminated at 110 ° C. and 0.7 MPa, further pressed at 110 ° C. and 6 kgf / cm 2 for 60 seconds and fluttered, and then cured at 180 ° C. for 30 minutes to form an interlayer insulating resin layer on both sides. . A predetermined via pattern alignment was aligned with this insulating resin layer, and a via hole of φ60 μm was formed with a UV laser. Further swelling treatment was performed, and desmearing / roughening treatment was performed with a 70 ° C. solution of potassium permanganate 60 g / L and sodium hydroxide 40 g / L until there was no processing residue at the bottom of the via. The via part thus formed had a depth of 15 μmt, an opening width of φ65 μm, an opening width of the via bottom of φ50 μm, and a good desmear property.

Next, as a pretreatment for electroless copper plating, the substrate is immersed in a pre-dip liquid PD-301 (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a concentration of 250 g / L, and then a sensitizer HS-202B (Hitachi). Immersion treatment is performed on Kasei Kogyo Co., Ltd., trade name), and then immersion treatment is performed on adhesion promoter ADP-601 (trade name, manufactured by Hitachi Chemical Co., Ltd.), and then CUST-201 (Hitachi Chemical Industry Co., Ltd.). The product was subjected to electroless copper plating for 20 minutes to form a 0.8 μm thick conductor wiring seed layer (FIG. 2C).

Next, a photosensitive dry film resist UFG-115 (manufactured by Asahi Kasei Electronics Co., Ltd.) having a thickness of 15 μm is bonded onto the conductor wiring seed layer, and a photomask having a desired outer layer wiring pattern is placed thereon, and 80 mJ / cm ^2. And developed with a 0.8% sodium carbonate solution at 30 ° C. to provide a plating resist having a wiring pattern of 20 μm pitch and line / space = 13/7 μm design (FIG. 2D).

Next, electrolytic copper plating was performed on the non-resist forming portion with the following filled via plating bath to form an electrolytic copper plating film with a wiring portion having a thickness of 12 μm (FIG. 2E).
(Electrolytic plating aqueous solution)
Sulfuric acid 50g / L
Copper sulfate pentahydrate 200g / L
Additive Cu Bright VF2 A 20 ml / L made by Ebara Eugelite
Cu Bright VF2 B Ebara Eugelite 1mL / L
Chloride ion concentration 50mg / L
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 40 minutes Temperature Room temperature

Next, the plating resist was peeled off at 50 ° C. with a 5% NaOH aqueous solution. The via filling rate of the substrate thus prepared (= copper thickness at the center of the via / copper thickness from the bottom of the via to the periphery of the via land = 98%. Overplating in which the wiring plating copper height is higher than the dry film resist thickness) There were no spots, and the plating thickness uniformity was also good.

Subsequently, a second liquid negative resist PMER N-HC40PY (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied to the entire surface by slit coating on the upper substrate from which the dry film resist was peeled off, and then pre-baked to form a resist layer 30 μm from the core substrate resin surface. Thickness (via receiving pad upper surface resist thickness is 18 μm). Next, after exposing the via receiving land portion with ultraviolet light using a light-shielded glass mask, the via receiving land portion is selectively opened by developing with a dedicated developer (PMER N-A5, manufactured by Tokyo Ohka Kogyo Co., Ltd.). (FIG. 2 (F)) was subjected to electrolytic copper plating in the previous high throw bath to form an electrolytic copper plating film having a thickness of 10 μm. After removing the resist, flash wiring was performed with CPE 810 (Mitsubishi Gas Chemical) to dissolve the chemical copper plating film, thereby forming a wiring circuit (FIG. 2G). The 20 μm pitch wiring height created in this way is uniformly formed within Tl = 11 ± 1.6 μm within the 610 × 510 square substrate surface, and the inner layer circuit with via receiving land height Tv = 21 μm has a good circuit shape. I was able to create it.

・ Creation of built-up outermost layer Further, build-up resin is formed on both sides of the substrate by the same method as above, with interlayer insulation resin thickness Tr = 35 μm, and from via formation and catalyst application in FIG. 2 (B) to FIG. 2 (E) The process up to the described pattern plating process was performed by the same method. The via filling rate after pattern plating was as good as 99%. Further, after the dry film resist was peeled off, flash etching was performed to form a conductor circuit on the outermost layer of the substrate (FIG. 3 (H)). The height of the conductor layer thus prepared could be uniformly formed within 11 ± 1.5 μm within the 610 × 510 square substrate surface.

Subsequently, a photosensitive solder resist layer is applied on both sides of the outermost layer of the substrate so as to have a thickness of 30 μm, followed by patterning so as to expose the flip chip pads and the solder bonding pads, thereby forming a solder resist pattern to form a build-up wiring layer -Core wiring layer-Build-up wiring layer = A 2-2-2 layer density multilayer printed wiring board was prepared (Fig. 3 (I)). Thermal shock test at n = 10 (−40 ° C. to 125 ° C., 1000 cycles) using a semiconductor device in which a TEG chip is mounted on the prepared substrate and the multilayer printed wiring board according to the present invention after mounting the chip is mounted on the motherboard. However, there was no disconnection and all were good results.

<Example 2>
Example 2 was performed in the same manner as in Example 1 except that the via processing diameter of the build-up resin was changed from φ60 μm to φ30 μm. The finished via after the desmear roughening had a via depth of 15 μmt, an opening width of φ35 μm, and a via bottom opening width of φ25 μm, and the desmear property of the via bottom was also good. Similarly, the build-up inner layer wiring was able to be formed with a 20 μm pitch and wiring pattern without overplating portions. The via filling rate at this time was as good as 99%. The second resist of the present invention is provided, and after the electrolytic plating is performed again on the via receiving land portion, the resist is peeled off and flash etching is performed, whereby the wiring height Tl = 11 ± 1.7 μm, the line and space 10/10 μm, An inner layer circuit having a via receiving land height Tv = 21 μm could be formed with a good circuit shape.

Further, it was prepared by the same method as described in Example 1, and the conductor circuit of the outermost layer of the substrate could be uniformly formed within a conductor layer height of 11 ± 1.5 μm. Subsequently, a solder resist pattern was provided on the outermost layer of the substrate, and a 2-2-2 layer density build-up multilayer printed wiring board in which a flip chip pad and a solder bonding pad were exposed was prepared. Thermal shock test at n = 10 (−40 ° C. to 125 ° C., 1000 cycles) using a semiconductor device in which a TEG chip is mounted on the prepared substrate and the multilayer printed wiring board according to the present invention after mounting the chip is mounted on the motherboard. However, there was no disconnection in all the substrates, and good results were obtained.

<Comparative Example 1>
Comparative Example 1 was performed in the same manner as in Example 1 except that selective pattern plating was not performed on the via receiving land portion according to the present invention on the core substrate and the inner layer circuit. A build-up layer was formed by the same method as in Example 1, and a via hole with a diameter of 60 μm was formed as in Example 1. As a result of performing the desmear process until the residue on the bottom surface of the via was removed and partitioned, the depth of the via portion was 28 μmt, the opening width was φ75 μm, and the opening width of the via bottom was φ55 μm. Thereafter, a dry film resist of 15 μmt was laminated by the same method to form a resist pattern, and then pattern plating was performed. Overplating spots where the wiring plating copper height was higher than the dry film resist thickness occurred everywhere in the 610 × 510 square substrate surface, and were particularly prominent at the outer periphery of the substrate. The wiring height at this time was 12 ± 5.0 μm. Wiring could not be formed due to frequent occurrence of overplating locations, and it was impossible to make more substrates. The via filling rate at this time was 83%.

<Comparative Example 2>
This Comparative Example 2 was carried out in the same manner as Example 1 and Comparative Example 2 except that a dry film resist having a thickness of 25 μm was used. The finished via after desmearing had a depth of 28 μmt, an opening width of φ76 μm, and an opening width of the via bottom of φ55 μm. A resist pattern having the same pitch was formed on a dry film resist having a thickness of 25 μm, but there were peeling of the resist pattern and defective resolution portions everywhere in the 610 × 510 square substrate surface. Pattern plating was performed in the same manner as in Example 1 and Comparative Example 2. Although the occurrence of overplating spots where the wiring plating copper height is higher than the dry film resist thickness has disappeared, there are also places where the resist peels off during electrolytic plating, and it is impossible to manufacture with practical yield, and more substrates Creation was impossible. The via filling rate at this time was 82%.

<Comparative Example 3>
This Comparative Example 3 was performed in the same manner as in Example 2 except that it was prepared by a known method in which selective pattern plating was not performed on the via receiving land portion according to the present invention on the core substrate and the inner layer circuit. After forming the build-up resin, a via hole having a diameter of 30 μm was formed in the same manner as in Example 2. As a result of the desmear treatment until the residue on the bottom surface of the via is removed and divided, the depth of the via portion is 28 μm, the opening width is φ50 μm, and the opening width of the via bottom is φ40 μm. As a result. Subsequently, chemical copper plating was performed by the same method, a 15 μmt dry film resist was laminated, a resist pattern having the same pitch was formed, and then pattern plating was performed by the same method. Overplating spots where the wiring plating copper height was higher than the dry film resist thickness occurred everywhere in the 610 × 510 square substrate surface, and were particularly prominent at the outer periphery of the substrate. The wiring height at this time was 12 ± 7.0 μm. Wiring could not be formed due to frequent occurrence of overplating locations, and it was impossible to make more substrates. The via filling rate at this time was 78%.

<Comparative example 4>
This Comparative Example 4 was carried out in the same manner as Example 2 and Comparative Example 3 except that a dry film resist having a thickness of 25 μm was used. The finished via after desmearing had a depth of 28 μm, an opening width of φ52 μm, and an opening width of φ41 μm at the bottom of the via. A resist pattern having the same pitch was formed on a dry film resist having a thickness of 25 μm, but there were peeling of the resist pattern and defective resolution portions everywhere in the 610 × 510 square substrate surface. Pattern plating was performed in the same manner as in Example 1 and Comparative Example 2. Although the occurrence of overplating spots where the wiring plating copper height is higher than the dry film resist thickness has disappeared, there are also places where the resist peels off during electrolytic plating, and it is impossible to manufacture with practical yield, and more substrates Creation was impossible. The via filling rate at this time was 76%.

Table 1 shows the sum of the thicknesses (Tv, Tl, Tr) of the via receiving lands, the wiring circuits, and the interlayer insulating resin layers of the core layer and the buildup layer in the examples and comparative examples of the present invention.

Table 2 summarizes the results shown in Examples and Comparative Examples of the present invention.

As shown in the above Examples and Comparative Examples, the high-density multilayer printed wiring board according to the present invention can provide a multilayer printed wiring board with reduced via diameter, finer wiring, and high reliability.

According to the present invention, it is possible to easily realize miniaturization of wiring and reduction of via diameter, and to provide a multilayer printed wiring board capable of ensuring high electrical reliability. It contributes to.

Explanatory drawing of the multilayer printed wiring board of this invention Examples of implementation of each process in the present invention Examples of implementation of each process in the present invention

Explanation of symbols

111 Via receiving land 111a Via receiving land (first layer)
111b via receiving land (second layer)
112 wiring circuit 113 interlayer connection through hole 121 interlayer insulating resin 122 via hole 123 roughening treatment 131 chemical copper plating layer 141 dry film resist pattern 151 filled via 152 via land 153 via receiving land 154 wiring circuit 161 via receiving land 181 outermost layer conductor circuit ( Flip chip or ball pad)
191 Solder resist layer 192 Solder resist opening

Claims (4)

In a multilayer printed wiring board having an inner layer circuit, a via receiving land for a via connected to an upper layer and a wiring circuit are provided on at least one inner layer circuit, and the thickness of the via receiving land is Tv. A multilayer printed wiring board having an inner layer circuit satisfying Tr> Tv> Tl, where T1 is the thickness of the circuit and Tr is the thickness of the interlayer insulating resin laminated on the internal circuit.   The multilayer printed wiring board according to claim 1, wherein the via receiving land includes a first layer having a thickness substantially the same as that of the wiring circuit and a second layer on the first layer.   The multilayer printed wiring board according to claim 2, wherein the second layer is a metal plating layer. A method of manufacturing a multilayer printed wiring board in which via receiving lands for vias connected to an upper layer and a wiring circuit are provided on at least one inner layer circuit, and the inner layer circuit manufacturing process is performed on an insulating resin. Forming a wiring circuit and a via receiving land first layer and a step of selectively forming a via receiving land second layer on the via receiving land first layer by electrolytic plating. Manufacturing method of printed wiring board.

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