JP2001053444A - Method of forming conductor-filled via and method of manufacturing multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a metal layer inside a relatively large via hole without increasing the thickness of a wiring layer and to provide a wiring layer having a flattened surface, and to have excellent reliability and durability. Manufacture multilayer wiring boards. SOLUTION: An insulating layer 3 is provided on a base wiring layer 2 on a substrate 1.
After forming an electroless copper plating film 4 on the upper surface of the insulating layer, an insulating protective coating 5 is formed thereon. Next, a via hole 6 is formed, an electroless copper plating film 7 is selectively formed on the insulating layer on the side wall of the via hole, and the via hole is filled with copper metal 8 by a first electrolytic copper plating. Thereafter, the insulating protective coating 5 is removed, and thereafter the plating resist pattern 9 is formed in the same manner as in the semi-additive method.
Is used to form the wiring pattern 10 by electrolytic copper plating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a conductor-filled via penetrating an insulating layer in a laminated structure having an insulating layer interposed between upper and lower conductor layers. INDUSTRIAL APPLICABILITY The method of the present invention is broadly related to an electronic component manufacturing technique, and can be used particularly for forming fine copper wiring such as a package for housing a semiconductor element and a multilayer wiring board. The present invention also relates to a method for manufacturing a multilayer wiring board using the above method.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for miniaturization and high integration of electronic devices such as computers, and plastic packages used for housing and connecting multilayer wiring boards and semiconductor elements constituting these devices have been strongly demanded. Is
There is a demand for improved reliability along with finer wiring and higher integration.

In order to meet such a demand, a method of manufacturing a multilayer wiring board called a build-up method in which a conductor layer and an insulating layer are sequentially stacked to form a multilayer has been frequently used. In the manufacture of a multilayer wiring board having a relatively high degree of integration by a build-up method, a wiring pattern is generally formed on a conductor layer by a method called a semi-additive method.

In the semi-additive method, an insulating resin layer is formed on a substrate provided with a base wiring layer, and via holes penetrating the insulating resin layer are formed by, for example, laser processing. Thereafter, after performing a roughening treatment on the resin surface, electroless copper plating is performed to form a thin copper plating film.
This plating film covers not only the surface of the insulating resin layer but also the side wall of the via hole. After that, a pattern for wiring formation is formed on the electroless copper plating film with a plating resist, and then the electroless copper plating film is used as a power supply layer, and electrolytic copper plating is applied to a required thickness on the wiring layer. Copper is deposited on the parts not covered with.

[0005] By the electrolytic copper plating, a predetermined wiring pattern is formed, and at the same time, copper is deposited inside the via hole, and the via hole is filled with copper to form a vertical conductive path connecting the upper and lower wiring layers. Vias (via holes filled with conductors) are formed. Thereafter, the plating resist is peeled off, and quick etching is performed to remove a thin electroless copper plating film remaining on the portion covered with the plating resist, thereby obtaining a desired wiring pattern.

In this method, the metal is deposited in the via hole at the same time as the wiring portion by a single electrolytic plating, and the formation of the wiring pattern and the filling of the via hole are achieved at the same time. Has been widely put into practical use.

[0007]

As described above, in the multilayer wiring board, there has been a strong demand for high integration and improved durability and reliability. In order to achieve high integration of a multilayer wiring board, it is effective to reduce the diameter of the via and at the same time, to form the via vertically so as to reduce the area of the wiring layer.

However, when a wiring pattern is formed by the above-described semi-additive method, as shown in FIG. 2, a relatively deep dent is formed on the upper surface of a via formed by metal deposition into a via hole by electrolytic plating. As described above, since the metal wiring layer (electrolytic copper plating layer 11) is not flattened, it is not easy to form the via directly above the via, and even if it is formed, the connection reliability is lowered.

This is because the latter is overwhelmingly larger in the amount of metal required for forming the wiring and the amount of metal required for filling the via hole with metal. That is, when the electroplating is completed at the stage when the wiring having the required thickness is formed, the filling of the metal in the via hole is not completed yet. As a result, a considerably deep concave space as shown in FIG. 2 remains in the via hole.

[0010] As a countermeasure, after the space remaining in the via hole is filled with a resin or a metal paste, or electrolytic plating is performed until the via hole is completely filled with metal, copper excessively precipitated in the wiring portion is removed. Various techniques have been proposed, such as removal by polishing or the like to reduce the thickness of the wiring portion. However, in each case, the complexity of the process is inevitable.

As another countermeasure, means such as a further reduction in the diameter of the via hole (miniaturization, for example, a diameter of 20 μm or less) and an increase in the thickness of the wiring layer are easily conceived. There are difficulties, and practical application is difficult.

Regarding miniaturization of via holes, it is not easy to stably form such micro via holes even by using laser processing, and moreover, uniform electrolytic plating is stably formed inside the micro via holes. It is also difficult to implement. Therefore, in order to ensure sufficient connection reliability, the via hole needs to have a certain size.

On the other hand, increasing the thickness of the wiring layer necessarily entails increasing the thickness of the insulating layer. This is because the wiring layer is patterned and an insulating layer is formed between the wiring patterns. In a plastic package, the thickness of the insulating layer is limited because the component that hinders transmission of a high-speed signal increases as the thickness of the insulating layer increases. Therefore, the wiring layer cannot be excessively thickened.

As described above, in order to improve the durability and reliability simultaneously with the high integration of the multilayer wiring board, the metal is sufficiently deposited in the via hole having a relatively large diameter within a range that can be stably formed by laser processing. Despite the strong demand for a simple method of forming a relatively thin wiring layer by achieving improved connection reliability and flattening of the wiring layer, there has been no effective method to achieve these. Was.

An object of the present invention is to provide a semiconductor device without increasing the thickness of a wiring layer.
A method for forming a conductor-filled via capable of completely filling a relatively large via hole with a metal, and a wiring layer having a relatively thin wiring layer thickness and a flat surface using the method for forming a conductor-filled via. And a method for manufacturing a multilayer wiring board capable of forming the same.

[0016]

According to the present invention, the above object is attained by separating an electrolytic plating step for depositing a metal inside a via and an electrolytic plating step for forming a wiring. That is, first, electrolytic plating only for filling the via hole portion is performed, and second, electrolytic plating for forming the entire wiring layer including the via hole portion is performed. As a result, it is possible to provide an appropriate amount of electrolytic plating deposition in each plating step, and completely fill the inside of a relatively large via hole with a metal, and at the same time, reduce the wiring layer thickness with a relatively thin wiring layer thickness. It is possible to form a uniform wiring layer having a flat surface.

For this purpose, first, after forming an insulating layer on the underlying wiring layer, electroless plating is performed to form an electroless plating film on the upper surface of the insulating layer. Thereby, a laminated body including a laminated structure in which the insulating layer is interposed between the upper and lower conductor layers is obtained. An insulating protective coating is formed on the electroless plating film. Thereafter, a via hole is formed through the protective coating, the electroless plating film, and the insulating layer to reach the underlying wiring layer by using a mechanical processing method such as laser processing.

Next, electroless plating is selectively performed on the insulating layer exposed on the side wall of the via hole. After that, the first electrolytic plating is performed using the electroless plating layer as a power supply layer. In the first electrolytic plating, since the wiring layer is covered with the protective film, the metal is deposited only in the exposed via holes. Therefore, it is possible to perform electrolytic plating until the amount of precipitation required for filling the metal in the via hole is obtained. Thus, a conductor-filled via is formed in the laminate.

Thereafter, the insulating protective coating is removed, and a wiring pattern is formed by an appropriate technique using the exposed electroless plating film. This can be achieved by selectively performing the second electrolytic plating only on the wiring portion using a plating resist, similarly to the usual semi-additive method. Since the filling of the via hole portion with the metal has already been completed, the second electrolytic plating can be completed when the required amount of deposition as the thickness of the wiring layer is obtained.

According to the present invention, there is provided a method for forming a conductor-filled via penetrating through an insulating layer in a laminate having a laminated structure in which an insulating layer is interposed between upper and lower conductor layers, the method comprising the following steps: There is provided a method of forming a conductor-filled via, characterized by: (A) forming an insulative protective coating over the upper conductor layer;
(B) a step of forming a via hole that penetrates the insulating protective coating and the upper conductor layer and the insulating layer below the insulating protective coating, and (C) selectively forms a conductor plating film on the insulating layer exposed on the side wall of the via hole. And (D) filling the via hole with a conductor by performing electrolytic plating.

According to the present invention, there is also provided a method for producing a multilayer wiring board, comprising the steps of: Removing; and (F) forming a wiring pattern on the upper conductor layer.

More specifically, the present invention provides a method for manufacturing a multilayer wiring board, comprising the following steps: (a) forming an insulating layer on an underlying wiring layer; b) a step of forming a conductor plating film on the upper surface of the insulating layer by electroless plating, (c) a step of forming an insulating protective coating covering the electroless plating film, and (d) a step of forming the insulating protective coating and under the same. Forming a via hole penetrating through the electroless plating film and the insulating layer on the side, (e) forming a conductor plating film by electroless plating selectively on the insulating layer exposed on the side wall of the via hole, (f) A step of filling the via hole with a conductor by performing electrolytic plating, (g) removing the insulating protective coating, and exposing an electroless plating film thereunder,
(h) a step of forming a plating resist pattern on the exposed electroless plating film, (i) a step of forming a conductor layer patterned by electrolytic plating, (j) a step of removing the plating resist pattern, (k) A step of removing the exposed electroless plating film by etching.

In the present invention, the relationship between “lower” and “upper” is that “lower” is closer to the substrate than “upper”, or that the “lower” layer is formed before the “upper” layer. Means
As will be described later, wiring layers can be formed on both surfaces of the substrate. In such a case, on both surfaces, the layer closer to the substrate is the lower layer and the layer farther from the substrate is the upper layer.

[0024]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Although the drawing shows only one side of the substrate (the top surface of the substrate at the position shown) for simplicity, it goes without saying that both sides of the substrate can be processed simultaneously. In addition, since copper is generally used as a conductor in multilayer wiring boards,
In the following description, the case where the conductor is copper will be described, but the conductor metal is not limited to copper, and other metals or alloys (eg, silver, silver-palladium, gold, etc.) can be used.

FIG. 1 (a) shows that a base copper wiring layer 2, an insulating layer 3, an electroless copper plating film 4, and an insulating protective coating 5 are formed on a substrate 1 in this order from the bottom. This shows the formed state. In the figure, the underlying copper wiring layer 2 is formed directly on the substrate (for example, by patterning a copper foil of a copper-clad substrate by lithography).
The underlying wiring layer 2 is not limited to this form, and any wiring pattern already formed can be used as the underlying wiring layer. For example, when a third wiring layer is formed on a substrate, the third wiring layer serves as a base wiring layer, on which a fourth wiring layer is formed according to the present invention. Become.

The laminated structure shown in FIG. 1A can be manufactured by a method well known to those skilled in the art. For example, a coating solution of an appropriate insulating resin is applied on the substrate on which the underlying copper wiring layer 2 is formed, and if necessary, heated or dried or baked to form the insulating layer 3 [Steps above]
(a)]. Up to this point, it is the same as the conventional semi-additive method.

The resin type of the substrate 1 and the insulating layer 3 is not particularly limited, and may be the same as the conventional one. The substrate may be a rigid type or a flexible type. Examples of the material of the insulating layer include polyimide, epoxy resin, and phenol resin. The thickness of the insulating layer is preferably about 30 to 60 μm.

In the conventional semi-additive method, a via hole is formed next, and then the side wall portion of the via hole is formed.
Electroless copper plating is applied to the entire surface of the insulating layer 3. In the present invention, before forming a via hole, electroless copper plating is performed on the surface of the insulating layer to form an electroless copper plating film 4 covering the flat upper surface of the insulating layer 3 [the above step (b)]. Thus,
A laminate having a laminated structure in which the insulating layer 3 is interposed between the lower conductor layer (base wiring layer 2) and the upper conductor layer (electroless copper plating film 4) as defined in claim 1 is obtained.

The electroless copper plating film 4 can also be formed according to a conventional method. For example, first, the surface of the insulating layer is roughened by using a roughening treatment generally performed when electroless plating a resin. The surface roughening may be performed by any of a mechanical method such as sandblasting and a chemical method such as treatment with an etching solution containing an oxidizing agent such as permanganate.
More than one method may be combined.

Next, when an electroless copper plating treatment is performed, copper is deposited on the surface of the roughened insulating layer, and an electroless copper plating film is formed. This copper plating can be performed as instructed using a commercially available electroless copper plating solution. Usually, first, as a pretreatment, a treatment with a catalyst solution is performed, a catalyst nucleus such as Pd is applied to the roughened portion, and further a treatment with an activating solution. After that, when treated with an electroless copper plating solution containing a copper salt, a reducing agent, a complexing agent, and the like, copper is deposited on the roughened portion to which the catalyst has been applied. The thickness of the formed electroless copper plating film 4 may be the same as the conventional semi-additive method,
Usually, about 0.5 to 2.0 μm is sufficient.

On the electroless copper plating film 4, an insulating protective coating 5, which is a feature of the present invention, is formed so as to cover the plating film 4 [Step (A)]. This is claimed in claim 1
This method corresponds to the above step (A) of forming an insulating protective film covering the upper conductor layer in the above method. Thus, a laminate having the structure shown in FIG. 1A is obtained.

The material constituting the insulating protective coating 5 can ensure appropriate adhesion between the electroless copper plating film 4, has plating chemical resistance, and is relatively easy when unnecessary. There is no particular limitation as long as it is a removable insulating material, but it is usually a resin.

Examples of preferable materials for the protective coating 5 from the above viewpoints include polytetrafluoroethylene (PTFE), tetrafluoroethylene / hexafluoropropylene copolymer (FEP), and tetrafluoroethylene / perfluoroalkyl vinyl ether copolymer. Coalescence, polychlorotrifluoroethylene, polyvinylidene fluoride, polyvinyl fluoride,
Ethylene / tetrafluoroethylene copolymer, ethylene / chlorotrifluoroethylene copolymer, fluorine rubber, chloroprene rubber, nitrile rubber, styrene rubber, polystyrene, polyamide, polyvinyl acetal such as polyvinyl butyral, polycarbonate, hydroxypropyl Cellulose ethers such as methyl cellulose, acrylic resins such as polymethyl acrylate and polymethyl methacrylate, vinyl acetate, ethylene / vinyl acetate copolymer, ethylene / acrylic (methacrylic) copolymer,
Styrene / methyl methacrylate copolymer, acrylonitrile / styrene copolymer, acrylonitrile / butadiene / styrene copolymer and the like can be mentioned. In particular, if you want to improve chemical resistance, use polyether sulfone.
Engineering plastics such as (PES), polyparaphenylene ether, polyetheretherketone (PEEK), and polyetherimide may be used.

The resin material of the insulating protective coating 5 is the insulating layer 3
Is used, the reactivity of which is lower with respect to the surface roughening treatment liquid than the resin material constituting the above. This is because a portion of the insulating layer 3 is preferentially roughened in a later-described roughening process of the via hole side wall portion. Therefore, the insulating protective coating 5 may be formed from a material that is more stable than the insulating layer 3 with respect to an etchant that can roughen the surface of the material of the insulating layer 3.

For the insulating protective coating 5, a coating solution of an appropriate resin material is prepared, and this coating solution is subjected to electroless copper plating by an appropriate coating method such as a spin coating method, a roll coating method, a doctor blade method, and a dipping method. Apply on film 4,
If necessary, it can be formed by heating and drying or baking. Also, a dry film of an appropriate insulating resin material is stuck on the surface of the electroless copper plating film 4 by thermocompression bonding or an adhesive to form an insulating protective coating 5.
It is also possible to form

The thickness of the insulating protective coating 5 may be a thickness which functions as a barrier to electroless copper plating and electrolytic copper plating performed later. In order to easily supply various processing solutions such as a plating solution into the via holes to be formed next, it is preferable that the thickness of the insulating protective coating is not too large. Although the required thickness varies depending on the type of resin, the thickness of the insulating protective coating 5 is usually preferably about 5 to 30 μm.

Next, a via hole 6 penetrating the insulating protective coating 5, the electroless plating film 4 thereunder and the insulating layer 3 and reaching the underlying wiring layer 2 is formed [Step (d) above]. This corresponds to the step (B) of forming a via hole penetrating the insulating protective coating and the upper conductor layer and the insulating layer thereunder in the method of the first aspect. Thus, unlike the conventional semi-additive method, in the present invention, via holes are formed after electroless plating is first performed.

The via hole 6 is preferably formed by laser processing using an appropriate laser such as a carbon dioxide gas laser, which is generally employed for fine processing in a highly integrated multilayer wiring board. However, mechanical drilling can also be used in some cases. The diameter of the via hole is not particularly limited, but considering the ease of processing and the metal filling property in electrolytic plating, a bottom diameter in the range of 30 to 80 μm is appropriate. If the diameter of the via hole is excessively small, the above-described problem occurs. If the diameter is too large, the degree of integration of the multilayer wiring board decreases.

The formation of the via hole 6 removes the insulating protective coating 5 at the via hole portion, but the protective coating 5 still remains at other portions. In the formed via hole 6, the underlying wiring layer 2 is exposed on the bottom surface, and the side wall portions are covered with the protective coating 5, the electroless plating film 4, and the insulating layer 3 from above.
Is exposed.

Next, a portion of the insulating layer 3 exposed on the side wall of the via hole 6 is selectively subjected to electroless copper plating, and a copper plating film 7 is formed on this portion (the above step (e)). This corresponds to step (C) of the method of claim 1. Thus, the structure shown in FIG. 1B is obtained. As shown in this figure, the electroless copper plating film 7 formed at this time usually covers not only the side wall portion of the via hole but also the bottom portion.
That is, the underlying wiring layer 2 exposed at the lower portion of the via hole 6
(Lower conductor layer) is also covered with the electroless copper plating film 7.

Thus, the bottom and side surfaces of the via holes penetrating through the insulating layer 3 are covered with the electroless copper plating film 7,
This electroless copper plating film 7 is connected to the electroless copper plating film 4 formed on the surface of the insulating layer 3 first. as a result,
The via hole is the same as the state after electroless copper plating in the conventional semi-additive method. However, in the present invention, the point that the surface other than the via hole portion is covered with the insulating protective coating 5 is different from the conventional method. It is.

Although the insulating protective coating 5 is also exposed on the side wall of the via hole 6, the exposed protective coating 5 is not subjected to electroless copper plating, and only the exposed insulating layer 3 is removed. Selectively electroless copper plating. For this purpose, first, only the exposed portion of the insulating layer 3 is preferentially roughened. This can be achieved, for example, by a chemical roughening method using an etching solution containing an oxidizing agent such as permanganate.

As described above, if the insulating protective coating 5 is formed from a material having a lower reactivity to the roughening solution to be used than the insulating layer 3, the insulating layer 3 has a higher priority when treated with the roughening solution. Is roughened. The insulating protective coating 5 also
Although some elution and surface roughening are recognized by the roughening solution, the surface is not as rough as the insulating layer 3.

When the electroless copper plating is performed after the roughening treatment, as shown in FIG. 1B, the electroless copper plating film 7 is formed on the roughened insulating layer 3 and the bottom surface of the via hole side wall. The deposited side wall portion of the via hole 6 penetrating the insulating layer 3 is metallized. Insulating protective coating 5 that is hardly roughened
Since almost no catalyst nucleus such as Pd is imparted to the portion in the pretreatment of the electroless copper plating, the electroless copper plating film hardly precipitates. In addition, since the adhesion of the electroless copper plating film 7 is extremely low in this portion that has not been roughened, even slightly precipitated metal can be easily and completely removed by the subsequent washing with running water.

After the state shown in FIG. 1B is obtained,
The first electrolytic copper plating is performed using the electroless copper plating film as a power supply layer. As a result, copper is selectively deposited only in the via hole 6 where the conductor metal is exposed, and the inside of the via hole is filled with the conductor copper [the above step (f)]. This electrolytic plating step corresponds to the step (D) of claim 1. Thus, in a laminate including a laminate structure in which the insulating layer 3 is interposed between the upper and lower conductor layers (the underlying wiring layer 2 and the electroless copper plating film 4),
A conductor (copper) filling via penetrating the insulating layer 3 is formed.

The electrolytic copper plating may be carried out using any of the known electrolytic plating techniques such as copper sulfate plating and copper pyrophosphate plating. However, in order to ensure uniform deposition of copper in the via holes, It is desirable to have excellent uniform electrodeposition properties.

The purpose of the first electrolytic copper plating is to fill the inside of the via hole with a conductive metal to form a via having excellent connection reliability. Since copper does not deposit on the wiring layer portion covered with the insulating protective coating 5, this electrolytic copper plating must be continued without worrying about the thickness of the wiring layer until the inside of the via hole is completely filled with copper. Can be.

In the case of the conventional semi-additive method, since the wiring layer and the via hole are simultaneously filled by one electrolytic copper plating, when the electrolytic copper plating is performed so that the wiring layer has an appropriate thickness, as shown in FIG. Thus, the inside of the via hole cannot be completely filled with copper, and a considerably deep concave portion remains in the via hole portion. According to the present invention, electrolytic copper plating is performed only for the purpose of filling the via hole, so that copper can be deposited so that the via hole is just filled, as shown in FIG. 1 (c).

The amount of electrolytic copper plating deposited at this time affects the flatness of the wiring layer. To ensure the flatness of the wiring layer, the ratio of the minimum height (h) of the deposited copper (conductor metal) near the center of the via hole to the thickness (t) of the insulating layer is expressed by P
It is preferable to deposit copper so that (P = h / t) is 0.8 to 1.2. FIG. 2 shows the measurement site of the thickness (t) of the insulating layer and the minimum height (h) of copper near the center of the via hole. As shown in this figure, when the electroless copper plating film 7 formed on the side wall of the via hole also covers the bottom surface of the via hole, the minimum height (h) of copper includes the height of this electroless copper plating film 7. Height. The values of t and h can be easily measured by using an optical microscope or the like after cutting the wiring board after electrolytic plating and embedding and polishing the cross section in the via hole.

If P (= h / t), which is a parameter indicating the flatness of via hole filling, is smaller than 0.8, the height of the deposited metal inside the via hole is too small as compared with the thickness of the insulating layer. A rather deep recess remains. Therefore, planarization of the metal layer is not sufficiently achieved, and an upper via hole cannot be stably formed immediately above the via hole. On the other hand, if P is larger than 1.2, the via hole portion becomes too high, so that not only the flattening of the wiring layer is not achieved, but also extra time is required for electrolytic plating, and the productivity is deteriorated.

When manufacturing a multilayer wiring board, it is necessary to form a wiring layer next. For that purpose, after filling of the via hole by the first electrolytic copper plating is completed, the insulating protective coating 5 is removed, and the electroless copper plating film 4 covered with this coating is exposed. This is the above step (g) or (E)
It is.

The removal of the protective coating 5 may be performed by using a known appropriate method according to the material of the protective coating. For example, it can be dissolved and removed using a suitable organic solvent in which the protective coating is dissolved. When the protective coating 5 is a dry film, it may be able to be removed by peeling. Further, removal by etching, or mechanical removal by polishing, sandblasting or the like is also possible. With mechanical removal,
The upper surface of the via can also be planarized.

Thereafter, a wiring pattern is formed on the exposed electroless copper plating film 4 using the exposed electroless copper plating film 4
(F)]. In the case where the upper conductor layer is an electroless copper plating film, the thickness of the wiring layer is insufficient by using the conductor layer alone, as is well known, so that the thickness of the wiring layer is increased by electrolytic plating or the like. The wiring pattern is formed using a photosensitive plating resist in the same manner as the normal semi-additive method.
This can be performed as described below. However, the method of forming the wiring pattern is not limited to this.

First, a layer of a photosensitive plating resist 9 is formed on the exposed electroless copper plating film. The resist may be in any form of a coating solution or a dry film.
Next, a necessary wiring pattern is formed on the plating resist 9 through exposure and development treatments (the above step (h)). This state is shown in FIG.

Thereafter, a second electrolytic copper plating is performed using the electroless copper plating film 4 as a power supply layer, and copper is deposited on a portion where the copper plating film is exposed, thereby forming a patterned copper wiring layer 10. Form [Step (i) above]. The purpose of the second electrolytic copper plating is to form a wiring, and the electrolytic copper plating can be terminated when a wiring layer having a predetermined thickness is obtained by the deposition of copper. Preferred thickness of the wiring layer is 10 to
20 μm. Since the via hole is already filled,
It is not necessary to deposit metal to an excessive thickness for filling the via hole. FIG. 1D shows a state in which the second electrolytic copper plating is completed.

Thereafter, the plating resist is removed [Step (j) above]. This may be performed according to a conventional method such as stripping or dissolving and removing with a resist removing solution.
Finally, the electroless copper plating film exposed by removing the resist is dissolved and removed by so-called quick etching.
[Step (k) above). Thereby, a multilayer wiring board having via holes completely filled with the conductive metal and relatively thin wiring layers is obtained. When the first electrolytic copper plating is performed so that the parameter P falls within the range of 0.8 to 1.2, as shown in FIG. 1E, the wiring layer 10 having a highly planarized surface even in the via portion. Can be formed.

By repeating the above steps as necessary, a multilayer wiring board having a predetermined number of layers can be manufactured. Since the wiring layer 10 is flat also in the via portion, it is possible to form an upper layer via portion immediately above the via portion. As a result, there is no need to shift the via portion for each layer, and a highly integrated multilayer wiring board can be easily manufactured. In addition, since the via connection can be performed directly above, a sufficient size can be secured in the via portion even at a high degree of integration, and no void portion is generated. Therefore, the connection reliability and durability of the via are extremely high.

In the method of the present invention, as compared with the conventional semi-additive method, the formation and removal of the insulating protective coating, and the extra electroless copper plating and the electrolytic copper plating are added once each. This is a process frequently used in the production of a multilayer wiring board, and does not impose a great burden. On the other hand, there is no unnecessary deposition of copper, so that it is economical and troublesome steps such as removal of copper by polishing are not required. Therefore, in total, the method of the present invention can efficiently manufacture a highly reliable multilayer wiring board.

[0059]

EXAMPLES Hereinafter, the present invention will be described specifically with reference to Examples, but the present invention is not limited to these Examples.

(Example 1) A commercially available copper-clad laminate (epoxy, FR-4 grade) was used for the substrate, and the copper foils on both surfaces were coated with a photosensitive plating resist (THB, manufactured by JSR Corporation). Then, patterning was performed using an etching solution containing a ferric chloride aqueous solution as a main component to form a base wiring layer. An insulating layer and a wiring layer were formed on the underlying wiring layers on both sides according to the following procedure.

In order to form an insulating layer, a phenol novolak type epoxy resin (manufactured by Yuka Shell, trade name: Epicoat 154), an imidazole-based curing agent (manufactured by Shikoku Chemicals), and an epoxy resin fine powder (manufactured by Toray, trade name: Trepearl) EP-B) No.1
A varnish was prepared by adding the mixture at a weight ratio of 5: 1: 4 to a mixed solvent of dimethylformamide / butyl cellosolve. This varnish was applied on the substrate by a roll coating method, and then heated at 423 K for 10.8 kiloseconds to dry and cure the coating, thereby forming an insulating layer. The thickness of the insulating layer after drying and curing was 35 μm.

Next, in order to apply electroless copper plating to the resin surface, first, the resin surface was subjected to a roughening treatment. Roughening treatment, hydroxide dimethylamide resin surface, sodium dodecyl sulfonate, after swelling treatment using a swelling treatment liquid containing sodium hydroxide and a surfactant, and potassium permanganate (60 g / dm ³⁾ This was carried out by immersing in an etching solution containing sodium (35 g / dm ³ ) as a main component at 353 K for 720 seconds. After the surface of the insulating resin thus roughened was subjected to a neutralization treatment, a hardening treatment was performed at 448 K for 3.6 ksec.

Thereafter, a treatment solution for electroless copper plating made of Shipley was used on each of the roughened resin surfaces, a palladium catalyst was first applied with a catalyst solution, and then an activation treatment was performed. Using an electroless copper plating bath having the composition shown in Table 1, electroless copper plating was performed at 323 K for 1.2 kiloseconds.
The film thickness of the copper deposited by the electroless copper plating was 0.8 μm.

[0064]

[Table 1]

After forming the electroless copper plating film on the insulating layer as described above, an insulating protective coating made of polyvinyl butyral resin was formed on the plating film. This protective coating is prepared by adding a solvent mixture of toluene / xylene / n-butanol (weight ratio: 1/1/1) to a polyvinyl butyral resin (trade name: Eslex-
(BMS) is dissolved to a concentration of 10%.
The coating was formed on the electroless plating film of the substrate by spin coating, followed by drying and curing at 353 K for 1.8 ksec. The film thickness of this insulating protective coating was 12 μm.

Then, using a carbon dioxide laser drill machine (manufactured by Sumitomo Heavy Industries, Impact Model L500), the top diameter was 80 μm.
m, a via hole having a bottom diameter of 50 μm was formed to a depth where the underlying wiring layer was exposed (that is, so as to penetrate the insulating protective coating, the electroless plating film, and the insulating layer). The surface of the substrate other than the via hole is protected by an insulating protective coating.

Next, the substrate was exposed by immersing it in an etching solution containing potassium permanganate and sodium hydroxide as main components at 353 K for 0.72 kiloseconds, which was the same as that used for the roughening treatment of the insulating layer. Roughening treatment of the resin portion of the via hole side wall portion was performed. Since the polyvinyl butyral resin constituting the insulating protective coating is relatively stable to this etching solution, in this roughening treatment, the insulating layer 3 exposed on the side wall of the via hole was preferentially roughened. .

Thereafter, similar to the above-described electroless copper plating,
The catalyst was applied, activated, and subjected to an electroless copper plating treatment for 1.5 ksec in an electroless copper plating bath of 323 K to deposit copper on the side wall and the bottom of the via hole. The film thickness of the deposited copper by the second electroless copper plating was 1 μm, and the copper plating film formed at this time was connected to the first electroless copper plating film whose side surface was exposed on the side wall of the via hole. .

In this second electroless copper plating, slight copper deposition was also observed on the insulative protective coating. However, by performing running water washing treatment for 30 seconds after the electroless copper plating, the insulative protective coating was obtained. The copper deposited on top was completely removed. Also,
It was also observed that the insulating protective coating eluted somewhat during the roughening treatment and the electroless copper plating treatment, and that the film thickness decreased after the electroless plating. However, the reduced thickness of the insulating protective coating was at most about 3 μm, and it was confirmed that even after the film thickness was reduced, the insulating protective coating had sufficient insulating properties and protective properties for the subsequent electrolytic plating step.

In this manner, only the via hole is exposed, and the copper plating film formed by two times of electroless plating is used as the power supply layer for the substrate whose side wall is covered with the electroless copper plating film. A second electrolytic copper plating was performed. For this electrolytic copper plating, a copper sulfate plating bath having a composition shown in Table 2 and containing sulfuric acid and copper sulfate as main components was used. As a plating additive, a commercially available plating additive [Top Lucina manufactured by Okuno Pharmaceutical Co., Ltd.] was used.

[0071]

[Table 2]

Electrolytic copper plating was carried out by applying a current at a current density of 100 A / m ² and a plating bath temperature of 298 K for 10.8 km. Under these conditions, the inside of the via hole was sufficiently filled with the deposited metal. When the minimum height (h) of the deposited metal near the center of the via hole after electrolytic plating was measured by cross-sectional observation using an optical microscope for ten via holes, there was some variation depending on the site (different via holes). It was in the range of 33-35 μm. Since the thickness (t) of the insulating layer in this embodiment is 35 μm, the P value (= h / t), which is a parameter representing the flatness, is 0.94 to 1.0, and the conductor-filled via formed by electrolytic plating is used. Was confirmed to be sufficiently flat.

Thereafter, the substrate was immersed in a mixed solvent of toluene / xylene / n-butanol at room temperature for 180 seconds to dissolve and remove the insulating protective coating, thereby exposing the electroless plating film covered with this coating. .

Next, a photosensitive plating resist (manufactured by JSR, TH
Using B), the resist was patterned through exposure and development by a photolithography method. Thereafter, a second electrolytic copper plating was performed. In the second electrolytic copper plating, the above copper sulfate plating bath was used at the same bath temperature, but the current density was 50 A / m ² and the electrolysis time was 8.4 ksec. Thus, a wiring layer having a thickness of 15 μm was formed.

Thereafter, the photosensitive plating resist is removed with a dedicated alkaline stripping solution, and an etching solution containing sodium persulfate and sulfuric acid is used to remove 308 K, sufficient to remove the first electroless copper plating film. Was performed for 80 seconds to remove the electroless copper plating film remaining on the portion covered with the plating resist.

Thus, a wiring layer of a predetermined pattern connected to the underlying wiring layer via the conductor-filled via was formed on the insulating layer. The surface of the formed wiring layer was highly flat including the via portion. Therefore, when a multilayer wiring board is manufactured by forming an insulating layer and a wiring layer thereon in the same manner as described above, a via penetrating the upper insulating layer immediately above the via penetrating the lower insulating layer does not interfere. Thus, a highly integrated multilayer wiring board in which vias are connected in the vertical direction can be manufactured.

(Comparative Example 1) For comparison, an example is shown in which a similar multilayer wiring board was manufactured by the ordinary semi-additive method without using the insulating protective coating of the present invention. Unless otherwise described, the same treatment liquid as in Example 1 was used.

The underlayer wiring layer and the insulating layer were formed on both surfaces of the same commercially available copper-clad laminate used in Example 1 as in Example 1. After that, a carbon dioxide laser
Using a drill machine, the bottom diameter is 50μ, the same as in Example 1.
A via hole was formed through the insulating layer. The top diameter of this via hole was 80 μm.

Thereafter, a roughening treatment and an electroless copper plating treatment are carried out, so that the surface of the insulating layer including the via holes has a thickness of 1 μm.
m of electroless copper plating film was formed. Next, after applying and patterning a photosensitive plating resist, electrolytic via plating was simultaneously performed on both the via hole portion and the wiring portion using a copper sulfate plating bath.

The electrolytic copper plating was performed under the same conditions (current density: 50 A / m ² × 8.4 ksec) as the ^second electrolytic copper plating in Example 1 so that the film thickness of the wiring portion became the target value of 15 μm. went. As a result, the thickness of the wiring portion was 15 μm, which was the target value. However, metal deposition in the via hole portion was insufficient, and a large concave portion remained. The P value, which is a parameter representing the flatness, was as small as 0.36 to 0.49 for the measured values of the ten via holes, and the variation depending on the measurement site was large.

Comparative Example 2 Comparative Example 1 was repeated, except that the electrolytic copper plating step was performed at a current density of 50 A / m ^{2 for} 21.6 kiloseconds in order to complete metal deposition inside the via hole. Was. As a result, the via holes were substantially completely filled with metal, and the P values of the ten via holes were as good as 0.92 to 0.99. However, the thickness of the wiring layer exceeded 36 μm, and it was not practical for practical use considering the necessary thickness of the insulating layer.

[0082]

According to the method of the present invention, a relatively large via hole can be substantially completely filled with a conductive metal while the thickness of the wiring portion is maintained at a desired thickness, and the via portion is flat. A flexible wiring layer can be formed. As a result, it is possible to form a via directly above, and the integration degree is high.
In addition, a multilayer wiring board having excellent connection reliability and durability can be easily manufactured.

[Brief description of the drawings]

FIGS. 1 (a) to 1 (e) are explanatory views showing cross sections of a multilayer wiring board in different stages of a method of manufacturing a multilayer wiring board according to the present invention.

FIG. 2 shows the thickness (t) of the insulating layer and the minimum height of the deposited metal at the center of the via hole when the via hole is filled with metal.
It is explanatory drawing which shows the measurement site of (h). However, this figure shows a case where a metal is simultaneously deposited in the wiring portion and the via hole by one electrolytic plating according to the conventional additive method.

[Explanation of symbols]

1: substrate, 2: base wiring layer, 3: insulating resin, 4: electroless copper plating film, 5: insulating protective coating, 6: via hole, 7: electroless copper plating film in via hole, 8: first
9: photosensitive plating resist, 10: patterned wiring layer by second electrolytic plating, 1
1: Electroplated copper.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E346 AA43 CC32 DD23 DD24 DD25 DD44 DD47 FF07 FF13 FF14 FF18 GG15 GG17 GG22 GG28 HH07

Claims (4)

[Claims] 1. A method for forming a conductor-filled via penetrating an insulating layer in a laminate including a laminated structure in which an insulating layer is interposed between upper and lower conductor layers, the method comprising the steps of: And how. (A) forming an insulating protective coating covering the upper conductor layer,
(B) a step of forming a via hole that penetrates the insulating protective coating and the upper conductor layer and the insulating layer below the insulating protective coating, and (C) selectively forms a conductor plating film on the insulating layer exposed on the side wall of the via hole. And (D) filling the via hole with a conductor by performing electrolytic plating. 2. A ratio P (P = h / t) of the minimum height (h) near the center of the via hole to the thickness (t) of the insulating layer of the conductor filled in the via hole in the step (D) is 0.8 to 0.8. 1.
The method of claim 1, wherein 3. A method for manufacturing a multilayer wiring board, comprising the following steps after forming a conductor-filled via according to the method according to claim 1. (E) a step of removing the insulating protective coating, and (F) a step of forming a wiring pattern on the upper conductor layer. 4. A method of manufacturing a multilayer wiring board, comprising the steps of: (a) forming an insulating layer on a base wiring layer; and (b) electroless plating the upper surface of the insulating layer. A step of forming a conductor plating film, (c) a step of forming an insulating protective coating covering the electroless plating film, and (d) penetrating the insulating protective coating and the electroless plating film and the insulating layer thereunder. A step of forming a via hole, (e) a step of selectively forming a conductor plating film by electroless plating on the insulating layer exposed on the side wall of the via hole, and (f) a step of filling the via hole with a conductor by performing electrolytic plating. (G) removing the insulating protective coating to expose an electroless plating film thereunder;
(h) a step of forming a plating resist pattern on the exposed electroless plating film, (i) a step of forming a conductor layer patterned by electrolytic plating, (j) a step of removing the plating resist pattern, (k) A step of removing the exposed electroless plating film by etching.