JP2009276174A - Measurement method, measurement program, and measuring device - Google Patents

Abstract

[PROBLEMS] To shorten test time.
A step of comparing the magnitude of a voltage of a variable resistor that changes according to a predetermined variable pattern of the variable resistor with a reference first voltage, and a comparison result by the first voltage in a storage means. A step of storing, a step of comparing the magnitudes of the voltage of the variable resistor and a second voltage different from the first voltage, a step of storing the comparison result by the second voltage in the storage means, And a step of specifying a resistance value of the variable resistor based on the comparison result by the second voltage and the comparison result by the second voltage.
[Selection] Figure 11

Description

  The present invention relates to a measurement method, a measurement program, and a measurement apparatus, and more particularly to a measurement method, a measurement program, and a measurement apparatus that measure a resistance value of a variable resistor included in an electronic circuit.

  In recent years, with the increase in data transmission volume, a band exceeding 1 Gbps is becoming widespread for high-speed device transmission and high-speed signal transmission. In order to ensure high-speed signal transmission quality, LSI (Large Scale Integration circuit) Also, various design techniques have been taken (see, for example, Patent Document 1).

  In LSI, in order to reduce the deviation in output timing, by adjusting the impedance value of the output driver inside the LSI, the drive capability switching function that corrects the voltage so that the pull-up resistance and pull-down resistance of the output signal are equal Built in.

This function is mounted as an OCD (Off Chip Driver) function in, for example, a DDR2 SDRAM (Double Data Rate 2 Synchronous DRAM (Random Access Memory)).
Japanese Patent Laid-Open No. 10-285012

At the time of product shipment or the like, it is necessary to test whether the drive capability switching function provided in the LSI is operating normally.
As this test apparatus, DC current measurement and DC voltage measurement using a DC unit are generally known.

  However, the resistance used for the drive capability switching function is multistage. In response to the demand for LSI (System On Chip), LSIs are equipped with a variety of analog circuits such as A / D converters, D / A converters, and amplifiers, and memory controller circuits. And analog circuits are also equipped with many drive capability switching functions.

  In order to guarantee the function of an LSI with a built-in drive capability switching function, DC current measurement using DC units equal to the number of terminals and the number of stages of pull-up / pull-down resistors depends on the number of DC units that can be measured simultaneously. It is necessary to repeat DC voltage measurement. Also, in a large-scale LSI that has been made into an SOC, there are hundreds of combinations of the number of terminals and the number of stages of pull-up / pull-down.

Therefore, in DC current measurement and DC voltage measurement using a DC unit, an increase in test time is a problem.
The present invention has been made in view of these points, and an object of the present invention is to provide a measurement method, a measurement program, and a measurement apparatus that can shorten the test time.

In order to achieve the above object, a measurement method for measuring the resistance value of a variable resistor included in an electronic circuit is provided. This measurement method is realized by executing the following steps.
(1) A step of comparing the magnitude of the voltage of the variable resistor that changes in accordance with a predetermined variable pattern of the variable resistor and the first voltage as a reference.

(2) A step of storing the comparison result by the first voltage in the storage means.
(3) A step of comparing the magnitudes of the voltage of the variable resistor and the second voltage different from the first voltage.

(4) A step of storing the comparison result by the second voltage in the storage means.
(5) A step of specifying a resistance value of the variable resistor based on the comparison result by the first voltage and the comparison result by the second voltage.

  In order to achieve the above object, a measuring device for testing a variable resistor that adjusts the impedance of a signal output terminal of an electronic circuit is provided. This measuring apparatus includes a pattern signal output unit, a comparison unit, and a determination unit.

The pattern signal output unit outputs a plurality of pattern signals for changing the resistance value of the variable resistor.
The comparison unit compares an output voltage having a different value output from the signal output terminal in accordance with a change in the resistance value with a comparison voltage that can distinguish the change in the resistance value. Thereby, for example, the logic output from the comparison unit is switched at a certain part.

  The determination unit determines whether each result compared by the comparison unit matches a result prepared in advance according to the magnitude of the comparison voltage. For example, it is determined whether or not the logic switching portion matches the switching portion of the result prepared in advance.

  It can be determined whether or not the variable resistor is operating normally based on the determination result of the determination unit.

  According to the disclosed measurement method, measurement program, and measurement apparatus, the resistance value of the variable resistor is specified by comparing the magnitudes of the voltages, so that the test time can be shortened.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing a system configuration.
In the test system 30, a test apparatus (tester) 20 is detachably connected to the LSI circuit 10.

The LSI circuit 10 is a circuit to be tested, and has drive circuits (I / O circuits) 11, 11,.
Each drive circuit 11 includes an input / output driver D1 and an impedance matching resistor Ra.

The input / output driver D1 outputs a signal generated inside the LSI circuit 10 via the bus line. Further, an external signal is input via the bus line.
The impedance matching resistor Ra adjusts the impedance with an external device connected to the output terminal B1 of the corresponding input / output driver D1.

The test apparatus 20 tests whether the impedance adjustment function of the impedance matching resistor Ra operates correctly.
Specifically, in FIG. 1, each output terminal B <b> 1 is connected to the test apparatus 20, and the output values of the drive circuits 11, 11,... Pass through the output terminals B <b> 1, B <b> 1,. Are input to the test apparatus 20.

  The test apparatus 20 inputs a signal to the control terminal A and inspects the signal output from each output terminal B1, thereby testing whether the impedance adjustment function of the impedance matching resistor Ra operates correctly.

Hereinafter, since each drive circuit 11 has the same function, only one drive circuit 11 will be described below.
FIG. 2 is a diagram illustrating a circuit configuration of the drive circuit.

The input / output driver D1 has a P-channel transistor P1 and an N-channel transistor N1.
The source electrode of the P-channel transistor P1 is connected to the VDD terminal, and the source electrode of the N-channel transistor N1 is connected to the GND terminal.

The impedance matching resistor Ra has a pull-down resistor RP1 and a pull-up resistor RP2.
The pull-down resistor RP1 has one end connected to the GND terminal, the other end connected to the switch SW1, one end connected to the GND terminal, the other end connected to the switch SW2, and one end GND. A resistor R3 connected to the terminal and having the other end connected to the switch SW3 is connected in parallel.

A resistance current of 1 mA flows through the resistor R1, a resistance current of 2 mA flows through the resistor R2, and a resistance current of 4 mA flows through the resistor R3.
The pull-up resistor RP2 has one end connected to the VDD terminal, the other end connected to the switch SW4, one end connected to the VDD terminal, the other end connected to the switch SW5, and one end connected to the switch SW5. A resistor R6, which is connected to the VDD terminal and has the other end connected to the switch SW6, is connected in parallel.

A resistance current of 1 mA flows through the resistor R4, a resistance current of 2 mA flows through the resistor R5, and a resistance current of 4 mA flows through the resistor R6.
One end of each of the switches SW1 to SW6 is connected to the resistors R1 to R6, and the other end is connected to the output of the input / output driver D1.

  The switches SW1 to SW6 are switched by test pattern signals input from control terminals A1 to A6 (corresponding to the control terminal A in FIG. 1), respectively. The test apparatus 20 outputs this test pattern signal as described above.

  Specifically, the switch SW1 is switched by the test pattern signal input from the control terminal A1, the switch SW2 is switched by the test pattern signal input from the control terminal A2, and the test pattern input from the control terminal A3. The switch SW3 is switched by the signal, the switch SW4 is switched by the test pattern signal input from the control terminal A4, the switch SW5 is switched by the test pattern signal input from the control terminal A5, and input from the control terminal A6. The switch SW6 can be switched by the test pattern signal.

By switching the switches, the pull-down resistor RP1 and the pull-up resistor RP2 can each create a 3-bit resolution, that is, eight types of resistance values.
FIG. 3 is a diagram illustrating a circuit configuration of the test apparatus.

The test apparatus 20 includes a test circuit 21 and a measurement unit 22.
The test circuit 21 is provided for each drive circuit 11 of the LSI circuit 10. Since one drive circuit 11 is described in FIG. 3, one test circuit 21 is illustrated.

The test circuit 21 includes a driver D2, a termination resistor Rref, and two comparators CMP1 and CMP2.
The driver D2 is connected to the output terminal B1 via the resistor R1.

  A reference voltage Vref is applied to the termination resistor Rref. The termination resistor Rref has a resistance value of 50Ω, for example, and converts the signal output from the output terminal B1 into a voltage so that the comparators CMP1 and CMP2 can compare the voltages.

  The comparators CMP1 and CMP2 are connected in parallel to the termination resistor Rref, respectively, and the divided voltage divided by the ON resistance of the transistor, the pull-down resistor RP1, the pull-up resistor RP2, and the termination resistor Rref is a comparator. Comparison is made with the comparison voltages of CMP1 and CMP2.

The comparator CMP1 measures the Hi side voltage, and the comparator CMP2 measures the Lo side voltage.
In the test of the impedance adjustment function, the measurement unit 22 outputs the voltage VDD to the LSI circuit 10, and outputs the drive voltage and the comparison voltage to the comparators CMP1 and CMP2.

Further, the comparison result voltages of the comparators CMP1 and CMP2 are taken in, and it is determined whether or not the impedance adjustment function of the LSI circuit 10 operates normally.
FIG. 4 is a diagram illustrating a hardware configuration example of the measurement unit.

  The entire measuring unit 22 is controlled by a CPU (Central Processing Unit) 22a. A RAM 22b, a ROM (Read Only Memory) 22c, and a power source 22d are connected to the CPU 22a.

  The RAM 22b temporarily stores at least part of a program to be executed by the CPU 22a. The RAM 22b stores various data necessary for processing by the CPU 22a. The ROM 22c stores program files and the like.

The power supply 22d generates a voltage to be output to each unit.
With the circuit configuration as described above, the processing function of the present embodiment can be realized. In order to test the impedance adjustment function in a system having such a circuit configuration, the following functions are provided in the measurement unit 22.

FIG. 5 is a block diagram illustrating functions of the measurement unit.
The measurement unit 22 includes a comparison voltage output unit 221, a test pattern storage unit 222, a test pattern signal output unit 223, a comparison result voltage acquisition unit 224, a comparison result voltage storage unit 225, and an expected value determination table storage unit. 226, an expected value determination unit 227, and a result output unit 228.

  The comparison voltage output unit 221 outputs a drive voltage and a comparison voltage to the comparators CMP1 and CMP2. The voltage level of the comparison voltage corresponds to a comparator level described later.

The test pattern storage unit 222 stores test patterns for creating the plurality of test pattern signals described above.
The test pattern signal output unit 223, in accordance with the test pattern stored in the test pattern storage unit 222, is a test pattern signal (P In the P channel transistor P1 and the N channel transistor N1, this corresponds to a gate signal).

  As described above, the test pattern signal output unit 223 compares the comparators CMP1 and CMP2 by changing the combination of the pull-down resistor RP1 and the pull-up resistor RP2 by outputting voltages having different patterns to the control terminals A1 to A6. Change the resulting voltage.

The comparison result voltage acquisition unit 224 acquires the comparison result voltage output from the comparators CMP <b> 1 and CMP <b> 2 and stores it in the comparison result voltage storage unit 225.
The comparison result voltage storage unit 225 stores the comparison result voltage acquired by the comparison result voltage acquisition unit 224.

The expected value determination table storage unit 226 stores a table in which data for determination of the expected value determination unit 227 is stored.
The expected value determination unit 227 includes the comparison voltage output from the comparison voltage output unit 221, the comparison result voltage stored in the comparison result voltage storage unit 225, and the table stored in the expected value determination table storage unit 226. Based on the above, it is determined whether or not a comparison result corresponding to the test pattern output by the test pattern signal output unit 223 is obtained.

The result output unit 228 outputs the determination result of the expected value determination unit 227.
Next, the data configuration of the test pattern storage unit 222 will be described. In the test pattern storage unit 222, data is stored as a table.

FIG. 6 is a diagram illustrating an example of the data structure of the test pattern table.
The test pattern table 222a has columns of test address, control terminal, P channel transistor and N channel transistor, and pieces of information arranged in the horizontal direction are associated with each other.

  In the test address column, names (address 1 to address 6) for identifying the type of the test pattern signal output to the control terminal, the P channel transistor and the N channel transistor are stored.

In the control terminal column, voltage patterns (0 or 1) output to the control terminals A1 to A6 are stored.
In the column of the P channel transistor and the N channel transistor, ON / OFF patterns (0 or 1) of the P channel transistor and the N channel transistor are stored, respectively.

Next, the data structure of the comparison result voltage storage unit 225 will be described. The comparison result voltage storage unit 225 stores the data in a table.
FIG. 7 is a diagram illustrating a data structure example of the comparison result voltage table.

A plurality of comparison result voltage tables 225a are provided corresponding to the number of voltage levels of the comparison voltage output from the comparison voltage output unit 221, that is, the comparison level.
Each comparison result voltage table 225a has columns of test address and terminal number, and information arranged in the horizontal direction is associated with each other.

The same address name as the test address column of the test pattern table 222a is stored in the test address column.
In the terminal number column, numbers p1 to p7 for identifying the output terminal B1 of the drive circuit 11 are provided. For example, in FIG. 1, the upper output terminal B1 corresponds to the number p1, and the lower output terminal B1 corresponds to the number p2.

Each of these columns stores the logic (“H” or “L”) of the comparison result voltage output from the comparators CMP1 and CMP2 in accordance with the output of the test pattern signal.
Next, the data structure of the expected value determination table storage unit 226 will be described.

FIG. 8 is a diagram illustrating a data structure example of the expected value determination table.
The expected value determination table 226a is provided with test address and comparison level columns, and pieces of information arranged in the horizontal direction are associated with each other.

In the test address column, address names corresponding to the test address column of the test pattern table 222a are stored.
In the column of the comparator level, a plurality of comparator levels (1 to 7 in FIG. 8) corresponding to the resolution of the impedance matching resistor Ra are provided.

  At each comparator level, the logic (expected value) expected to be output from the comparators CMP1 and CMP2 in accordance with the value of the comparison voltage output by the comparison voltage output unit 221 to the comparators CMP1 and CMP2 is for each address. Stored.

9 and 10 are diagrams showing specific examples of the comparison level.
FIG. 9 illustrates the relationship between the comparison voltage corresponding to “Comparative level 2” and the voltage applied to the input terminals of the comparators CMP1 and CMP2 in accordance with the change of the test address.

  As shown in FIG. 9, in the case of “comparation level 2”, only when the test pattern signal of address 3 is output, the output result is lower than the voltage of “comparation level 2” (for comparison, such as below) Therefore, the comparator CMP2 outputs “L”. When the test pattern signal of the remaining address is output, the output result exceeds the voltage of “Comparator level 2”, and therefore “H” is output by the comparator CMP1.

  FIG. 10 illustrates the relationship between the comparison voltage corresponding to “comparation level 4” and the voltage applied to the input terminals of the comparators CMP1 and CMP2 in accordance with the change of the test address.

  As shown in FIG. 10, in the case of “comparation level 4”, when the test pattern signals of address 1, address 2 and address 3 are output, the output result is lower than the voltage of “comparation level 4”. Therefore, “L” is output by the comparator CMP2. When the test pattern signals of address 4, address 5, and address 6 are output, the output result exceeds the voltage of “comparation level 4”, so that “H” is output by the comparator CMP1.

By comparing these results with expected values, it can be determined whether or not the impedance matching resistor Ra is operating correctly.
Next, the process of the measurement part 22 is demonstrated.

FIG. 11 is a flowchart showing the processing of the measurement unit.
First, the comparison voltage output unit 221 outputs a comparison voltage corresponding to the determined comparison level to the comparators CMP1 and CMP2 (step S1).

  Next, the test pattern signal output unit 223 outputs the test pattern signals of the test addresses stored in the test pattern table 222a in order from the smallest address number, the control terminals A1 to A6, the P channel transistor P1, and the N channel transistor. Output to N1 (step S2).

  Each time the test pattern signal is output, the comparison result voltage acquisition unit 224 sequentially stores the logic of the comparison result voltage output from the comparators CMP1 and CMP2 in the comparison result voltage table 225a (step S3).

  When the storage of the logic of the comparison result voltage for all the test pattern signal outputs is completed, the comparison voltage output unit 221 determines whether there is another comparison level (step S4).

When another comparison level exists (Yes in step S4), the process proceeds to step S1, another comparison level is determined, and the processing after step S1 is continuously performed.
When there is no other comparison level (No in step S4), the expected value determination unit 227 compares the value stored in the comparison result voltage table 225a with the expected value stored in the expected value determination table 226a. Then, it is determined whether or not they match (step S5).

Next, the determination result is output (step S6).
Above, description of description of the process of the measurement part 22 is complete | finished.
Next, a specific example of the processing of the measurement unit 22 will be described using the comparison result voltage table 225a shown in FIG.

First, the comparison voltage output unit 221 outputs a comparison voltage corresponding to “comparate level 4” to the comparators CMP1 and CMP2.
Then, the test pattern signals stored in the test pattern table 222a are sequentially output from address 1 to address 6.

  As shown in FIG. 10, in the case of “comparation level 4”, when the test pattern signals of address 1, address 2 and address 3 are output, “L” is output by the comparator CMP2. When the test pattern signals of address 4, address 5, and address 6 are output, “H” is output by the comparator CMP1. In the terminal number column of the comparison result voltage table 225a, logics corresponding to the test addresses are sequentially stored.

  When the measurement is completed, the expected value determination unit 227 compares the value stored in the comparison result voltage table 225a with the expected value of “Comparator level 4” stored in the expected value determination table 226a shown in FIG. , It is determined whether or not they match.

  In the comparison result voltage table 225a shown in FIG. 7, the expected value does not match the logic at the terminal number p4. Therefore, it outputs that the impedance matching resistor Ra of the terminal number p4 is not operating correctly. Further, it outputs that the impedance matching resistors Ra of other terminal numbers are operating correctly.

  Note that the determination result may be output in such a manner that only terminal numbers that are not operating correctly may be output, or terminal numbers that are not operating correctly and terminal numbers that are operating correctly can be distinguished. It may be.

  As described above, according to the test system 30 of the present embodiment, the impedance matching resistor Ra is operating correctly by the measurement unit 22 repeating binary determination of the comparison result voltage and the expected value. Can be tested.

As a result, the test time can be significantly shortened (for example, about 70%) as compared with the case where DC current measurement or DC voltage measurement is performed.
According to the test apparatus 20, the effect of shortening the test time increases as the combination of the number of terminals of the LSI circuit 10 and the resistance of the impedance matching resistor Ra increases.

  In the present embodiment, the expected value determination unit 227 performs the determination based on the contents of the expected value determination table 226a. However, the present invention is not limited to this, for example, the logic of the comparison result voltage of each terminal number. The determination may be made by comparing each other.

  The measurement method, the measurement program, and the measurement apparatus of the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit is an arbitrary function having the same function. It can be replaced with the configuration of Moreover, other arbitrary structures and processes may be added to the present invention.

In addition, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
Note that the measurement method of the present invention can be applied to, for example, an LSI including a PCI Express (Express) in addition to the above-described DDR2 SDRAM.

  The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the function that the measurement unit 22 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Examples of the magneto-optical recording medium include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the measurement program stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

It is a figure which shows the structure of a system. It is a figure which shows the circuit structure of a drive circuit. It is a figure which shows the circuit structure of a test apparatus. It is a figure which shows the hardware structural example of a measurement part. It is a block diagram which shows the function of a measurement part. It is a figure which shows the data structure example of a test pattern table. It is a figure which shows the example of a data structure of a comparison result voltage table. It is a figure which shows the example of a data structure of an expected value determination table. It is a figure which shows the specific example of a comparison level. It is a figure which shows the specific example of a comparison level. It is a flowchart which shows the process of a measurement part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 LSI circuit 11 Drive circuit 20 Test apparatus 21 Test circuit 22 Measuring part 22a CPU
22b RAM
22c ROM
22d power supply 30 test system 221 comparison voltage output unit 222 test pattern storage unit 222a test pattern table 223 test pattern signal output unit 224 comparison result voltage acquisition unit 225 comparison result voltage storage unit 225a comparison result voltage table 226 expected value determination table storage unit 226a Expected value determination table 227 Expected value determination unit 228 Result output unit CMP1, CMP2 Comparator A, A1-A6 Control terminal B1 Output terminal D1 Input / output driver Ra Impedance matching resistor Rref Terminating resistor

Claims (8)

In a measurement method for measuring the resistance value of a variable resistor included in an electronic circuit,
Comparing the voltage of the variable resistor, which changes according to a predetermined variable pattern of the variable resistor, with the reference first voltage, respectively,
Storing the comparison result of the first voltage in a storage means;
Comparing the magnitude of the voltage of the variable resistor and the second voltage different from the first voltage, respectively;
Storing the comparison result of the second voltage in the storage means;
Identifying a resistance value of the variable resistor based on a comparison result by the first voltage and a comparison result by the second voltage;
A measuring method characterized by comprising:   The step of specifying the resistance value includes a step of comparing a comparison result by the first voltage and a comparison result by the second voltage with a prepared determination value, respectively. 1. The measuring method according to 1.   The measurement method according to claim 1, wherein the variable resistor is a resistance element for impedance matching of the electronic circuit. In a measurement program that measures the resistance value of a variable resistor included in an electronic circuit,
On the computer,
Comparing the voltage of the variable resistor, which changes according to a predetermined variable pattern of the variable resistor, with the reference first voltage, respectively.
Storing the comparison result of the first voltage in a storage means;
Comparing the magnitude of the voltage of the variable resistor with a second voltage different from the first voltage;
Storing the comparison result by the second voltage in the storage means;
Identifying a resistance value of the variable resistor based on a comparison result by the first voltage and a comparison result by the second voltage;
A measurement program characterized by causing In a measuring device for testing a variable resistor that adjusts the impedance of a signal output terminal of an electronic circuit,
A pattern signal output unit for outputting a plurality of pattern signals for changing the resistance value of the variable resistor;
A comparison unit that compares an output voltage having a different value output from the signal output terminal according to the change in the resistance value with a comparison voltage that can distinguish the change in the resistance value, respectively.
A determination unit that determines whether or not each result compared by the comparison unit matches a result prepared in advance according to the magnitude of the comparison voltage;
A measuring apparatus comprising: A plurality of the comparison voltages are prepared,
The measuring device according to claim 5, wherein the comparison unit compares output voltages having different values output from the signal output terminal in accordance with a change in the resistance value with a plurality of the comparison voltages. . The variable resistor has a plurality of resistance elements having different resistance values,
The pattern signal is a signal using any one of the plurality of resistance elements,
The measuring apparatus according to claim 6, wherein each of the comparison voltages is a voltage corresponding to a resolution of the variable resistor.   The measuring apparatus according to claim 5, further comprising a comparison voltage output unit that outputs the comparison voltage to the comparison unit.

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