JP2009194685A - Signal transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal transmission system for suppressing the effect of capacitive reflection. <P>SOLUTION: In a configuration including, e.g., a transmission circuit TX, a reception circuit RX and a transmission line LN connecting these circuits, a resistor R1 is inserted in series between the receiving terminal Nr of the transmission line LN and the reception circuit RX. The resistor R1 is made into a resistance value equal to characteristic impedance Z0 of the transmission line LN. Furthermore, in the reception circuit RX, a capacitor C1 indicating gate capacitance or the like of an MIS transistor that becomes an input buffer is provided. Consequently, even when the impedance of the capacitor C1 inside the reception circuit RX becomes zero in transition of transmission signal, a reflection coefficient at the receiving terminal Nr becomes equal to 0 or greater, thereby obtaining a monotonic signal waveform within the transmission line LN at all times. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a signal transmission system, and more particularly to a technique that is useful when applied to a high-speed signal transmission system that performs desired processing using signal edges.

For example, in a signal transmission system that performs signal transmission from a transmission end to a reception end on a transmission line, in general, in order to suppress signal reflection, the impedance of the transmission line is between the reception end of the transmission line and the power supply voltage. A termination resistor having the same value as is provided. Further, for example, FIG. 6.7 of Non-Patent Document 1 describes an explanation of capacitive reflection and inductive reflection in a transmission line.
Ron K. Poon, “Computer Circuits Electrical Design”, Prentice Hall, April 1995, p. 158

  By the way, as a result of the inventor's study on the technology of the signal transmission system as described above, the following has been clarified.

  In recent years, with the increase in signal transmission speed, the rising or falling time of the signal waveform has been shortened, and the rising or falling edge of the voltage waveform becomes a problem, such as a clock signal or an asynchronous strobe signal. The effect of capacitive reflection that appears in For example, the rise or fall time of the voltage waveform has been on the order of several ns in the past, but in recent high-speed interfaces (for example, DDR2 SDRAM), it is on the order of several hundred ps. is expected.

  FIG. 4 is a schematic diagram showing an example of the configuration of the signal transmission system studied as a premise of the present invention. The signal transmission system shown in FIG. 4 includes a transmission circuit TX, a reception circuit RX, and a transmission line LN connecting them. The transmission circuit TX transmits a pulse signal from the pulse generation circuit PG serving as an output buffer to the transmission end Nt of the transmission line LN via the output resistor R2, and the reception circuit RX receives this pulse signal via the reception end Nr of the LN. The data is received by a transistor (such as a MIS (Metal Insulator Semiconductor) transistor) TR serving as an input buffer.

  The transmission line LN has a characteristic impedance Z0, and the output resistance R2 is designed to have the same resistance value as the Z0, for example. The transistor TR of the receiving circuit RX can be represented by a capacitor C1 equivalently connected between the receiving end Nr and the ground voltage GND due to its gate-source capacitance, gate-substrate capacitance, and the like. FIG. 5 is a simulation circuit diagram illustrating the configuration example of FIG. 4, FIG. 6 is a simulation result of FIG. 5, and (a) to (e) are waveform diagrams acquired at different nodes.

  In the simulation circuit shown in FIG. 5, the characteristic impedance Z0 and the output resistance R2 are set to 50Ω, the delay time (length) of the transmission line LN is divided in units of 0.5ns to obtain a total of 2ns, and the capacitance C1 is set to 0pF, 10pF, and 20pF. , 30 pF, 40 pF, and 50 pF. Further, the transmission end Nt and the reception end Nr of the transmission line LN correspond to the node (NearEnd) and the node (FarEnd), respectively, and in that order, the node (Tap1) and the node in order of 0.5 ns from the node (FarEnd) side. (Tap2) and a node (Tap3) are provided. FIG. 6 shows a result of transmitting a waveform having an amplitude of 5 V with a rise time of 1 ns from the voltage generation source V1 (pulse generation circuit PG) under these conditions. In FIG. 6, (a), (b), (c), (d), and (e) respectively represent a node (FarEnd), a node (Tap1), a node (Tap2), a node (Tap3), and a node (NearEnd). ) Waveform.

As shown in FIG. 6A, in the node (FarEnd), although the waveform becomes dull as the capacitance C1 increases, a monotonically increasing (monotonic) waveform is obtained. On the other hand, as shown in FIGS. 6B to 6E, when the capacitance C1 is other than 0 pF at other nodes, it is once decreased from 2.5 V as the intermediate potential and then increased again toward 5 V. This is a non-monotonic waveform. This is because, while the capacitor C1 is being charged, the impedance of the capacitor C1 instantaneously appears to be zero, so that the impedance of the capacitor C1 is Z _C1 and the reflection coefficient Γ (= (Z _C1 −Z0) from the receiving end Nr. ) / (Z _C1 + Z0)).

  FIG. 7 is another simulation circuit diagram illustrating the configuration example of FIG. 4, FIG. 8 is a simulation result of FIG. 7, and (a) to (e) are waveform diagrams acquired at different nodes. The simulation circuit shown in FIG. 7 differs from the case of FIG. 5 in that the capacitance C1 is fixed at 10 pF, the delay time (length) of the transmission line LN is divided by 0.25 ns to make a total of 1 ns, and the voltage generation source V1 The rise time trf of the waveform transmitted from the (pulse generation circuit PG) can be set in increments of 300 ps from 300 ps to 3 ns. The rest is the same as in FIG. Further, each node shown in FIGS. 8A to 8E is the same as the case in FIG. 7 except that the interval between the nodes is 0.25 ns.

  As shown in FIG. 8A, at the node (FarEnd), a monotonically increasing (monotonic) waveform is obtained regardless of the rise time trf. On the other hand, as shown in FIGS. 8B to 8E, in other nodes, the tendency of non-monotonic waveforms as described above appears as the rise time trf becomes shorter. For example, when the rise time trf is 3 ns, a monotonic waveform is obtained. However, when trf is about 1 ns, a non-monotonic waveform becomes obvious depending on the node, and when trf reaches 300 ps, the node (FarEnd) Non-monotonic waveforms at all nodes except. Thus, a non-monotonic waveform is generated as the rise time (fall time) becomes shorter as the transmission speed increases. Qualitatively, this is due to the fact that the impedance of the capacitor C1 decreases and the negative reflected wave increases as the rise (fall) time becomes shorter (that is, the frequency becomes higher).

  When such a non-monotonic waveform is generated, the potential level in the vicinity of the threshold (for example, 2.5 V) becomes unstable. For example, when it is used as a clock waveform or a strobe waveform, an error occurs within one rising edge. There is a possibility that two rising edges are detected, or that a rising edge and a falling edge are detected once. Of course, there is no problem at the receiving end Nr because a monotonic waveform is obtained. However, when a signal is obtained by branching from another node (for example, the node (Tap1)), a normal signal is obtained. It will not be possible. Note that even if a terminating resistor equal to the characteristic impedance Z0 is provided at the receiving end Nr, such a problem cannot be avoided because the impedance of the capacitor C1 acts mainly.

  The present invention has been made in view of the above, and one of its purposes is to provide a signal transmission system capable of suppressing the influence of capacitive reflection. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

  A signal transmission system according to an embodiment of the present invention includes a transmission circuit, a transmission line having a first characteristic impedance, and a reception circuit having an equivalent capacitive input unit. A first resistor having a first characteristic impedance or higher is connected in series between the end and the input portion of the receiving circuit. The capacitive input unit corresponds to a capacitor such as a gate of a MIS transistor, for example.

  When such a configuration is used, since the impedance when the receiving circuit is viewed from the receiving end of the transmission line is at least the first characteristic impedance, even if the impedance of the capacitive input unit becomes zero, There is no negative reflection coefficient. Therefore, since a monotonic signal waveform is always obtained in the transmission line, for example, it is possible to transmit a signal waveform branched and extracted from the transmission line to another receiving circuit. Such a configuration is particularly useful when the signal waveform uses an edge portion such as a clock signal waveform or a strobe signal waveform.

  By using the signal transmission system according to the embodiment of the present invention, it is possible to suppress the influence of capacitive reflection typically.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  FIG. 1 is a schematic diagram showing an example of the configuration of a signal transmission system according to an embodiment of the present invention. The signal transmission system shown in FIG. 1 includes a transmission circuit TX, a reception circuit RX, and a transmission line LN connecting them. The transmission circuit TX transmits a pulse signal from the pulse generation circuit PG serving as an output buffer to the transmission end Nt of the transmission line LN via the output resistor R2. The receiving circuit RX receives this pulse signal by the capacitor C1 provided between Nr and the ground voltage GND via the receiving end Nr of the transmission line LN. The capacitor C1 corresponds to a gate capacitor such as a MIS transistor as described in FIG. The transmission line LN has a characteristic impedance Z0. The output resistance R2 is not particularly limited, but is designed to have the same resistance value as Z0, for example.

  In such a configuration, the main feature of the signal transmission system of the present embodiment is that a series-connected resistor R1 is inserted between the receiving end Nr of the transmission line LN and one end of the capacitor C1, and the resistance of this R1 The value is equal to the characteristic impedance Z0 of LN. For example, when the transmission circuit TX and the reception circuit RX are different LSI devices mounted on a multilayer wiring board and the transmission line LN is a microstrip line formed by the multilayer wiring board, the resistor R1 is the multilayer wiring board. It may be mounted as an external resistance element on the top, or may be formed as a built-in resistance element in the receiving circuit RX.

  2 is a simulation circuit diagram illustrating the configuration example of FIG. 1, FIG. 3 is a simulation result of FIG. 2, and (a) to (e) are waveform diagrams acquired at different nodes. In the simulation circuit shown in FIG. 2, the characteristic impedance Z0, the output resistance R2, and the resistance R1 are each 50Ω, the delay time (length) of the transmission line LN is divided in units of 0.5 ns, and the total is 2 ns, and the capacitance C1 is It can be set to 6 levels of 0 pF, 10 pF, 20 pF, 30 pF, 40 pF, and 50 pF. The transmission end Nt and the reception end Nr of the transmission line LN correspond to a node (NearEnd) and a node (FarEnd), respectively, and in that order, the node (Tap1) and the node in units of 0.5 ns from the node (FarEnd) side. (Tap2) and a node (Tap3) are provided.

  Here, the length of the transmission line LN is represented by a delay time. For example, the speed at which the voltage waveform is transmitted on the transmission line LN formed of a multilayer wiring board is inversely proportional to the square root of the effective relative dielectric constant around the LN. When the effective relative dielectric constant is 1, the delay time 1 ns corresponds to about 30 cm. When a copper-clad laminate using a glass cloth base epoxy resin widely known as a multilayer wiring board is used, the relative dielectric constant is 4.2 to 4.8. Therefore, depending on the cross-sectional structure of the transmission line, assuming that the effective relative dielectric constant is 4, the square root of 4 is 2, so 1 ns corresponds to about 15 cm. That is, typically, the delay time 0.5 ns of the transmission line LN in FIG. 2 represents about 7.5 cm, and the delay time 2 ns represents about 30 cm. For example, when a memory module serving as another multilayer wiring board is mounted on a connector on the multilayer wiring board on which the memory controller is mounted and a control signal is transmitted from the memory controller to the memory module. Etc. can occur sufficiently.

  FIG. 3 shows a result of transmitting a waveform having an amplitude of 5 V from the voltage generation source V1 (pulse generation circuit PG) with a rise time of 1 ns under such conditions. In FIG. 3, (a), (b), (c), (d), and (e) respectively represent a node (FarEnd), a node (Tap1), a node (Tap2), a node (Tap3), and a node (NearEnd). ) Waveform. Various conditions of this simulation circuit are the same as those in the case of FIG. 5, and the difference is only the presence or absence of the resistor R1.

As shown in FIG. 3A, in the node (FarEnd), although the waveform becomes dull as the capacitance C1 increases, a monotonically increasing (monotonic) waveform is obtained. Further, as shown in FIGS. 3B to 3E, monotonic waveforms are obtained in all the capacitors C1 also in other nodes, unlike the cases of FIGS. 6B to 6E. . This is because by inserting the series-connected resistor R1, the impedance of the receiving circuit RX viewed from the receiving end Nr becomes at least the resistance value of R1 (= Z0) or more, and negative reflected waves can be suppressed. That is, assuming that the impedance of the capacitor C1 is Z _C1 and the reflection coefficient Γ at the receiving end Nr is given by Γ = (Z _C1 + R1−Z0) / (Z _C1 + R1 + Z0), suppose Z _C1 is instantaneously zero. Even so, the reflection coefficient Γ is Γ ≧ 0.

  As described above, by inserting the resistor R1 equal to the characteristic impedance Z0 of the transmission line LN in series on the receiving end Nr side, it is possible to suppress the influence of the negative reflected wave due to capacitive reflection. As a result, a monotonic waveform can be realized not only at the receiving end Nr but also within the transmission line LN. For example, a clock waveform or a strobe waveform can be branched from the node (Tap1).

  Here, the resistance value of the resistor R1 is assumed to be equal to the characteristic impedance Z0 of the transmission line LN. However, if R1 ≧ Z0 in principle, the negative reflected wave can be suppressed, and the monotonic in the transmission line LN. Can be realized. However, since the waveform becomes dull as the resistance value of R1 increases, it is desirable to set R1 = Z0. In addition, here, the explanation is given by taking the rising edge of the waveform as an example, but the same applies to the falling edge of the waveform. That is, although not shown, in the transmission line LN in FIG. 5, the non-monotonic waveform is once increased near the threshold and then decreased again, but in the transmission line LN in FIG. A monotonically decreasing waveform can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The signal transmission system according to an embodiment of the present invention is a technique that is particularly useful when applied to a high-speed transmission system that performs desired processing using signal edges, typically DDR2 SDRAM and the like. The present invention is widely applicable to all signal transmission systems in which the input part of the receiving circuit is represented by a capacity.

In the signal transmission system by one embodiment of this invention, it is the schematic which shows an example of the structure. It is a simulation circuit diagram showing the example of a structure of FIG. It is a simulation result of Drawing 2, and (a)-(e) is a wave form chart acquired at a different node, respectively. In the signal transmission system examined as a premise of the present invention, it is a schematic diagram showing an example of the configuration. FIG. 5 is a simulation circuit diagram illustrating the configuration example of FIG. 4. It is a simulation result of Drawing 5, and (a)-(e) is a wave form chart acquired at a different node, respectively. FIG. 5 is another simulation circuit diagram illustrating the configuration example of FIG. 4. It is a simulation result of Drawing 7, and (a)-(e) is a wave form chart acquired at a different node, respectively.

Explanation of symbols

TX transmission circuit RX reception circuit PG pulse generation circuit R resistance LN transmission line N node C capacitance TR transistor Near End of transmission line Far end of transmission line Far end of transmission line Tap 1-3 Voltage measurement point provided on transmission line

Claims (5)

A transmission circuit for transmitting a pulse signal;
A transmission line having a first characteristic impedance and transmitting the pulse signal from a transmitting end to a receiving end;
A receiving circuit for receiving the pulse signal transmitted to the receiving end with an equivalent capacitive input unit;
A signal transmission system comprising: a first resistor connected in series between the receiving end and the input unit and having a resistance value equal to or higher than the first characteristic impedance. The signal transmission system according to claim 1, wherein
The input unit includes a MIS transistor,
The signal transmission system, wherein the pulse signal is received by a gate of the MIS transistor. The signal transmission system according to claim 1, wherein
The signal transmission system according to claim 1, wherein a resistance value of the first resistor is equal to the first characteristic impedance. The signal transmission system according to claim 1, wherein
The transmission line is formed of one or more wiring boards,
The transmission circuit and the reception circuit are mounted on the wiring board or boards as separate LSI devices,
The signal transmission system according to claim 1, wherein the first resistor is mounted on the one or more wiring boards. The signal transmission system according to claim 1, wherein
The signal transmission system, wherein the pulse signal is a signal whose edge portion is used as a trigger.

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