JP2009164875A - Duty ratio adjustment circuit - Google Patents

Abstract

A duty ratio adjustment circuit capable of setting a desired duty ratio according to a control voltage is provided.
An input signal IN is integrated by a CR integration circuit having a time constant T10 composed of a resistor 12 and a capacitor 13 via a buffer inverter 11, and is supplied from a connection point N1 to an inverting input terminal of a comparator 30 as a signal S10. Given. The output signal OUT of the comparator 30 is integrated by the integrator 20 having a time constant T20 larger than the time constant T10, and is supplied to the non-inverting input terminal of the comparator 30 as a signal S20 corresponding to the control voltage VC. The comparator 30 outputs the output signal OUT of the ground voltage GND when the signal S10 is higher than the signal S20, and outputs the output signal OUT of the power supply voltage VDD when vice versa. By this feedback operation, the average level (that is, the duty ratio) of the output signal OUT is controlled to a value corresponding to the control voltage VC.
[Selection] Figure 1

Description

  The present invention relates to a duty ratio adjustment circuit for adjusting a duty ratio of a clock signal or the like.

FIG. 2 is a configuration diagram of a conventional duty ratio correction circuit described in Patent Document 1 below.
This duty ratio correction circuit corrects the duty ratio of the clock signal to be 50%. A buffer inverter 1 for inverting the clock input signal CKI and a first connected to the output side of the inverter 1 are provided. And a second CR integration circuit. The first CR integration circuit is composed of a resistor 2 and a capacitor 3, and the second CR integration circuit is composed of a resistor 4 and a capacitor 5. The time constant T1 of the first CR integration circuit is set to be smaller than a half cycle of the clock input signal CKI, and the time constant T2 of the second CR integration circuit is sufficiently large with respect to the cycle of the clock input signal CKI. Is set.

  The output side of the first CR integration circuit is connected to the inverting input terminal of the comparator 6, and the output side of the second CR integration circuit is connected to the non-inverting input terminal of the comparator 6. Then, the corrected clock output signal CKO is output from the comparator 6, and this clock output signal CKO is fed back to the non-inverting input terminal of the comparator 6 via the resistor 7 in order to have a hysteresis characteristic. It has become so.

  In this duty ratio correction circuit, the input clock input signal CKI is inverted by the inverter 1 and applied to the first CR integration circuit, and is applied to the inverting input terminal of the comparator 6 as a trapezoidal wave (or triangular wave). . On the other hand, since the time constant T2 is sufficiently large with respect to the cycle of the clock input signal CKI, the output of the second CR integration circuit can be regarded as a DC voltage corresponding to the duty ratio of the clock input signal CKI.

  The comparator 6 outputs a level “L” when the output of the first CR integration circuit is higher than the output of the second CR integration circuit, and outputs a level “H” in the opposite case. . Therefore, when the duty ratio of the output signal of the inverter 1 is small, the output of the second CR integration circuit is shifted to the “L” side, and the output of the first CR integration circuit is compared with a voltage close to this “L” side. The As a result, the duty ratio of the clock output signal CKO output from the comparator 6 increases. Conversely, when the duty ratio of the output signal of the inverter 1 is large, the output of the second CR integration circuit is shifted to the “H” side, and the output of the first CR integration circuit is compared at a voltage close to the “H” side. Is done. As a result, the duty ratio of the clock output signal CKO output from the comparator 6 decreases. By such an operation, the duty ratio of the clock output signal CKO approaches 50%.

Japanese Patent Laid-Open No. 10-163823

  However, the duty ratio correction circuit corrects the duty ratio of the clock signal so as to approach 50%, and cannot be adjusted to an arbitrary duty ratio.

  An object of the present invention is to provide a duty ratio adjusting circuit that can set a desired duty ratio in accordance with a control voltage.

  The present invention provides a duty ratio adjustment circuit that outputs an output signal having a desired duty ratio by controlling the duty ratio of an input signal that periodically changes between a high level and a low level in accordance with a control voltage. A first integration means for integrating a first time constant to generate a first signal, and integrating the output signal with a second time constant larger than the first time constant, A second integrating means for generating a second signal obtained by adding the control voltage; and when the level of the first signal is lower than the level of the second signal, the output signal is set to a high level and output. Comparing means for outputting the output signal at a low level when the level of the first signal is higher than the level of the second signal is provided.

  In the present invention, the first integration means for integrating the input signal that periodically changes between the high level and the low level with a first time constant to generate a first signal that approximates a triangular wave or a trapezoidal wave, and an output signal In addition to a second integration means for generating a second signal obtained by adding a control voltage to a signal obtained by integrating a signal with a second time constant larger than the first time constant, in addition to the first and second signals. Comparing means for outputting an output signal by comparing the levels is provided. With such a feedback configuration, there is an effect that the average level of the output signal is controlled to be equal to the control voltage, and the duty ratio of the output signal can be set to a desired value based on the control voltage.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a configuration diagram of a duty ratio adjustment circuit showing Embodiment 1 of the present invention.
The duty ratio adjusting circuit includes a filter 10 that generates a signal S10 obtained by integrating the input signal IN, an integrator 20 that generates a signal S20 obtained by integrating the output signal OUT with reference to the control voltage VC, and these signals S10 and S20. The comparator (CMP) 30 outputs an output signal OUT for comparison.

  The filter 10 includes, for example, a buffer inverter 11 that inverts an input signal IN, and a CR integration circuit having a time constant T10 that includes a resistor 12 and a capacitor 13 connected to the output side of the inverter 11. The signal S10 output from the connection point N1 between the resistor 12 and the capacitor 13 is applied to the inverting input terminal of the comparator 30.

  The integrator 20 is a general one using an operational amplifier (OP) 21. The integrator 20 supplies the output signal OUT of the comparator 30 to the inverting input terminal of the operational amplifier 21 via the resistor 22. A capacitor 23 is connected between the output terminal and the inverting input terminal. The control voltage VC is applied to the non-inverting input terminal of the operational amplifier 21, and the signal S20 output from the output terminal is applied to the inverting input terminal of the comparator 30. Note that the time constant T20 of the integrating circuit including the resistor 22 and the capacitor 23 is set to be sufficiently larger than the time constant T10 of the filter 10.

  The comparator 30 outputs the output signal OUT of level “L” (for example, ground voltage GND) when the level of the signal S10 applied to the inverting input terminal is higher than the signal S20 applied to the non-inverting input terminal. In the reverse case, the output signal OUT of the level “H” (for example, the power supply voltage VDD) is output.

  FIG. 3 is a signal waveform diagram showing an example of the operation of FIG. Here, a case where the control voltage VC is set to ½ of the power supply voltage VDD is shown.

  The input signal IN is inverted by the inverter 11 and then integrated by a CR integration circuit composed of a resistor 12 and a capacitor 13, and a signal S10 having a constant rising and falling time constant T10 (in the figure, simplified). Display with trapezoidal waves).

  The signal S10 is supplied to the comparator 30 and compared with the signal S20 generated by the integrator 20. If the level of the signal S10 is higher than the level of the signal S20, the output signal OUT output from the comparator 30 is “L”. Conversely, if the level of the signal S10 is lower than the level of the signal S20, the output signal OUT becomes “H”.

  The output signal OUT is supplied to the inverting input terminal of the operational amplifier 21 and one end of the capacitor 23 through the resistor 22 of the integrator 20. Thereby, the integration operation according to the time constant T20 by the resistor 22 and the capacitor 23 is performed.

  When the output signal OUT is “H” (that is, when S10 <S20), current flows into the capacitor 23 through the resistor 22, and the capacitor 23 is charged. Since a constant control voltage VC (in this case, VC = VDD / 2) is applied to the non-inverting input terminal of the operational amplifier 21, from the nature of an imaginary short (the potential difference between the two input terminals is 0). The signal S20 at the output terminal of the operational amplifier 21 gradually decreases according to the time constant T20.

  When the signal S20 decreases and becomes equal to or lower than the level of the signal S10, the output signal OUT of the comparator 30 changes from “H” to “L”. As a result, current flows from the capacitor 23 through the resistor 22 this time, and the capacitor 23 is discharged. For this reason, the signal S20 at the output terminal of the operational amplifier 21 gradually increases. At this time, since the signal S10 is increasing with the time constant T10, the level of the signal S20 does not catch up with the level of the signal S10.

  Due to the saturation of the CR integration circuit of the filter 10, the rise of the signal S10 is almost stopped, and the signal S10 starts to fall this time due to the change of the input signal IN. At this time, since the output signal OUT of the comparator 30 is “L”, the signal S20 of the integrator 20 continues to rise gradually.

  When the signal S10 decreases and becomes equal to or lower than the level of the signal S20, the output signal OUT of the comparator 30 changes from “L” to “H”. As a result, a current flows into the capacitor 23 through the resistor 22, and the capacitor 23 is charged again. For this reason, the signal S20 at the output terminal of the operational amplifier 21 gradually decreases. At this time, since the signal S10 is decreasing with the time constant T10, the level of the signal S20 does not catch up with the level of the signal S10.

  The fall of the signal S10 almost stops due to the saturation of the CR integration circuit of the filter 10, and the signal S10 starts to rise due to the change of the input signal IN. At this time, since the output signal OUT of the comparator 30 is “H”, the signal S20 of the integrator 20 continues to gradually decrease. When the signal S10 rises and exceeds the level of the signal S20, the output signal OUT of the comparator 30 changes from “H” to “L”. By such an operation of the feedback loop, the change timing of the output signal OUT of the comparator 30 is controlled.

  Here, due to the imaginary short nature of the operational amplifier 21, feedback control is performed so that the average level of the output signal OUT applied to the non-inverting input terminal of the operational amplifier 21 is equal to the control voltage VC applied to the inverting input terminal. Is done. The output signal OUT fully swings between “L” (ground voltage GND) and “H” (power supply voltage VDD), and the control voltage VC is set to ½ of the power supply voltage VDD. The duty ratio of OUT is 50%.

  As apparent from FIG. 3, the duty ratio of the output signal OUT is determined by the relative level relationship between the signal S10 and the signal S20. Further, the average level of the signal S20 rises and falls according to the control voltage VC. Therefore, in order to widen the adjustment range of the duty ratio by the control voltage VC, the time constant T10 is set so that the upper and lower sides of the trapezoidal signal S10 are almost eliminated, and the signal S20 is almost horizontal. It can be seen that the time constant T20 should be increased so that That is, the time constant T10 is set to be approximately ½ of the cycle of the input signal IN, and the time constant T20 is a value sufficiently larger than the cycle of the input signal IN (for example, 10 times or more of the cycle of the input signal IN). Should be set.

  Note that if the control voltage VC is set higher than ½ of the power supply voltage VDD, the average level of the output signal OUT becomes higher and the duty ratio becomes higher than 50%. On the contrary, if the control voltage VC is set lower than ½ of the power supply voltage VDD, the average level of the output signal OUT becomes lower and the duty ratio becomes lower than 50%.

  As described above, in the duty ratio adjusting circuit according to the first embodiment, the integrator 20 generates the signal S20 obtained by integrating the output signal OUT with reference to the control voltage VC, the signal S10 obtained by integrating the input signal IN, and this signal. A feedback configuration is employed in which the comparator 30 compares S20 with the output signal OUT. Accordingly, there is an advantage that the average level of the output signal OUT is controlled to be equal to the control voltage VC, and the duty ratio of the output signal OUT can be set to a desired value based on the control voltage VC.

  FIG. 4 is a configuration diagram of a duty ratio adjustment circuit showing Embodiment 2 of the present invention, and common elements to those in FIG. 1 are denoted by common reference numerals. This duty ratio adjustment circuit is provided with a filter 10A having a different configuration in place of the filter 10 in FIG.

  That is, the filter 10A includes a buffer inverter 11 that inverts an input signal IN, an N-channel MOS transistor (hereinafter referred to as “NMOS”) 14 that is ON / OFF controlled by an output signal of the inverter 11, and a P-channel MOS. It has a transistor (hereinafter referred to as “PMOS”) 15. The source of the NMOS 14 is connected to the ground voltage GND, and the drain is connected to the connection point N 1 via the resistor 12. One end of the capacitor 13 is connected to the connection point N1, and the other end of the capacitor 13 is connected to the ground voltage GND. On the other hand, the source of the PMOS 15 is connected to the power supply voltage VDD, and the drain is connected to the connection point N1. A signal S10A is output from the connection point N1 and is supplied to the inverting input terminal of the comparator 30. Other configurations are the same as those in FIG.

FIG. 5 is a signal waveform diagram showing an example of the operation of FIG.
In the filter 10A of the duty ratio adjusting circuit, when the input signal IN is “H”, the NMOS 14 is turned off and the PMOS 15 is turned on. As a result, the capacitor 13 is immediately charged to the power supply voltage VDD via the PMOS 15. On the other hand, when the input signal IN becomes “L”, the NMOS 14 is turned on and the PMOS 15 is turned off. Thereby, the capacitor 13 is discharged to the ground voltage GND through the resistor 12 and the NMOS 14 according to the time constant T10. Therefore, as shown in FIG. 5, the waveform of the signal S10A instantaneously rises simultaneously with the input signal IN, and when the input signal IN becomes “L”, the sawtooth waveform falls to the ground voltage GND according to the time constant T10. It becomes.

  On the other hand, the operation of the integrator 20 that generates the signal S20 obtained by integrating the output signal OUT with the control voltage VC as a reference and the comparator 30 that compares the signals S10 and S20 and outputs the output signal OUT are described in the first embodiment. As explained in. As a result, the duty ratio adjusting circuit according to the second embodiment is controlled so that the average level of the output signal OUT becomes equal to the control voltage VC as in the first embodiment, and the duty ratio of the output signal OUT is set to the control voltage VC. Can be set to a desired value. In the duty ratio adjustment circuit of the second embodiment, as shown in FIG. 5, since the integration operation for the rising edge of the input signal IN is not performed, the “H” period of the input signal IN is widened. Although the adjustment range of the duty ratio is narrowed, the rising timing of the input signal IN and the falling timing of the output signal OUT can be matched. Even in this case, as in the first embodiment, if the time constant T10 is set to be ½ of the cycle of the input signal IN and the time constant T20 is set to a value sufficiently larger than the cycle of the input signal IN, The adjustment range of the duty ratio can be widened.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) The configuration of the filter 10 and the integrator 20 of the first embodiment is an example, and the present invention is not limited to this. For example, instead of the filter 10, two constant current sources and a capacitor are used. When the input signal IN is “H”, the capacitor is charged via the first constant current source, and the input signal IN is “L”. In some cases, the circuit may be such that the capacitor is discharged via the second constant current source. Thereby, the signal S10 whose level changes linearly can be obtained.
(B) The resistor 12 in the filter 10A of the second embodiment may be provided between the drain of the NMOS 15 and the connection point N1. As a result, a signal S10 having a sawtooth waveform opposite to that shown in FIG. 5 is obtained at the rise and fall, and the “H” period of the input signal IN is narrowed, and the fall and output of the input signal IN are output. The rising timing of the signal OUT can be matched.

1 is a configuration diagram of a duty ratio adjustment circuit showing Embodiment 1 of the present invention. FIG. It is a block diagram of the conventional duty ratio correction circuit. It is a signal waveform diagram which shows an example of the operation | movement of FIG. It is a block diagram of the duty ratio adjustment circuit which shows Example 2 of this invention. It is a signal waveform diagram which shows an example of the operation | movement of FIG.

Explanation of symbols

10, 10A Filter 11 Inverter 12, 22 Resistor 13, 23 Capacitor 14 NMOS
15 PMOS
20 integrator 21 operational amplifier 30 comparator

Claims (4)

A duty ratio adjustment circuit for controlling the duty ratio of an input signal that periodically changes between a high level and a low level according to a control voltage and outputting an output signal having a desired duty ratio,
First integrating means for integrating the input signal with a first time constant to generate a first signal;
Integrating the output signal with a second time constant larger than the first time constant, and generating a second signal obtained by adding the control voltage to the integrated signal;
When the level of the first signal is lower than the level of the second signal, the output signal is output at a high level, and when the level of the first signal is higher than the level of the second signal Comparing means for outputting the output signal at a low level;
A duty ratio adjustment circuit comprising: A duty ratio adjustment circuit for controlling the duty ratio of an input signal that periodically changes between a high level and a low level according to a control voltage and outputting an output signal having a desired duty ratio,
A first signal that integrates the input signal with a first time constant according to a change in one of rising or falling of the input signal, and immediately generates a first signal that changes according to the input signal at other changes. One integration means;
Integrating the output signal with a second time constant larger than the first time constant, and generating a second signal obtained by adding the control voltage to the integrated signal;
When the level of the first signal is lower than the level of the second signal, the output signal is output at a high level, and when the level of the first signal is higher than the level of the second signal Comparing means for outputting the output signal at a low level;
A duty ratio adjustment circuit comprising:   In the second integrating means, the control voltage is applied to the non-inverting input terminal, the output signal is applied to the inverting input terminal via a resistor, and a capacitor is connected between the output terminal and the inverting input terminal. 3. The duty ratio adjusting circuit according to claim 1, wherein the duty ratio adjusting circuit comprises an operational amplifier that outputs the second signal from the output terminal.   The first time constant is set to a value that is approximately a half of the period of the input signal, and the second time constant is set to a value that is 10 times or more the period of the input signal. Item 4. The duty ratio adjustment circuit according to item 1, 2 or 3.

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