JP2009148000A - Power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply circuit which reduces cost and power consumption. <P>SOLUTION: A comparator COMP2 compares a divided voltage VDIV1 of a power supply voltage VCC with a predetermined Vref (reference voltage). If the divided voltage VDIV1 of a power supply voltage VCC is larger than the reference voltage Vref as a result of comparison, a determination is made that a charge pump circuit 200a is in overcapacity, and a signal IVPPHIDETP of L level is output to reduce the output of an AND element A1 to L level. More specifically, an inverted signal ICLK of clock signal is prevented from being input to a capacitor C1 on the last stage thus inactivating a buffer of a clock on the last stage. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power supply circuit, and more particularly to a technique for reducing cost and power consumption.

  Conventionally, a nonvolatile memory such as a flash memory or an EEPROM is used for a microcomputer or the like. For example, in a flash memory, a tunnel effect or channel hot electrons are used when writing or erasing a memory cell. At that time, a high voltage of about 5 to 10 V is required, but this high voltage is generally generated by a booster circuit such as a charge pump inside the flash memory module (for example, Patent Documents 1 and 2). .

  Further, as a booster circuit, a plurality of MOS transistors whose gates are diode-connected to their drains are connected in series, and a clock signal and an inverted signal of the clock signal are connected to a plurality of capacitors respectively connected to nodes between the MOS transistors. In many cases, a so-called Dickson type charge pump circuit or an improved version thereof is used (for example, Non-Patent Documents 1 to 4).

  In the Dickson type charge pump circuit, the voltage amplification value Vga per MOS transistor becomes Vga = VCC−Vth using the input power supply voltage VCC and the threshold voltage Vth of the MOS transistor. Therefore, the maximum value VPPmax of the output voltage VPP is VPPmax = (N + 1) × (VCC−Vth) by further using the pump stage number N.

JP 2001-157438 A JP 2003-88103 A JOHN F. DICKSON, "On-Chip High-Voltage Generation in Integrated Circuits Using an Improved Multiplier Technique", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-11, NO. 3, pp.374-378, JUNE 1976 Toru Tanzawa, and Tomoharu Tanaka, "A Dynsmic Analysis of the Dicson Charge Pump Circuit", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 8, pp.1231-1240, JUNE 1976 Kikuzo Sawada, Yoshikazu Sugawara, and Shoichi Masui, "An On-Chip High-Voltage Circuit for EEPROMs with a Power Supply Voltage below 2V", 1995 Symp. On VLSI Circuits Dig. Of Tech. Papers, pp.75-76 Jongshin Shin, In-Young Chung, Yung June Park, and Hong Shick Min, "A New Charge Pump Without Degration In Threshold Voltage Due to Body Effect", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, pp .1227-1230, Auguest 2000

  When designing a Dickson type charge pump circuit in which the operating range of the power supply voltage VCC extends over a wide range (eg, VCC = 2 to 5V), the voltage lower limit (VCC = 2V) is satisfied so that the supply capability is satisfied even when the power supply voltage VCC is the lower limit. The pump size is determined by the capacity. However, if this circuit is used on the higher power supply voltage side (VCC = 5V), the supply capacity becomes excessive, and various problems occur.

  The first problem is that the ripple of the voltage VPP output from the charge pump circuit increases on the high voltage side of the power supply voltage VCC. In order to satisfy the necessary supply capability even on the low voltage side of the power supply voltage VCC, it is necessary to increase the CAP capacity (C) of each stage of the charge pump or increase the operating frequency (f) (i = CVf). . However, if this is used on the high voltage side as it is, the capacity becomes excessive and the ripple of the output voltage VPP becomes large. In order to obtain a stable voltage VPP by reducing ripple, it is necessary to increase the decoupling capacitance CAP given to the voltage VPP. However, when a large-capacity decoupling capacitor CAP is mounted, the module area increases and the chip cost increases.

  The second problem is that power consumption increases on the high voltage side of the power supply voltage VCC. That is, in order to input a low power supply voltage VCC and output a high voltage VPP by pumping, it is necessary to increase the number of pump stages N. For example, in order to realize VPP = 10V with VCC = 2V, Vth = 0.3V, N> 10 ÷ (2-0.3) −1 requires five or more stages. However, in order to realize VPP = 10V with VCC = 5V, Vth = 0.3V, N> 10 ÷ (5-0.3) −1, so that two stages are sufficient. As the number of pump stages N increases, the current efficiency of the charge pump decreases and the power consumption increases. Therefore, if the number of stages of the charge pump is set to 5 on the basis of the low voltage side, on the high voltage side, although only 2 stages of pumps are required, the 5 stages of pumps are operated. An unnecessary soot current loss will occur.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a power supply circuit capable of reducing cost and power consumption.

  In one embodiment of the present invention, the comparator compares the divided power supply voltage with a predetermined reference voltage. As a result of the comparison, when the divided voltage of the power supply voltage is larger than a predetermined reference voltage, it is determined that the charge pump circuit is in an overcapacity state, and an L level signal is output, whereby the output of the AND element is reduced to L Level. In other words, the pump of the final stage is deactivated by not inputting the inverted signal of the clock signal to the capacity of the final stage.

  In the present invention, the current required for charging and discharging the deactivated capacity can be reduced, so that power consumption can be reduced. In addition, since the deactivated capacitor and the MOS transistor function as an RC filter, output voltage ripple can be reduced. Therefore, it is possible to reduce a large decoupling capacity for reducing the ripple, and it is possible to prevent an increase in chip cost due to an increase in module area.

<Basic technology>
FIG. 1 is a schematic block diagram showing the configuration of a microcomputer with built-in flash memory according to the basic technology.

  The flash memory module 1 transmits / receives data to / from the microcomputer 7 via a data bus, and is controlled by a control signal from the microcomputer 7.

  The flash memory module 1 mainly includes a memory array 4, a decoder 3, a sense amplifier 8, a control circuit 6, a power supply circuit 5, and a power supply switching circuit 2.

  Hereinafter, the read path of the flash memory module 1 will be described.

  A sense amplifier 8 is connected to the memory cell array 4 including a plurality of memory cells, and data is read from the memory cells by the sense amplifier 8. At the time of reading, one memory cell is selected by a word line and a column selection line (both not shown) according to an address signal input to the flash memory module 1, and is supplied to the sense amplifier 8 via a bit line (not shown). Connected. When a certain voltage is applied to the selected word line and the current flowing through the memory cell connected to the word line is larger or smaller than a certain value, the information stored in the memory cell is 0 or 1 Determine if it exists. At this time, if the threshold voltage Vth of the memory cell is higher than the applied word line voltage, it is determined that the current does not easily flow through the memory cell, so that the threshold voltage Vth is higher than the applied word line voltage. If it is low, current is likely to flow.

  FIG. 2 is a circuit diagram showing a charge pump circuit main body 100 which is a main body of the Dickson type charge pump circuit according to the basic technology. The charge pump circuit main body 100 in FIG. 2 is built in the power supply circuit 5 in FIG. 1 and functions as a booster circuit.

  As shown in FIG. 2, in the charge pump circuit main body 100, a plurality of (here, five) MOS transistors TR1 whose gates are diode-connected to the drains are connected in series. The diode-connected MOS transistor TR1 can be configured by a PMOS, but here, an NMOS will be described as an example. The clock signal CLK and the inverted signal ICLK of the clock signal are alternately input via the buffer B1 to a plurality of (here, N = 4 stages) capacitors C1 respectively connected to the node between the NMOS transistors TR1. . In the charge pump circuit main body 100, the power supply voltage VCC is input, pumped, and the voltage VPP is output.

  FIG. 3 is a circuit diagram showing a charge pump circuit 200 to which the charge pump circuit main body 100 of FIG. 2 is applied. In the charge pump circuit 200, the divided voltage of the output voltage VPP is compared with a predetermined Vref (reference voltage) by the comparator COMP1. As a result of the comparison, when the divided voltage VPP is larger than the reference voltage Vref, the supply of the clock signal CLK is stopped in all the pumps by stopping the ring oscillator RO that generates the clock signal CLK. ing. As a result, it is possible to perform control such that the voltage VPP is kept constant at a desired level equal to or lower than the maximum value VPPmax. The voltage VPP is provided with a large decoupling capacitor CAP in order to reduce ripples and stabilize the VPP voltage.

  FIG. 4 is a circuit diagram showing a charge pump circuit body 101 which is an improved version of the charge pump circuit body 100 of FIG. In the charge pump circuit body 101 of FIG. 4, the NMOS transfer TF1 whose gate is diode-connected to the drain corresponds to the NMOS transistor TR1 whose gate is diode-connected to the drain of the charge pump circuit body 100 of FIG. The NMOS transfers TF1 and TF2 are elements in which two NMOS transistors are combined and arranged such that the gates are arranged on opposite sides.

  As shown in FIG. 4, in the charge pump circuit body 101, one gate is connected between the NMOS transfer TF1 whose diode is connected to the drain and the gate and drain of the NMOS transfer TF2, and the gate is connected to the NMOS transfer TF1 ( A plurality of sets (here, 5 sets) of NMOS transistors TR2 connected to the source of TF2) are connected in series. The clock signal CLKP and the inverted signal ICLKP of the clock signal are alternately input to the plurality of capacitors C1 respectively connected to the nodes between the NMOS transfer TF1 (TF2) via the buffer B1, and also to the gate of the NMOS transfer TF2. The clock signal CLKG whose H level period is shorter than the clock signal CLKP and the inverted signal ICLKG of the clock signal are alternately input to the plurality of capacitors C2 connected thereto through the buffer B2. In the charge pump circuit main body 101, similarly to the charge pump circuit main body 100, the power supply voltage VCC is input, pumped, and the voltage VPP is output.

  FIG. 5 is an example of a circuit diagram illustrating a configuration of a clock generation circuit CLKGEN that generates clock signals CLKP and CLKG from a clock signal CLK. FIG. 6 is a timing chart showing clock signals CLKP and CLKG generated by the clock generation circuit CLKGEN of FIG.

  As shown in FIG. 5, the clock signal CLKD is generated by delaying the clock signal CLK by a delay circuit Delay for a predetermined time. The clock signal CLKP is generated by inputting the clock signals CLK and CLKD to the NOR element and inverting the output by an inverter. The clock signal CLKG is generated by inputting the clock signals CLK and CLKD to the NAND element and inverting the output by an inverter. Thereby, as shown in FIG. 6, in the clock signal CLKG, the H level period can be made shorter than that of the clock signal CLKP.

  FIG. 7 is a circuit diagram showing a charge pump circuit 201 to which the charge pump circuit main body 101 of FIG. 4 is applied. In the charge pump circuit 201, similarly to the charge pump circuit 200, the divided voltage of the output voltage VPP is compared with a predetermined Vref voltage (reference voltage) by the comparator COMP1. As a result of the comparison, when the divided voltage VPP is larger than the reference voltage Vref, the supply of the clock signal CLK is stopped in all the pumps by stopping the ring oscillator RO that generates the clock signal CLK. (That is, generation of clock signals CLKP and CLKG by the clock generation circuit CLKGEN is stopped). As a result, it is possible to perform control such that the voltage VPP is kept constant at a desired level equal to or lower than the maximum value VPPmax. The voltage VPP is provided with a large decoupling capacitor CAP in order to reduce ripples and stabilize the VPP voltage.

  In FIG. 7, for convenience of the following description, four nodes between five NMOS transfer TF1 (TF2) are designated as nodes NODE1 to NODE4 from the input side to the output side. The gates of the five NMOS transfers TF2 are gates GX1 to GX5 from the input side to the output side.

  FIG. 8 is an enlarged view of the vicinity of nodes NODE2 to NODE4 and gates GX3 to GX4 in FIG. FIG. 9 is a timing chart showing potential changes of the nodes NODE2 to NODE4 and the gates GX3 to GX4 according to the potential changes of the clock signals CLKP and CLKG. In FIG. 9, a period a corresponds to the H level period of the clock signal CLKP, a period b corresponds to the H level period of the clock signal CLKG, and a period c corresponds to the L level period of the clock signal CLKP. It corresponds. Hereinafter, with reference to FIG. 9, the potential change of each part of FIG. 8 will be described.

  When the clock CLKP rises at the beginning of the period a, the potential of the node NODE3 rises due to the coupling of the capacitor C1. Thereafter, with a slight delay, when the clock CLKG rises at the beginning of the period b, the potential of the gate GX4 rises due to the coupling of the capacitor C2. During a period in which the potential of the gate GX4 is sufficiently higher than the potential of the node NODE3, the NMOS transfer TF2 is turned on, and current flows from the node NODE3 toward the node NODE4. Therefore, the potential of the node NODE3 decreases and the potential of the node NODE4 increases. To do. In this way, current flows sequentially from the input side to the output side, so that the output potential VPP increases.

  When the clock CLKG falls at the end of the period b, the potential of the gate GX4 falls due to the coupling of the capacitor C2. When the potential of the gate GX4 becomes lower than the potential of the node NODE3, the NMOS transfer TF2 is turned off and no current flows. After that, when the clock CLKP falls at the end of the period a, the potential of the node NODE3 falls due to the coupling of the capacitor C1. At this time, since the NMOS transfer TF2 is already in the OFF state, no current flows backward from the node NODE4 to the node NODE3. In other words, by making the H level period shorter than the clock signal CLKP in the clock signal CLKG, it is possible to prevent the backflow of current from the output side to the input side.

  At the beginning of the period c, the potential of the node NODE4 rises. The charge stored in the node NODE4 flows to the output side, but since the node NODE4 is also connected to the gate of the NMOS transistor TR2, the NMOS transistor TR2 is turned on, and in the period c, the potential of the gate GX4 is changed to the node Precharged to the potential of NODE3.

  That is, in the charge pump circuit 201 of FIGS. 7 to 8, when the power supply voltage VCC of the clock signals CLKP and CLKG is relatively low, by boosting the gates GX1 to GX5 of the NMOS transfer TF2 with the clock signal CLKG, The current efficiency is improved.

<Embodiment 1>
The charge pump circuits 101 and 201 according to the basic technology are characterized in that the supply of the clock signal CLK is stopped in all the pumps in accordance with the output voltage VPP.

  On the other hand, the charge pump circuit according to the first embodiment is characterized in that, in addition to this, the supply of the clock signal CLK is stopped in the clock buffers in some stages in accordance with the input power supply voltage VCC. Is.

  FIG. 10 is a circuit diagram showing the charge pump circuit 200a according to the present embodiment. The charge pump circuit 200a shown in FIG. 10 stops the supply of the inverted signal ICLK of the clock signal to the final stage pump according to the input power supply voltage VCC in the charge pump circuit 200 shown in FIG. It is. 10, elements similar to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted here.

  The charge pump circuit 200a of FIG. 10 is different from the charge pump circuit 200 of FIG. 3 in that an AND element A1 is provided in the final stage pump instead of the buffer B1, and the inverted signal ICLK of the clock signal is supplied to one input terminal. The signal IVPPHIDETP output from the comparator COMP2 is input to each of the input terminals. The comparator COMP2 compares the divided voltage VDIV1 of the power supply voltage VCC with a predetermined Vref voltage (reference voltage). As a result of the comparison, if the divided voltage VDIV1 of the power supply voltage VCC is larger than the reference voltage Vref, it is determined that the charge pump circuit 200a is in an overcapacity state, and outputs an L level signal IVPPHIDETP, whereby the AND element A1. Is set to L level.

  As described above, when the divided voltage VDIV1 of the input power supply voltage VCC is larger than the predetermined Vref voltage, the charge pump circuit 200a according to the present embodiment supplies the inverted signal ICLK of the clock signal to the capacitor C1 at the final stage. By not inputting, the final stage pump is deactivated.

  Accordingly, the current required for charging / discharging the deactivated capacitor C1 can be reduced, so that power consumption can be reduced.

  In the final stage pump, the deactivated capacitor C1 and the NMOS transistor TR1 function as an RC filter, so that the ripple of the voltage VPP can be reduced. Therefore, it is possible to reduce the large-capacity decoupling capacitance CAP, and it is possible to prevent an increase in chip cost due to an increase in module area.

  That is, according to the charge pump circuit 200a according to the present embodiment, it is possible to provide the power supply circuit 5 capable of reducing cost and power consumption.

  In the above description, the case where the input of the inverted signal ICLK of the clock signal to the capacitor C1 is stopped and deactivated only in the buffer of the clock of the last stage has been described. However, not only the buffer of one clock of the final stage, but also the buffer of one clock of another stage may be deactivated, and the buffer of multiple clocks may be deactivated, not limited to the buffer of one clock. Also good. That is, it is only necessary to deactivate the clock buffers of some stages so that the charge pump circuit 200a does not have excessive capacity.

<Embodiment 2>
FIG. 11 is a circuit diagram showing the charge pump circuit 201a according to the second embodiment. The charge pump circuit 201a of FIG. 11 stops supplying the inverted signals ICLKP and ICLKG of the clock signal to the final stage pump in accordance with the input power supply voltage VCC in the charge pump circuit 201 of FIG. To do. 11, elements similar to those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted here.

  The charge pump circuit 201a of FIG. 11 is different from the charge pump circuit 201 of FIG. 7 in that an AND element A1 is provided instead of the buffer B1 in the final stage pump, and the inverted signal ICLKP of the clock signal is supplied to one input terminal. The signal IVPPHIDETP output from the comparator COMP2 is input to the input terminal, and an AND element A2 is provided instead of the buffer B2, and the inverted signal ICLKG of the clock signal is provided to one input terminal, and the comparator COMP3 is provided to the other input terminal. Are input with signals IVPPHIDETG output from. The comparators COMP2 and COMP3 compare the divided voltage of the power supply voltage VCC with a predetermined Vref voltage (reference voltage) Vref. As a result of the comparison, when the divided voltages VDIV1 and VDIV2 of the power supply voltage VCC are larger than the reference voltage Vref, it is determined that the charge pump circuit 201a is in an excessive capacity state, and outputs L level signals IVPPHIDETP and IVPHIDETG The outputs of the AND elements A1 and A2 are set to L level.

  The divided voltage VDIV1 of the power supply voltage VCC input to the comparator COMP2 and the divided voltage VDIV2 of the power supply voltage VCC input to the comparator COMP3 may be the same voltage or different.

  As described above, when the input power supply voltage VCC is higher than the predetermined reference voltage, the charge pump circuit 201a according to the present embodiment supplies the inverted signals ICLKP and ICLKG of the clock signal to the capacitors C1 and C2 in the final stage. By not inputting, the final stage pump is deactivated.

  Therefore, the current required for charging / discharging the deactivated capacitors C1 and C2 can be reduced, so that power consumption can be reduced.

  In the final stage pump, the deactivated capacitor C1 and the NMOS transfer TF1 function as an RC filter, so that the ripple of the voltage VPP can be reduced. Therefore, it is possible to reduce the large-capacity decoupling capacitance CAP, and it is possible to prevent an increase in chip cost due to an increase in module area.

  That is, according to the charge pump circuit 201a according to the present embodiment, it is possible to provide the power supply circuit 5 capable of reducing cost and power consumption.

  In the above description, the case where the input of the inversion signals ICLKP and ICLKG of the clock signal to the capacitors C1 and C2 is stopped and inactivated only in the buffer of one clock of the final stage has been described. However, not only the buffer of one clock of the final stage, but also the buffer of one clock of another stage may be deactivated, and the buffer of multiple clocks may be deactivated, not limited to the buffer of one clock. Also good. That is, it is only necessary to deactivate the clock buffers of some stages so that the charge pump circuit 201a does not have excessive capacity.

  In the above description, the case where both the input of the inverted signal ICLKP of the clock signal to the capacitor C1 and the input of the inverted signal ICLKG of the clock signal to the capacitor C2 are stopped when the pump is deactivated has been described. The input of only one of the signals may be stopped without being limited to both. FIG. 12 shows the pumping capability, that is, the current when the signal IVPPHIDETP input to the AND element A1 and the signal IVPPHIDETG input to the AND element A2 are at the H level and the L level, respectively (four states 1 to 4). It is the figure which showed an example of supply capability. That is, it is only necessary to perform control for appropriately selecting one of the states 2 to 4 according to the required current supply capability.

It is a schematic block diagram which shows the structure of the microcomputer with built-in flash memory which concerns on basic technology. It is a circuit diagram which shows the main body of the charge pump circuit which concerns on basic technology. It is a circuit diagram which shows the charge pump circuit which concerns on basic technology. It is a circuit diagram which shows the improved type of the main body of the charge pump circuit which concerns on basic technology. It is a circuit diagram which shows the structure of the clock generation circuit CLKGEN which produces | generates clock signal CLKP, CLKG from the clock signal CLK in the improved type of the main body of the charge pump circuit which concerns on basic technology. 7 is a timing chart showing clock signals CLKP and CLKG generated by a clock generation circuit CLKGEN in an improved type of charge pump circuit according to the basic technology. It is a circuit diagram which shows the improved type of the charge pump circuit which concerns on basic technology. It is an enlarged circuit diagram which shows the improved type of the charge pump circuit which concerns on basic technology. 7 is a timing chart showing potential changes of nodes NODE2 to NODE4 and gates GX3 to GX4 in response to potential changes of clock signals CLKP and CLKG in the improved charge pump circuit according to the basic technology. 1 is a circuit diagram showing a charge pump circuit according to a first embodiment. FIG. 5 is a circuit diagram showing a charge pump circuit according to a second embodiment. In the charge pump circuit according to the second embodiment, it is a diagram showing the correspondence between the signal input to the AND element and the current supply capability.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Flash memory module, 2 Power supply switching circuit, 3 Decoder, 4 Memory array, 5 Power supply circuit, 6 Control circuit, 7 Microcomputer, 8 Sense amplifier, 100a, 101a Charge pump circuit main body, 200a, 201a Charge pump circuit, A AND element , B buffer, C, CAP capacity, CLKGEN clock generation circuit, COMP comparator, Delay delay circuit, RO ring oscillator, TF NMOS transfer, TR NMOS transistor.

Claims (3)

A charge pump in which a plurality of MOS transistors whose gates are diode-connected to the drain are connected in series, and a clock signal and an inverted signal of the clock signal are alternately input to a plurality of capacitors respectively connected to nodes between the MOS transistors A power supply circuit comprising a circuit,
A power supply circuit that does not allow the clock signal or the inverted signal to be input to some of the plurality of capacitors when a voltage input to the charge pump circuit is higher than a predetermined reference voltage. A set of a MOS transfer in which one gate is diode-connected to the drain and a MOS transistor connected between the other gate and the drain of the MOS transfer is connected in a plurality of stages in series, and each node between the MOS transfers is connected to each node. The first clock signal and the inverted signal of the first clock signal are alternately input to the plurality of first capacitors connected, and the second capacitor connected to the other gate of the MOS transfer is connected to the second capacitor. A power supply circuit including a charge pump circuit that alternately inputs a second clock signal having an H level period shorter than one clock signal and an inverted signal of the second clock signal,
When the voltage input to the charge pump circuit is larger than a predetermined reference voltage, the first or second clock signal or the inverted signal is supplied to a part of the plurality of first capacitors or second capacitors. Power supply circuit that does not input. The power supply circuit according to claim 1 or 2,
The part of the capacitance is a power supply circuit which is a capacitance arranged at the last stage from the input side to the output side.

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