JP2009038240A - Placement and wiring method for semiconductor integrated circuit device - Google Patents

Abstract

To solve simultaneously problems such as unconnected signal wiring and timing failure and voltage drop in power wiring.
According to one aspect of the present invention, there is provided a method for arranging and wiring a semiconductor integrated circuit device, wherein a power supply wiring is wired so that power to cells arranged based on a netlist is supplied through at least two different paths. A wiring step (ST12), a cell placement step (ST13) in which a plurality of cells are placed, and a signal in which signal wiring between cells placed in ST13 is wired in the same wiring layer as the initial power supply wiring routed in ST12 In the wiring step (ST14), when the signal wiring is not connected or the wiring is short-circuited in ST14, or when the timing violation occurs in the signal wiring, the initial power supply arranged in the vicinity of the problematic signal wiring There is a wiring correction step (ST15) in which the wiring is deleted within the allowable voltage drop and the signal wiring in question is rewired.
[Selection] Figure 1

Description

  The present invention relates to a placement and routing method for a semiconductor integrated circuit device having multilayer wiring.

  In semiconductor integrated circuit devices in recent years, voltage increases due to an increase in current consumption due to higher functionality, larger scale, and higher speed of mounted systems, and higher wiring resistance due to miniaturization of metal wiring processes. Descent is more likely to occur. Since the voltage drop lowers the operation speed of the circuit and causes a phenomenon that the performance and malfunction of the integrated circuit device are caused, measures have been conventionally taken so as not to cause a voltage drop.

  In order to prevent a voltage drop under the determined current consumption conditions, it is important to reduce the resistance of the power supply wiring (see, for example, “Patent Document 1”). For this reason, conventionally, it has been often performed to increase the number of power supply wires or increase the number of power supply wires as much as possible. However, on the other hand, wiring resources in the integrated circuit device are used not only for power supply wiring but also for signal wiring between cells. Increasing the resource ratio in order to reduce the resistance of the power supply wiring causes problems such as wiring congestion due to insufficient resources in the signal wiring, and timing violation due to unconnected or shorted wiring, or detour wiring. For this reason, conventionally, a method has been employed in which current consumption is estimated, the necessary number of power supplies that do not cause a voltage drop problem is calculated, and wiring resources are appropriately allocated to power supply wiring and signal wiring for layout.

However, in such a conventional semiconductor integrated circuit device placement and routing method, layout information is used when a local voltage drop that can be seen after actual layout occurs or the value of current consumption at the time of estimation is small. If it is found by verification, it will be necessary to add power supply wiring, which will cause a backlash in the design process and the design man-hour will increase significantly, resulting in a longer development period and, consequently, an increase in development cost. There was a problem. In the future, with the further miniaturization of the semiconductor manufacturing process, it is inevitable that the power supply voltage will become lower, and it is assumed that the problem of voltage drop will become increasingly important.
JP 2004-363294 A

  The present invention provides a placement and wiring method for a semiconductor integrated circuit device that can simultaneously solve problems such as unconnected signal wiring and timing failure and voltage drop in power supply wiring.

  According to one aspect of the present invention, a power supply wiring step in which power supply wiring is routed so that power to cells arranged based on a netlist is supplied through at least two different paths, and the plurality of cells A cell placement step in which the signal wiring between the cells arranged in the cell placement step is wired in the same wiring layer as the initial power supply wiring routed in the power supply wiring step, and the signal When the signal wiring is not connected or a wiring short circuit occurs in a wiring step, or when a timing violation occurs in the signal wiring, the initial power supply wiring arranged in the vicinity of the signal wiring in question is A semiconductor having a wiring correction step in which the signal wiring in question is re-wired after being deleted within an allowable voltage drop Placement and routing method of the AND circuit device is provided.

  According to the present invention, backtracking in the design process can be greatly suppressed, so that the development period can be shortened and the development cost can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a flowchart showing a placement and routing method for a semiconductor integrated circuit device according to Embodiment 1 of the present invention. Here, the portion related to the layout design that generates the layout data based on the net list generated by the logical design is mainly shown.

  The placement and routing method for a semiconductor integrated circuit device according to the first embodiment of the present invention includes a step of generating a floor plan (ST11), a step of routing initial power supply wiring (ST12), and a plurality of cells based on a netlist. Step (ST13), Step of wiring signal wiring between cells (ST14), Step of correcting power supply wiring and signal wiring based on voltage drop (ST15), Step of outputting layout information (ST16) Yes.

  In the floor plan step (ST11), the pad arrangement and the like are determined using the floor plan module.

  In the power supply wiring step (ST12), the initial power supply wiring is drawn to the third wiring layer to the seventh wiring layer by the power supply wiring module. At this time, a larger number of power supply wires are provided in advance than is necessary in order to prevent a voltage drop from exceeding a power supply voltage range (for example, 3 V ± 0.15 V) allowed in the arranged cell. That is, the initial power supply wiring is formed so that power to the cell to be arranged is supplied through at least two different paths. A specific configuration of the initial power supply wiring will be described later with reference to FIGS.

  In the cell placement step (ST13), cells are placed by the cell placement module based on the net list.

  In the signal wiring step (ST14), the signal wiring between the cells arranged in ST13 is wired to the third wiring layer to the seventh wiring layer based on the net list by the wiring module. Here, when wiring congestion occurs due to a shortage of signal wiring resources, timing violation occurs due to unconnected signal wiring, wiring short-circuiting, and detour wiring.

  In the wiring correction step (ST15), when the signal wiring is not connected or a wiring short-circuit occurs in ST14, or when a timing violation occurs in the signal wiring, the initial stage arranged near the signal wiring in question The power supply wiring is deleted within the allowable voltage drop (for example, 5% or less), and the signal wiring in question is rewired. A specific detailed flow for dealing with this problem occurrence location (hereinafter referred to as “violation location”) will be described later with reference to FIG.

  In the information output step (ST16), the layout information created in ST11 to ST15 is output by the information output module, and the layout design process is completed.

FIG. 2 is a flowchart showing a wiring correction step (ST15) in the placement and routing method of the semiconductor integrated circuit device according to the first embodiment of the present invention.
The wiring correction step (ST15) in the placement and routing method for a semiconductor integrated circuit device according to the first embodiment of the present invention includes the step of extracting a violation location (ST21), the step of extracting a deletion candidate location (ST22), and the voltage of the power supply wiring A step of calculating a drop (ST23), a step of determining deletion of the initial power supply wiring based on the voltage drop (ST24), a step of deleting the initial power supply wiring (ST25), and a step of rewiring the signal wiring (ST26) I have.

  In the violation location extraction step (ST21), a plurality of violation locations are detected and specified by the wiring correction detection module. The following ST22 to ST25 are repeatedly executed for these identified violation points, and the shortage of signal wiring resources is solved.

  In the candidate extraction step (ST22), in order to eliminate the shortage of signal wiring resources, the initial power supply wiring is determined based on the coordinate information and connection information of the initial power supply wiring existing in the vicinity of the violation location identified in ST21. Are deleted by the power supply wiring deletion candidate extraction module.

  In the voltage drop calculation step (ST23), the voltage drop calculation module calculates how much voltage drop occurs in the power supply wiring when the deletion candidate part extracted in ST22 is deleted.

  In the deletion determination step (ST24), deletion of the initial power supply wiring is determined based on the result calculated in ST23. That is, if there is no problem even if the deletion candidate part is deleted (“yes”, voltage drop ≦ 5%), the process proceeds to ST25, and if the deletion candidate part is deleted, the voltage drop causes a large problem (“ no ″, voltage drop> 5%), the actual deletion is not performed, and the process proceeds to ST22 in order to process the next violation.

  In the power supply wiring deletion step (ST25), the deletion candidate portion extracted in ST22 is actually deleted from the initial power supply wiring.

  In this manner, after repeating ST22 to ST25 and processing is completed for all violations, the signal wiring is rewired by the rewiring module based on the updated power wiring in the rewiring step (ST26), and the wiring is performed in ST14. Corrected signal wiring is corrected.

  Next, the structure of the initial power supply wiring formed in the power supply wiring step (ST12) will be described.

  FIG. 3 is a layout diagram showing initial power supply wiring in the layout wiring method of the semiconductor integrated circuit device according to the first embodiment of the present invention. Here, as an example, the initial power supply wiring when the power supply wiring and the signal wiring are wired in the third wiring layer to the seventh wiring layer is shown. Further, the area ratio of the power supply wiring in each wiring layer is 25%.

  The initial power supply wiring in the method of arranging and wiring a semiconductor integrated circuit device according to the first embodiment of the present invention includes VDD wiring 17a and VSS wiring 17b arranged in the seventh wiring layer, and VDD wiring 16a arranged in the sixth wiring layer. VSS wiring 16b, VDD wiring 15a and VSS wiring 15b arranged in the fifth wiring layer, VDD wiring 14a and VSS wiring 14b arranged in the fourth wiring layer, VDD wiring 13a and VSS wiring arranged in the third wiring layer 13b and contact plugs 18a to 18d for connecting each wiring layer.

  The four dot-dash lines shown in FIG. 3 represent the positions of the cross sections shown in FIGS. 3 is a layout diagram (plan view), the lower-layer VDD wiring 13a, VSS wiring 13b, and contact plug 13d are not shown.

  The VDD wirings 13a to 17a are used for supplying a power supply potential (VDD = 3V), and the VSS wirings 13b to 17b are used for supplying a ground potential (VSS = 0V).

  The VDD wiring 17a and the VSS wiring 17b extend in the first direction (the vertical direction in the drawing of FIG. 3), and extend along the second direction (the horizontal direction of the drawing in FIG. 3) orthogonal to the first direction. They are alternately arranged at a pitch d.

  The VDD wiring 16a and the VSS wiring 16b extend in the second direction, and are alternately arranged at a pitch d along the first direction.

  The VDD wiring 15a and the VSS wiring 15b extend in the first direction and are alternately arranged at a pitch d along the second direction. Further, the VDD wiring 15a and the VSS wiring 15b are arranged with a d / 2 shift from the VDD wiring 17a and the VSS wiring 17b along the second direction.

  The VDD wiring 14a and the VSS wiring 14b extend in the second direction, and are alternately arranged at a pitch d along the first direction. Further, the VDD wiring 14a and the VSS wiring 14b are arranged with a d / 2 shift from the VDD wiring 16a and the VSS wiring 16b along the first direction.

  The VDD wiring 13a and the VSS wiring 13b extend in the first direction and are alternately arranged at a pitch d along the second direction. Further, the VDD wiring 13a and the VSS wiring 13b are disposed with a d / 2 shift along the second direction from the VDD wiring 15a and the VSS wiring 15b.

  The area ratio of the initial power supply wiring, that is, the resource ratio of the initial power supply wiring and the signal wiring is adjusted by the pitch d and the wiring width w of the power supply wiring. Here, as an example, the wiring width w of the initial power supply wiring is set to ¼ of the pitch d in order to set the area ratio of the initial power supply wiring to 25%.

  The VDD wiring 17a and the VSS wiring 17b are arranged in the uppermost wiring layer and are connected to a plurality of power supply pads (not shown) arranged at the peripheral edge of the chip in the floor plan step (ST11).

  The contact plug 18a connecting the seventh wiring layer and the sixth wiring layer is formed at the intersection position between the VDD wiring 17a and the VDD wiring 16a and at the intersection position between the VSS wiring 17b and the VSS wiring 16b.

  That is, the VDD wiring 17a and the VDD wiring 16a are connected in a grid pattern by the contact plug 18a. Similarly, the VSS wiring 17b and the VSS wiring 16b are also connected in a grid pattern.

  The contact plug 18b connecting the sixth wiring layer and the fifth wiring layer is formed at the intersection position between the VDD wiring 16a and the VDD wiring 15a and at the intersection position between the VSS wiring 16b and the VSS wiring 15b.

  That is, the VDD wiring 16a and the VDD wiring 15a are connected in a grid pattern by the contact plug 18b. Similarly, the VSS wiring 16b and the VSS wiring 15b are also connected in a grid pattern.

  The contact plug 18c that connects the fifth wiring layer and the fourth wiring layer is formed at the intersection position between the VDD wiring 15a and the VDD wiring 14a and at the intersection position between the VSS wiring 15b and the VSS wiring 14b.

  That is, the VDD wiring 15a and the VDD wiring 14a are connected in a lattice shape by the contact plug 18c. Similarly, the VSS wiring 15b and the VSS wiring 14b are also connected in a grid pattern.

  The contact plug 18d that connects the fourth wiring layer and the third wiring layer is formed at the intersection position between the VDD wiring 14a and the VDD wiring 13a and at the intersection position between the VSS wiring 14b and the VSS wiring 13b.

  That is, the VDD wiring 14a and the VDD wiring 13a are connected in a grid pattern by the contact plug 18d. Similarly, the VSS wiring 14b and the VSS wiring 13b are also connected in a grid pattern.

Next, the three-dimensional structure of the VDD wiring in the third wiring layer to the seventh wiring layer will be described with reference to FIGS.
4 to 7 are cross-sectional views showing the structure of the initial power supply wiring in the placement and routing method for the semiconductor integrated circuit device according to the first embodiment of the present invention. 4 shows an AA section in FIG. 3, FIG. 5 shows a BB section, FIG. 6 shows a CC section, and FIG. 7 shows a DD section.

  As shown in FIG. 6, the VDD wiring 17a of the seventh wiring layer is connected to the plurality of VDD wirings 16a of the sixth wiring layer by contact plugs 18a. Further, as shown in FIG. 4, a plurality of VDD wirings 17a are connected to one VDD wiring 16a by contact plugs 18a.

  Further, the VDD wiring 16a is connected to the plurality of VDD wirings 15a of the fifth wiring layer by the contact plug 18b shifted by a half pitch (d / 2) from the contact plug 18a in the second direction (left and right direction in FIG. 4). It is connected. Also, as shown in FIG. 7, a plurality of VDD wirings 16a are connected to one VDD wiring 15a by contact plugs 18b.

  Further, the VDD wiring 15a is connected to the plurality of VDD wirings 14a of the fourth wiring layer by the contact plug 18c shifted by a half pitch (d / 2) from the contact plug 18b in the first direction (left and right direction in FIG. 7). It is connected. Further, as shown in FIG. 5, a plurality of VDD wirings 15a are connected to one VDD wiring 14a by contact plugs 18c.

  Further, the VDD wiring 14a is connected to the plurality of VDD wirings 13a in the third wiring layer by the contact plug 18d shifted by a half pitch (d / 2) from the contact plug 18c in the second direction (left and right direction in FIG. 5). It is connected. Further, as shown in FIG. 6, a plurality of VDD wirings 14a are connected to one VDD wiring 13a by contact plugs 18d.

  As described above, the VDD wirings 13a to 17a of the third wiring layer to the seventh wiring layer are formed in a three-dimensional grid pattern of a plurality of layers by the contact plugs 18a to 18d.

  Similarly, the VSS wirings 13b to 17b are also formed in a three-dimensional grid pattern of a plurality of layers by the contact plugs 18a to 18d.

Next, deletion of the initial power supply wiring in the placement and routing method of the semiconductor integrated circuit device will be described.
FIG. 8 is a layout diagram showing an example of initial power supply wiring deletion in the placement and routing method of the semiconductor integrated circuit device according to the first embodiment of the present invention. Here, a case is shown where violations occur at points A and B shown in FIG. 8 in the signal wiring step (ST14).

  At point A, since a problem has occurred in the signal wiring of the sixth wiring layer in the signal wiring step, a part of the VDD wiring 16a is deleted. Further, at point B, a problem has occurred in the signal wiring of the fourth wiring layer, so a part of the VDD wiring 14a is deleted.

  The VDD wirings 13a to 17a are formed in a three-dimensional grid as described above, and in any case, the voltage drop calculated in the voltage drop calculation step is within an allowable range (<5%). is there. Therefore, by rewiring the signal wiring based on the power supply wiring shown in FIG. 8, the problem of signal wiring due to insufficient resources is solved while avoiding voltage drop problems such as malfunction due to voltage drop in the power supply wiring. .

  According to the first embodiment, since the signal wiring resources increase due to the deletion of the power supply wiring, there is a high possibility that the problem caused by the wiring congestion will be solved. The development period can be shortened and the development cost can be reduced.

  Further, according to the first embodiment, since the voltage drop of the power supply wiring is calculated and the deletion of the power supply wiring is determined based on the result, a voltage drop problem such as a malfunction caused by the voltage drop of the power supply occurs. Without increasing the signal wiring resources.

  In the first embodiment, the initial power supply wiring is formed in the third wiring layer to the seventh wiring layer in order to reduce the influence of the voltage drop due to the power supply deletion. However, the present invention is not limited to this. However, if there are two or more wiring layers that can realize power supply to the arranged cells through two or more different paths, the invention can be applied in principle.

  In the first embodiment described above, the area ratio in each wiring layer of the initial power supply wiring is 25%. However, the present invention is not limited to this. For example, a different area ratio is set for each wiring layer. You can also

  Further, in the above-described first embodiment, the initial power supply wirings of the seventh wiring layer and the fifth wiring layer, the fifth wiring layer and the third wiring layer, and the sixth wiring layer and the fourth wiring layer are half pitch (d / 2) Although it is assumed that they are displaced, the present invention is not limited to this. For example, when it is allowed to arrange the upper and lower contact plugs 18a to 18d at the same position in a plane, Corresponding initial power supply wirings can also be arranged at the same position in a plane.

  Further, in the first embodiment described above, the initial power supply wiring is assumed that the VDD wirings 13a to 17a and the VSS wirings 13b to 17b are alternately arranged in each wiring layer. However, the present invention is not limited to this and is necessary. The arrangement order may be set according to the above.

  In the first embodiment, the power supply voltage (VDD) is 3 V. However, the present invention is not limited to this, and may be applied to a low-voltage product such as VDD = 1.2 V, for example. it can.

  Further, in the above-described first embodiment, the allowable voltage drop is 5%, but the present invention is not limited to this. For example, the voltage drop is arbitrarily set within a range in which the arranged cell does not malfunction. You can also Furthermore, a voltage drop allowed at a different value for each cell may be set based on the cell specification.

  FIG. 9 is a flowchart showing a wiring correction step (ST15) in the placement and routing method of the semiconductor integrated circuit device according to the second embodiment of the present invention. Since the floor plan step (ST11), the power supply wiring step (ST12), the cell placement step (ST13), the signal wiring step (ST14), and the information output step (ST16) are the same as those in the first embodiment, description thereof will be omitted. Further, since the initial power supply wiring generated in ST12 is the same as that in the first embodiment, the description is omitted.

  The wiring correction step (ST15) in the placement and routing method for a semiconductor integrated circuit device according to the second embodiment of the present invention includes the step of extracting a violation location (ST91), the step of extracting a deletion candidate location (ST92), and the voltage of the power supply wiring A step of calculating a drop (ST93), a step of determining deletion of the initial power supply wiring based on the voltage drop (ST94), a step of deleting the initial power supply wiring (ST95), and a step of rewiring the signal wiring (ST96) I have.

  Since the processing at each step is the same as that in the first embodiment, detailed description thereof is omitted. The difference from the first embodiment is that the rewiring step (ST96) is repeatedly included in the loop.

  That is, in the rewiring step (ST96), on the basis of the power supply wiring updated in the power supply deletion step (ST95) for each violation part, the signal wiring is rewired by the rewiring module in order to eliminate the violation part, and ST14 The signal wiring routed at is corrected.

  In this way, by performing rewiring for each violation location, if there are relatively few violation locations, that is, if the voltage drop problem is not likely to occur even if the power supply wiring is partially deleted, the wiring correction step The amount of processing in (ST15) can be reduced.

  According to the second embodiment, not only the same effects as in the first embodiment can be obtained, but also the processing can be executed in a shorter time when the number of violations is relatively small.

  FIG. 10 is a flowchart showing a wiring correction step (ST15) in the placement and routing method of the semiconductor integrated circuit device according to the third embodiment of the present invention. Since the floor plan step (ST11), the power supply wiring step (ST12), the cell placement step (ST13), the signal wiring step (ST14), and the information output step (ST16) are the same as those in the first embodiment, description thereof will be omitted. Further, since the initial power supply wiring generated in ST12 is the same as that in the first embodiment, the description is omitted.

  The wiring correction step (ST15) in the placement and routing method of the semiconductor integrated circuit device according to the third embodiment of the present invention includes the step of extracting a violation location (ST101), the step of extracting a deletion candidate location (ST102), and the voltage of the power supply wiring A step of calculating a drop (ST103), a step of determining deletion of the initial power supply wiring based on the voltage drop (ST104), a step of storing the deleted part of the initial power supply wiring (ST105), and rewiring the power supply wiring and the signal wiring Step (ST106).

  Since the processing in each step except the deleted location storage step (ST105) and the rewiring step (ST106) is the same as that in the first embodiment, detailed description thereof is omitted. The difference from the first embodiment is that the initial power supply wiring is not deleted in ST105, but the deleted part is stored as deletion information in ST105, and the power supply wiring and the signal wiring are rewired from the beginning in ST106. is there.

  That is, in the rewiring step (ST106), the power supply wiring is rewired based on the deletion information of the initial power supply wiring stored in the deletion location storing step (ST105), and the signal wiring is further rewired.

  As described above, the deletion information of the initial power supply wiring is stored, and the power supply wiring is rewired based on this information, so that the processing time required for updating the power supply wiring can be shortened when there are many violations.

  According to the third embodiment, not only the same effect as in the first embodiment can be obtained, but also processing can be executed in a shorter time when there are many violations.

1 is a flowchart showing a placement and routing method for a semiconductor integrated circuit device according to Embodiment 1 of the present invention. The flowchart which shows the wiring correction step (ST15) in the arrangement | positioning wiring method of the semiconductor integrated circuit device concerning Example 1 of this invention. 1 is a layout diagram showing initial power supply wiring in a method of arranging and wiring a semiconductor integrated circuit device according to Embodiment 1 of the present invention. 1 is a diagram showing a cross section (AA) of an initial power supply wiring in a method of arranging and wiring a semiconductor integrated circuit device according to Embodiment 1 of the present invention. FIG. 5 is a diagram showing a cross section (BB) of the initial power supply wiring in the placement and routing method for the semiconductor integrated circuit device according to the first embodiment of the present invention. The figure which shows the cross section (CC) of the initial stage power supply wiring in the arrangement | positioning wiring method of the semiconductor integrated circuit device concerning Example 1 of this invention. FIG. 4 is a diagram showing a cross section (DD) of initial power supply wiring in the method of arranging and wiring a semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 3 is a layout diagram showing an example of initial power supply wiring deletion in the placement and routing method for a semiconductor integrated circuit device according to the first embodiment of the present invention; The flowchart which shows the wiring correction step (ST15) in the arrangement | positioning wiring method of the semiconductor integrated circuit device concerning Example 2 of this invention. The flowchart which shows the wiring correction step (ST15) in the arrangement wiring method of the semiconductor integrated circuit device concerning Example 3 of this invention.

Explanation of symbols

ST11 Floor plan step ST12 Power supply wiring step ST13 Cell placement step ST14 Signal wiring step ST15 Wiring correction step ST16 Information output step ST21 Violation point extraction step ST22 Candidate extraction step ST23 Voltage drop calculation step ST24 Deletion determination step ST25 Power supply wiring deletion step ST26 Rewiring Step

Claims (5)

A power supply wiring step in which power supply wiring is routed so that power to cells arranged based on the netlist is supplied by at least two or more different paths;
A cell placement step in which a plurality of the cells are placed;
A signal wiring step in which the signal wiring between the cells arranged in the cell arranging step is wired in the same wiring layer as the initial power wiring arranged in the power wiring step;
The initial power supply disposed in the vicinity of the problematic signal wiring when the signal wiring is unconnected or shorted in the signal wiring step, or when a timing violation occurs in the signal wiring A method of arranging and wiring a semiconductor integrated circuit device, comprising: a wiring correcting step in which wiring is deleted within a permissible voltage drop and the signal wiring in question is rewired. The initial power wiring is
A plurality of first wirings extending along a first direction and supplying a first potential; and a plurality of second wirings extending along the first direction and supplying a second potential. A first wiring layer;
A plurality of third wirings extending along a second direction orthogonal to the first direction and supplying the first potential, and extending along the second direction and supplying the second potential A second wiring layer having a plurality of fourth wirings to be supplied;
The plurality of first wirings and the plurality of third wirings are connected in a grid by contact plugs connecting the first wiring layer and the second wiring layer,
2. The method of arranging and wiring a semiconductor integrated circuit device according to claim 1, wherein the plurality of second wirings and the plurality of fourth wirings are connected in a grid pattern by the separate contact plugs. The wiring correction step includes
The location where the signal wiring is not connected or the wiring is short-circuited, or the location where the timing violation occurs in the signal wiring is specified as a violation location,
In the initial power supply wiring that exists in the vicinity of the violation location identified in the violation location extraction step, a candidate extraction step in which a deletion candidate location is extracted;
In the power supply wiring when the deletion candidate portion extracted in the candidate extraction step is deleted, a voltage drop calculation step in which a voltage drop of the power supply voltage in the cell arranged in the cell arrangement step is calculated;
If the calculated value calculated in the voltage drop calculation step is within a predetermined allowable range of voltage drop, the power supply wiring deletion in which the deletion candidate portion extracted in the candidate extraction step is deleted from the initial power supply wiring Steps,
2. The semiconductor integrated circuit device according to claim 1, further comprising a rewiring step in which the signal wiring routed in the signal wiring step is corrected based on the power supply wiring updated in the power supply wiring deletion step. Placement and wiring method.   4. The semiconductor integrated circuit device according to claim 3, wherein when there are a plurality of violation places, the rewiring step is executed after all the deletion candidate places corresponding to the violation places are deleted. Placement and wiring method. The wiring correction step includes
The location where the signal wiring is not connected or the wiring is short-circuited, or the location where the timing violation occurs in the signal wiring is specified as a violation location,
In the initial power supply wiring that exists in the vicinity of the violation location identified in the violation location extraction step, a candidate extraction step in which a deletion candidate location is extracted;
In the power supply wiring when the deletion candidate portion extracted in the candidate extraction step is deleted, a voltage drop calculation step for calculating a voltage drop of the power supply voltage in the cell arranged in the cell arrangement step;
If the calculated value calculated in the voltage drop calculation step is within a predetermined allowable voltage drop range, a deletion location storage step in which the deletion candidate location extracted in the candidate extraction step is recorded as a deletion location; ,
The method further comprises a rewiring step in which a new power supply wiring is formed based on the deleted location recorded in the deleted location storing step, and a signal wiring between the cells is routed based on the new power supply wiring. Item 2. A placement and routing method for a semiconductor integrated circuit device according to Item 1.

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