JP2009038114A - Semiconductor integrated circuit design method, design apparatus, and manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a chip yield by eliminating inter-chip dispersion in a wafer. <P>SOLUTION: A designing method for a semiconductor integrated circuit includes steps (S8, S9) of generating a database of processing dispersion, a step (S3A) of calculating process dispersion on the wafer from the generated database, a step (S3B) of calculating an RC constant of wiring resistance and a wiring capacity from the calculated process dispersion, and a step (S3C) of calculating a wiring width corresponding to the process dispersion on the wafer and arranging cells. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design method, design apparatus, and manufacturing method, and more particularly to a semiconductor integrated circuit design method, design apparatus, and manufacturing method for forming a large number of semiconductor integrated circuits in a single wafer.

  In recent years, a digital system typified by a semiconductor integrated circuit (LSI) usually uses a synchronous circuit and performs an operation synchronized with a clock signal (synchronization control signal). In a large-scale system, a clock signal output from a clock generation circuit is supplied to and synchronized with a plurality of divided systems. Further, the clock signal is distributed to the subdivided blocks.

  By the way, in order to increase the speed of an LSI, the operating frequency of a clock signal is usually increased. However, when the operating frequency is increased, the phase shift (skew) of the clock signal becomes a value that cannot be ignored with respect to the clock cycle, and the circuit malfunctions.

  Therefore, in a synchronous digital system, it is one of the important issues to make the clock skew as small as possible, and it is necessary to adjust the synchronization timing as necessary. However, since the wiring delay cannot be evaluated at the design stage, it cannot be evaluated until after element placement and wiring.

FIG. 1 is a block diagram schematically showing an example of a conventional semiconductor integrated circuit.
As shown in FIG. 1, a conventional semiconductor integrated circuit 10 has a plurality of logic circuit cells 12, 13, and 14 formed on a substrate 11, and these logic circuit cells are connected by wirings 21, 22, and 23. It has a structured.

  Specifically, the logic circuit cell 12 is a clock generation cell including a clock generation circuit that generates a clock signal (synchronization control signal) in a semiconductor integrated circuit including a digital system, for example, and the logic circuit cells 13 and 14 are For example, an FF cell having a flip-flop circuit to which a predetermined data signal is input and output.

  The clock signal generated in the logic circuit cell (clock generation cell) 12 is distributed to the logic circuit cell 13 via the wirings 21 and 22, and is similarly distributed to the logic circuit cell 14 via the wirings 21 and 23. The

  That is, the wirings 21, 22 and 23 correspond to clock distribution lines for distributing a clock signal, and the logic circuit cells 13 and 14 are logic circuit cells having a predetermined logic circuit and a clock. It is also a clock distribution cell to which the clock signal generated in the generation cell 12 is distributed.

  In FIG. 1, the wirings 22 and 23 are formed so as to branch from the wiring 21, but the branch point branching from the wiring 21 to the wiring 22 generates a clock more than the branch point branching from the wiring 21 to the wiring 23. It is close to the cell 12.

  That is, the length of the wiring (clock distribution wiring) for distributing the clock signal to the clock distribution cell 14 is longer than the length of the wiring for distributing the clock signal to the clock 13.

  Therefore, in the semiconductor integrated circuit of FIG. 1, a phase shift (skew) of the clock signal with respect to the clock distribution cell 13 occurs in the clock distribution cell 14 due to the influence of the wiring delay. Here, the wiring delay is calculated by the product of the resistance value R of the wiring and the parasitic capacitance C of the wiring, and is also referred to as an RC delay.

  The occurrence of skew due to the wiring delay described above may be a particularly serious problem in a high-performance semiconductor integrated circuit that operates at high speed. For example, if the operating frequency of the clock signal is increased in order to operate the semiconductor integrated circuit at a high speed, the skew becomes a value that cannot be ignored with respect to the clock cycle, and there is a greater concern about the malfunction of the circuit.

  Further, in recent semiconductor integrated circuits (LSIs), since the wiring tends to be miniaturized, the resistance (R) of the wiring is increased, and as a result, the influence of wiring delay is increased. Further, when the wiring is miniaturized, the variation in the shape of the wiring in the problem of manufacturing the semiconductor integrated circuit tends to increase, and the problem of variation in the wiring delay also increases.

  FIG. 2 is a flowchart showing an example of processing in a conventional method for designing a semiconductor integrated circuit.

  As shown in FIG. 2, the conventional method for designing a semiconductor integrated circuit includes a logic design step S1 for designing a logic circuit cell constituting the semiconductor integrated circuit, and wiring (placement wiring) for connecting a plurality of logic circuit cells. And a wiring design process S3 for designing.

  That is, the plurality of logic circuit cells designed and arranged in the logic design process S1 are connected by the wiring designed in the wiring design process S3, and the outline of the semiconductor integrated circuit is designed.

  Here, the logic design step S1 includes a plurality of logic circuit cell synthesis (individual cell design) step S1A, a plurality of logic circuit cell arrangement design step S1B, and a skew verification (clock signal distribution timing verification) step. S1C.

  First, in the cell synthesis step S1A, individual logic circuit cells constituting the semiconductor integrated circuit are designed (synthesized). Note that the logic circuit cells to be synthesized include cells corresponding to the clock generation cell 12 described above and cells corresponding to the clock distribution cells 13 and 14.

  Next, the process proceeds to a cell arrangement design step S1B, where the arrangement of the plurality of logic circuit cells is designed. That is, in step S1B, the layout of a plurality of logic circuit cells is designed.

  Further, the process proceeds to a skew verification step S1C to verify (calculate) the skew in the arrangement of the logic circuit cells. At this time, in step S1C, the skew is roughly estimated using the relationship of the distances due to the layout of the logic circuit cells without considering the length of the placement and routing designed in the subsequent step.

  Then, the process proceeds to step S2 to determine whether or not the skew is sufficiently small. If it is determined in step S2 that the skew is not sufficiently small, the process returns to the cell arrangement design step S1B and the above-described processing is performed. Conversely, if it is determined that the skew is sufficiently small. Then, the process proceeds to a wiring design (placement wiring design) step S3, and a wiring (placement wiring) for connecting the plurality of arranged logic circuit cells is designed. The designed wiring includes clock distribution wiring corresponding to the wirings 21, 22, and 23 described with reference to FIG.

  Next, in a skew verification (clock signal distribution timing verification) step S4, a skew is verified (calculated) when the logic circuit cells are connected by wiring (clock distribution wiring). At this time, in step S4, the skew is calculated in consideration of the length of the arrangement wiring, that is, in consideration of the influence of the wiring delay of the clock distribution wiring.

  Further, the process proceeds to step S5, and it is determined whether or not the skew is a practically sufficient value (whether or not the skew is sufficiently small for the operation of the circuit). If it is determined in step S5 that the skew is not sufficiently small in practice, the process returns to the wiring design step S3 and the above-described processing is performed. If it is determined that it is sufficiently small so as not to cause a problem in the operation of the device, the process proceeds to a device manufacturing data creation step S6.

  In the device manufacturing data creation step S6, data for device creation is created, and the process further proceeds to the semiconductor device manufacturing step S7 to manufacture a semiconductor integrated circuit corresponding to the data.

  As apparent from FIG. 2, in the conventional semiconductor integrated circuit design method described above, since the influence of the wiring delay is not known in the logic design step S1, accurate skew verification is performed after the wiring design step S3. This is done after designing the placement and routing (clock distribution wiring).

  However, as described above, for example, if the influence of the wiring delay increases due to the miniaturization of the wiring (clock distribution wiring), the skew may not be sufficiently reduced only by changing the wiring routing. It will occur.

  That is, if it is determined in step S5 that the skew is not sufficiently small in practice, the process returns to the logic design step S1 (for example, the cell placement design step S1B) instead of the wiring design step S3. Necessity arises (back annotation: broken line in FIG. 2). When such back annotation occurs, a design period loss occurs, and the cost of designing (manufacturing) the semiconductor integrated circuit increases.

  As a method for solving the above-described skew problem, for example, a method of adjusting a skew by adding a predetermined circuit (for example, a delay circuit) to a semiconductor integrated circuit has been proposed. However, a method for adding a circuit for skew adjustment to a semiconductor integrated circuit complicates and enlarges the semiconductor integrated circuit, which is a problem in reducing the size and integration of the semiconductor integrated circuit. Become.

  Although the design method here mainly indicates verification of the skew of the FF circuit, the verification after the design is not limited to the FF circuit. For example, the same design flow can be used even when a logic circuit, an SRAM circuit, or the like is used. It can be.

  3 to 6 are diagrams for explaining processing by a general damascene method, and sequentially show a method for manufacturing a semiconductor integrated circuit. In the description of FIGS. 3 to 6, the portions described above may be denoted by the same reference numerals and description thereof may be omitted.

  First, in the process shown in FIG. 3, the following structure including the MOS transistor 303 is formed on a substrate 301 made of a semiconductor such as Si, for example, by using a conventional method.

  The MOS transistor 303 is formed in an active region (element formation region) defined by an element isolation insulating film 302 having a shallow trench isolation (STI) structure formed in the surface layer portion of the substrate 301.

  The MOS transistor 303 includes a gate electrode 303G formed on the gate insulating film 303I on the substrate 301, and further includes a source region 303S and a drain region 303D that are opposed to each other with the gate insulating film 303I interposed therebetween. . Further, an interlayer insulating film 304 made of silicon oxide and having a thickness of 50 nm and a protective film 306 made of SiOC and having a thickness of 50 nm are stacked so as to cover the MOS transistor 303.

  A conductive plug 305B made of tungsten (W) connected to the drain region 303D is formed in the via hole that penetrates the protective film 306 and the interlayer insulating film 304, and between the conductive plug 305B and the inner surface of the via hole. A barrier metal layer 305A made of TiN and having a thickness of 25 nm is disposed.

  Further, an interlayer insulating film 310 made of a low dielectric constant insulating material is formed on the protective film 306, and a wiring 311 made of Cu connected to the conductive plug 305B is formed in the groove formed in the interlayer insulating film 310. Is formed. Further, a barrier film 311B containing Ta for preventing diffusion of Cu is formed around the wiring 311.

  The above structure can be formed by, for example, well-known photolithography, etching, chemical vapor deposition (CVD), chemical mechanical polishing (CMP), or the like.

  Next, in the step shown in FIG. 4, a cap film 320, an interlayer insulating film 321, an etching stopper film 322, and an interlayer insulating film 323 are sequentially stacked on the interlayer insulating film 310.

  The cap film 320 has, for example, a two-layer structure of a silicon oxide (SiO) film and a silicon carbide (SiC) film, and the total thickness is 20 to 70 nm. The etching stopper film 322 is made of, for example, SiC or silicon nitride (SiN) and has a thickness of 20 to 70 nm. These films can be formed by, for example, a CVD method.

  The interlayer insulating films 321 and 323 are formed of an organic or inorganic low dielectric constant insulating material and have a thickness of 300 to 700 nm. Examples of the inorganic low dielectric constant insulating material include porous silica and SiOC, and examples of the organic low dielectric constant insulating material include SiLK (registered trademark) manufactured by The Dow Chemical Company. be able to. These materials contain Si and O as constituent elements.

  Further, in the step shown in FIG. 5, in order to form the via hole 324H in the interlayer insulating film 321 and to form the groove 325H in the interlayer insulating film 323, for example, pattern etching using a mask pattern using a photolithography method. I do. Note that either the via hole 324H or the groove 325H may be formed first.

  Here, the dimension (width) of the planar cross section of the via hole 324H is, for example, 0.06 to 0.1 μm, and the minimum width of the groove portion 325H is, for example, 0.06 μm. The via hole 324H and the groove 325H can be formed, for example, by dry etching using a CF-based etching gas using a film including two layers of an SiO film and an SiC film as a hard mask. Further, the groove portion 325H reaches the upper surface of the etching stopper film 322, and the via hole 324H reaches the upper surface of the wiring 311.

  Note that when the groove 325H is formed by pattern etching of the interlayer insulating film 323, the structure rising from the bottom of the groove 325H is formed by pattern etching together with the groove 325H. Further, w1 and t1 in FIG. 3 indicate the wiring width and wiring height when the first-layer wiring process is performed.

  By the way, conventionally, by obtaining process variations according to the positions of a plurality of chips (LSIs) on a plurality of detected wafers in advance, and selecting and drawing a pattern of a semiconductor manufacturing apparatus according to the process variations, a delay time is obtained. There has been proposed an LSI in which the worst value is made smaller and the best value is made larger to facilitate LSI design (see, for example, Patent Document 1).

  Conventionally, a wiring structure that takes into account the variation condition including the wiring existing around the target wiring is generated, and the wiring capacity is calculated from this wiring structure to extract the wiring capacity considering the variation in the manufacturing process. In addition, a circuit simulation technique capable of performing delay analysis with high accuracy has also been proposed (see, for example, Patent Document 2).

  Furthermore, conventionally, it relates to a technique for forming a low-resistance wiring layer on a glass substrate in a display device such as a liquid crystal display device, but the relationship between the average crystal grain size of the copper plating layer and the specific resistance is There has also been proposed a technique of approximating by a model equation that the main factor of increase is due to scattering at the grain boundaries (see, for example, Patent Document 3).

  In addition, conventionally, the consideration regarding the size effect of the resistivity of a metal (copper) was also performed (for example, refer nonpatent literatures 1-3).

JP 2004-063815 A JP 2001-265826 A JP 2006-024754 A A. F. Mayadas et al., "Electrical-Resistivity Model for Polycrystalline Films: the Case of Arbitrary Reflection at External Surfaces", Phys. Rev. B1 (1970), PP.1382-1389 E.H.Sondheimer, "The Influence of a Transverse Magnetic Field on the Conductivity Thin Metallic Films", Phys. Rev. 80 (1950), pp.401-406 W. Steinhogl et al., "Comprehensive study of the thermally of copper wires with lateral dimensions of 100 nm and smaller", J. Appl. Phis. 97, 023706 (2005)

  In recent years, with the miniaturization of the LSI manufacturing process, the wiring delay is becoming larger than the element delay, and the problem of wiring with respect to the delay has been highlighted. In addition, as the miniaturization progresses, the problem of manufacturing variation has also expanded. In particular, as the frequency increases, the clock skew and timing adjustment in the chip are becoming more complicated.

  On the other hand, LSIs are manufactured by a wafer process, but an increase in wafer diameter has spurred an increase in in-plane variation of the manufacturing process. For this reason, the number of chips that deviate from the design margin for in-plane process variations of the wafer has increased, and the yield of chips has also deteriorated. On the other hand, when the design margin is increased, there is a problem that the desired performance of the chip cannot be expected.

  In addition, according to the technique described in Patent Document 1 described above, circuit design assuming various process variations must be performed in advance, and if the number of processes increases, the number of combinations of variations increases. Therefore, the work time for circuit design in advance is very long. In other words, the technique described in Patent Document 1 has a problem that, although the number of circuits in which the optimum pattern is actually selected is small, the work time spent in advance is long and the time loss is large.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a semiconductor integrated circuit design method, design apparatus, and manufacturing method that improve chip yield by solving chip-to-chip variations in a wafer.

  According to the first aspect of the present invention, a step of creating a process variation database, a step of calculating process variations on a wafer from the created database, and wiring resistance and wiring from the calculated process variations There is provided a method for designing a semiconductor integrated circuit, comprising: calculating an RC constant of capacitance; and calculating and arranging a wiring width according to process variation on the wafer.

  According to the second aspect of the present invention, database creation means for creating a process variation database, process variation calculation means for calculating process variation on a wafer from the created database, and the calculated process variation. A semiconductor device comprising: RC constant calculating means for calculating RC constants of wiring resistance and wiring capacity; and wiring width calculating and arranging means for calculating and arranging a wiring width according to process variations on the wafer. An integrated circuit design apparatus is provided.

  According to the third aspect of the present invention, the step of measuring the in-wafer pattern dimension of the previous step, the step of calculating the RC constant from the measured pattern size of the wafer, and the pattern size of the next step are calculated. And a step of selecting a process condition so that the RC constant is constant. A method for manufacturing a semiconductor integrated circuit is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the design method of a semiconductor integrated circuit, the design apparatus, and the manufacturing method which solved the dispersion | variation between the chips in a wafer and improved the chip yield can be provided.

  Before describing embodiments of a semiconductor integrated circuit design method, design apparatus, and manufacturing method according to the present invention in detail, the principle of the present invention will be schematically described.

  First, the present invention measures the process dimension variation (process variation) during the manufacturing process, calculates the RC constant from the measured process variation, calculates the delay, and performs the dimension in the next process so that the delay is the same. Take control.

  In addition, the present invention measures the variation in pattern dimensions of a plurality of circuits formed in a wafer (pattern variation in the wafer), calculates the RC constant from the measured pattern variation in the wafer, and performs delay calculation. The wiring width is set so that the delay is the same.

  Further, according to the present invention, resistance calculation is performed using a resistance calculation model of a copper wiring, for example, for delay calculation when the wiring shape varies.

  7 to 10 are diagrams for schematically explaining the semiconductor integrated circuit design method according to the present invention, and show the case where the cross-sectional shape of the wiring is changed. 8 to 10 conceptually show the wiring width distribution in the wafer, the wiring height distribution in the wafer, and the delay time distribution when the wafer is viewed from above. In FIGS. 8 to 10, in order to describe the numerical value for each position in the wafer, it is drawn as a shape that spreads horizontally, but it goes without saying that the actual wafer has a substantially circular shape. Nor.

  First, when standard process conditions are used, as shown in FIG. 7B, the wiring width W and wiring height (thickness) T must be constant at all positions in the wafer surface. However, in the actually manufactured semiconductor integrated circuit, the wiring as shown in FIG. 7B is formed only in the portion [II] between the central portion [I] and the peripheral portion [III] of the wafer, for example. Can not do it.

  Furthermore, in the semiconductor integrated circuit actually manufactured, in the central portion [I] of the wafer, for example, as shown in FIG. 7A, the wiring width W becomes narrow (W−ΔW), and the wafer In the peripheral portion [III] of FIG. 7, as shown in FIG. 7C, the wiring width W is wide (W + ΔW).

  Here, as shown in FIG. 7A, when the wiring width W is reduced, the wiring resistance is increased, but the distance between adjacent wirings is increased, so that the capacitance between the wirings is reduced. On the other hand, as shown in FIG. 7C, when the wiring width W increases and the wiring height T decreases, the wiring resistance decreases as the wiring width W increases and the distance between the wirings decreases. Capacity increases.

  8 and 9 show the distribution of the wiring width W and the distribution of the wiring height T in one wafer. According to the present invention, if the wiring width W is wide, the wiring height T is lowered (see FIG. 7A). Conversely, if the wiring width W is narrow, the wiring height T is increased (FIG. 7C). refer. Note that the wiring width distribution in FIG. 8 shows the wiring width at each position of the wafer in nm, and the average value is 83.9 [nm]. The wiring height distribution in FIG. 9 shows the wiring height at each position of the wafer in nm, and the average value is 141.1 [nm].

  That is, during the manufacturing process, for example, an in-plane distribution after etching causes a wiring width distribution as shown in FIG. 8 depending on each position of the wafer. The wiring width distribution as shown in FIG. 8 can generally occur in the manufacturing process, and there are many cases where it is difficult to improve the distribution depending on the manufacturing apparatus.

  In the present invention, for example, in the wiring width distribution as shown in FIG. 8, for example, in the next CMP wiring polishing step, the wiring height T is high (T + ΔT) in the central portion [I] of the wafer. In addition, the CMP condition is set so that the wiring height T is low (T−ΔT) in the peripheral portion [III] of the wafer, and the wiring polishing is executed to complete the first layer wiring process.

  As a result, as shown in FIG. 9, the wiring height T is increased in the central portion [I] of the wafer, and the wiring height T is decreased in the peripheral portion [III] of the wafer. S is substantially constant regardless of the position of the wafer, as shown in the shapes (cross-sectional shapes) of FIGS. 7A, 7B, and 7C.

  Next, when the wiring delay time is calculated by the delay calculation, the delay distribution is not as bad as the distribution of the wiring height and the wiring width. This is because the RC delay of the wiring cancels each other with respect to the fluctuation of the wiring width and the wiring height due to the capacitance × resistance, and therefore FIG. 7A, FIG. 7B and FIG. This is because there is a condition that the RC delay time becomes equal regardless of the shape of the wiring.

  That is, as shown in FIG. 10, the delay time distribution can be made substantially constant regardless of the position of the wafer. The delay time distribution shown in FIG. 10 shows the delay time of 1 mm wiring at each position of the wafer in ps, and the average value is 182.1 [ps].

  Thus, by applying the present invention, the delay time hardly changes even if the shape of the wiring is different, so that the performance between chips can be made substantially the same.

  Embodiments of a semiconductor integrated circuit design method, design apparatus, and manufacturing method according to the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 11 is a flowchart showing an example of processing in the method for designing a semiconductor integrated circuit according to the present invention.

  As is clear from a comparison between FIG. 11 and FIG. 2 described above, the semiconductor integrated circuit design method of the present embodiment shown in FIG. 11 roughly includes steps S8 and S9 for newly creating a process variation database. In addition, the process S3 (placement and wiring process) in the conventional semiconductor integrated circuit design method shown in FIG. 2 is changed to a process S3 ′ including a process variation calculation process S3A, an RC calculation process S3B, and a layout and wiring process S3C. Step S5 (step of determining whether the skew is a practically sufficient value) is deleted. In the following description, steps S1, S2, S4, S6 and S7 are substantially the same as those described with reference to FIG.

  First, as shown in FIG. 11, the semiconductor integrated circuit design method of this embodiment includes a logic design step S1 related to the design of a plurality of logic circuit cells constituting the semiconductor integrated circuit, and the plurality of logic circuit cells. A wiring design process S3 ′ for designing the wiring to be connected (placement wiring).

  That is, a plurality of logic circuit cells designed and arranged in the logic design step S1 similar to the conventional semiconductor integrated circuit design method described with reference to FIG. The outline of the semiconductor integrated circuit is designed by wiring.

  The wiring design step S3 'of this embodiment and steps (configurations) S8 and S9 for creating a newly added process variation database will be described. The wiring design step S3 ′ is connected to a process database (S9), and this process database S9 is a wiring step process (for example, a photo process, an etching process, a metal deposition process, a CMP process, and an interlayer film deposition process). It is a database which shows the process variation of S8.

  Here, in the process S8 of the wiring process, for example, process data such as a photo process and an etching process of each chip on the wafer is collected in advance, and a process database S9 is created.

  That is, in the process database S9, wafer position information such as the wiring height and width of the wiring process already exists as a database, and is collected in advance by the process of each unit in the wiring process S8, for example, The wiring width distribution within the wafer surface, the wiring height distribution after CMP, and the like as described with reference to FIGS. 7 to 10 are included.

  For example, when placing and routing after logical design, place and route with the wiring width under the central condition. At this time, calculate the wiring resistance by incorporating the wiring height distribution and wiring width distribution on the wafer surface at the same time. To the placement and routing process. Here, the wiring width is transferred to CAD data by calculating a design value of the wiring width so that the RC constant is constant within the wafer surface. Note that the wiring width in the wafer plane is different for each chip because the RC constant is given to be constant.

  12 and 13 are flowcharts showing another example of processing in the method for designing a semiconductor integrated circuit according to the present invention. Since FIG. 12 is substantially the same as that described with reference to FIG. 2 described above, the description thereof is omitted.

  In other words, the present embodiment corrects the wiring width and wiring height in the semiconductor integrated circuit manufacturing process (wiring manufacturing process) S7. At this time, the mask design value of the wiring pattern is the same within the wafer surface (corresponding to the wiring manufacturing process without correction as described with reference to FIG. 11). It is assumed that the process conditions and the results of CD (Critical Dimension) values in the wafer surface are stored in a database.

  That is, for example, when the CD value is measured in the inspection process of the etching process S74 and the result is that the wiring width becomes thicker toward the periphery of the wafer as shown in FIG. 8, the CD data (process data S75). The RC constant is calculated from (2), and the wiring height is calculated so that the RC constant becomes constant in the next CMP step S77 to generate correction data (RC calculation / correction data S76).

  Then, in the CMP step S77, the CMP process is performed according to the created correction data (S75). That is, the wiring height distribution data (correction data) as shown in FIG. 9 is created from the wiring width distribution data as shown in FIG. 8, and the CMP conditions that become the wiring height distribution data are created from the database. Select and polish. Specifically, the CMP process is performed with correction so that the wiring height in the central portion of the wafer is high and the wiring height in the peripheral portion is low.

  The above description is a case where the difference in wiring width (wiring width distribution) at each position of the wafer in the etching step S74 is corrected in the subsequent CMP step S77. For example, the wiring height distribution in the photo step S71 is corrected thereafter. The same applies to the case where the correction is performed in the etching step S74 or the case where the wiring height distribution in the CMP step S77 is corrected in a subsequent step (for example, an interlayer deposition step). The process data S75 and the RC calculation / correction data 76 described above correspond to the process data S72, S78 and the RC calculation / correction data 73, 79, respectively. Furthermore, it is needless to say that the resistivity calculation method can be performed using a wiring height dependency or wiring width dependency model.

  Thus, by calculating the correction between the processing steps from the calculation result of the RC constant and selecting the process conditions, the chip performance at each position in the wafer surface can be made substantially the same.

  Next, a specific RC constant calculation method will be described. The wiring resistance calculation method incorporates, for example, a size effect that depends on the wiring width and wiring height of the copper resistivity. In recent LSI wiring, when the wiring width becomes narrower, the resistivity rapidly increases, and recently, the wiring width becomes 0.1 μm or less and reaches about twice the bulk resistivity.

  In such a region where the size effect is remarkable, the rate of change in resistivity increases due to process variations in the wiring height and wiring width in the wafer surface, and thus the resistance value greatly deviates from the resistance value assumed for normal sheet resistance. Therefore, it is necessary to accurately determine the resistivity when the wiring height or wiring width changes.

  By the way, the resistivity model of copper (metal) is reported, for example, by Non-Patent Documents 1 and 2 described above, and the application of this resistivity model to wiring is, for example, Non-Patent Document 3 described above. It is reported by.

FIG. 14 is a diagram for explaining a resistivity model of copper used in the present invention.
As shown in FIG. 14, the size effect is divided into electron surface scattering (p in the formula) and grain boundary scattering (R in the formula). It has been found that the grain size of fluctuates with the wiring height.

  In the damascene method, the particle size (d) decreases with the width of the wiring, and also changes depending on the height of the wiring. In the model equation, the inventors' experiments have shown that the grain boundary scattering component when the wiring width is narrow is about half of the resistivity increase. Therefore, it is very important to use the grain boundary parameters accurately.

  By newly modeling this grain boundary scattering parameter and incorporating it into the model of resistance reported so far, it is possible to accurately obtain a prediction of wiring resistivity, which has been unpredictable until now.

  That is, when calculating the RC constant, it is preferable to use, for example, a model of electron grain boundary scattering and surface scattering, and a particle size model corresponding to variations in the width and height of wiring for copper resistance calculation.

  In the above description, the damascene structure wiring using copper as the wiring has been described. However, the wiring is not necessarily limited to the damascene structure copper wiring.

  FIG. 15 is a diagram for explaining an example of a medium recording a design program for a semiconductor integrated circuit to which the present invention is applied. In FIG. 15, reference numeral 10 denotes a semiconductor integrated circuit design processing apparatus (computer), 20 denotes a program (data) provider, and 30 denotes a portable recording medium.

  The present invention is given as a program (data) for the processing apparatus 10 as shown in FIG. The processing device 10 includes an arithmetic processing device main body 11 including a processor, and a processing device side memory (for example, a RAM (Random Access Memory) that stores a result of giving or processing a program (data) to the arithmetic processing device main body 11. ) Or hard disk) 12 or the like. The program provided to the processing device 10 is loaded and executed on the main memory of the processing device 10.

  The program provider 20 has means (line destination memory: for example, DASD (Direct Access Storage Device)) 21 for storing the program, and provides the program to the processing apparatus 10 via a line such as the Internet, or The data is provided to the processing apparatus 10 via a portable recording medium 30 such as an optical disk such as a CD-ROM or DVD, a magnetic disk, or a magnetic tape. Needless to say, the medium on which the design program of the semiconductor integrated circuit according to the present invention is recorded includes the processing device side memory 12, the line destination memory 21, the portable recording medium 30, and the like.

  As mentioned above, by applying the present invention, it is possible to improve the chip yield in the wafer, for example, even if the process variation is large and the process conditions have to be relaxed, and the chip performance improvement cannot be expected, The chip performance can be improved by utilizing the process variation characteristics of both RC. As described above, according to the present invention, the chip yield in the wafer can be improved, the performance of the chip (semiconductor integrated circuit) can be improved, and the time required for them can be shortened.

  The present invention can be applied to the design and manufacture of a semiconductor integrated circuit in which a large number of semiconductor integrated circuits are formed in one wafer, and in particular, to manufacture a semiconductor integrated circuit having a high demand for skew at a high yield. The present invention can be widely applied to the design and manufacture of semiconductor integrated circuits.

It is a block diagram which shows an example of the conventional semiconductor integrated circuit roughly. It is a flowchart which shows an example of the process in the design method of the conventional semiconductor integrated circuit. It is FIG. (1) for demonstrating the process by a general damascene method. It is FIG. (2) for demonstrating the process by the general damascene method. It is FIG. (3) for demonstrating the process by the general damascene method. It is FIG. (4) for demonstrating the process by the general damascene method. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram (part 1) for schematically explaining a method for designing a semiconductor integrated circuit according to the present invention; FIG. 6 is a diagram (part 2) for schematically describing the semiconductor integrated circuit design method according to the present invention; FIG. 6 is a diagram (part 3) for schematically describing the semiconductor integrated circuit design method according to the invention; FIG. 6 is a diagram (part 4) for schematically describing the semiconductor integrated circuit design method according to the invention; It is a flowchart which shows an example of the process in the design method of the semiconductor integrated circuit which concerns on this invention. It is a flowchart (the 1) which shows the other example of the process in the design method of the semiconductor integrated circuit which concerns on this invention. It is a flowchart (the 2) which shows the other example of the process in the design method of the semiconductor integrated circuit which concerns on this invention. It is a figure for demonstrating the resistivity model of copper used by this invention. It is a figure for demonstrating the example of the medium which recorded the design program of the semiconductor integrated circuit to which this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Processing device 11 Arithmetic processing device main body 12 Processing device side memory 20 Program (data) provider 21 Means for storing program (line destination memory)
30 Portable recording media

Claims (6)

Creating a process variation database;
Calculating process variations on the wafer from the created database;
Calculating RC constants of wiring resistance and wiring capacity from the calculated process variation;
Calculating and arranging a wiring width corresponding to process variations on the wafer, and designing a semiconductor integrated circuit. The method for designing a semiconductor integrated circuit according to claim 1,
A method for designing a semiconductor integrated circuit, wherein the wiring is a damascene wiring using copper. The method of designing a semiconductor integrated circuit according to claim 2,
The step of creating the database comprises creating a database relating to the width and height of the wiring. The method of designing a semiconductor integrated circuit according to claim 2,
The step of calculating the RC constant includes:
A method for designing a semiconductor integrated circuit, wherein a model of electron grain boundary scattering and surface scattering and a particle size model corresponding to variations in the width and height of the wiring are used for copper resistance calculation. Database creation means for creating a process variation database;
Process variation calculating means for calculating the process variation on the wafer from the created database;
RC constant calculation means for calculating RC constants of wiring resistance and wiring capacitance from the calculated process variation;
An apparatus for designing a semiconductor integrated circuit, comprising: a wiring width calculating / arranging unit that calculates and arranges a wiring width according to process variations on the wafer. A step of measuring the pattern size in the wafer in the previous step;
Calculating an RC constant from the measured in-wafer pattern dimension;
And a step of selecting process conditions such that the calculated RC constant is constant for a pattern dimension of the next process.

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