JP2009038189A - Semiconductor device, voltage supply system, and semiconductor device manufacturing method - Google Patents

Abstract

A semiconductor device capable of improving ESD resistance is provided.
The semiconductor device includes an internal circuit including an NMOS transistor, a p-type well diffusion region, and a pair of n-types facing each other at a predetermined interval in the p-type well diffusion region. And an electrostatic protection circuit 2 including a protection element 41 having regions 12a and 12b. The p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2 is configured to have a higher p-type impurity concentration than the p-type well diffusion region 4 of the NMOS transistor 31 included in the internal circuit 1. ing.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device, a voltage supply system, and a method for manufacturing a semiconductor device.

  Conventionally, a semiconductor device provided with an I / O circuit including an ESD (electrostatic discharge) protection circuit is known (see, for example, Patent Document 1).

  The conventional I / O circuit of the semiconductor device disclosed in Patent Document 1 is an ESD protection element comprising an input / output circuit including a MOS transistor and a low breakdown voltage MOS transistor having a drain breakdown voltage lower than that of the MOS transistor of the input / output circuit. And at least. The conventional I / O circuit of the semiconductor device is configured such that when an ESD surge is applied to the I / O circuit, the ESD protection element (low voltage MOS transistor) is turned on by turning on the parasitic bipolar transistor. Through the ESD current.

JP 2005-5333 A

  Patent Document 1 discloses the following two methods for obtaining a low breakdown voltage MOS transistor as an ESD protection element. One is a method in which the impurity concentration of the drain diffusion layer of the low breakdown voltage MOS transistor as the ESD protection element is set higher than the impurity concentration of the drain diffusion layer of the MOS transistor of the input / output circuit. The other is a method in which the gate length of the low breakdown voltage MOS transistor as the ESD protection element is made shorter than the gate length of the MOS transistor of the input / output circuit.

  However, in the MOS transistor of the I / O circuit, the drain diffusion layer is formed by supersaturated ion implantation in order to sufficiently reduce the on-resistance. Therefore, it is difficult to make the impurity concentration of the drain diffusion layer of the low breakdown voltage MOS transistor as the ESD protection element higher than the impurity concentration of the drain diffusion layer of the MOS transistor of the input / output circuit.

  Further, the MOS transistor of the I / O circuit has its gate length set to the minimum dimension (for example, about 0.18 μm) allowed by the process. Therefore, it is difficult to make the gate length of the low breakdown voltage MOS transistor as the ESD protection element shorter than the gate length of the MOS transistor of the input / output circuit.

  As a result, conventionally, since it is difficult to form a low breakdown voltage MOS transistor as an ESD protection element, there is a problem that it is difficult to obtain a semiconductor device having high ESD resistance.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device, a voltage supply system, and a semiconductor device manufacturing method capable of improving ESD tolerance. That is.

  To achieve the above object, a semiconductor device according to a first aspect of the present invention has an internal circuit formed on a semiconductor substrate and including at least an NMOS transistor, and a function formed on the semiconductor substrate to protect the internal circuit from static electricity. An electrostatic protection circuit including at least a protection element having a p-type well diffusion region and a first n-type region and a second n-type region facing each other at a predetermined interval in the p-type well diffusion region It has. At least a part of the p-type well diffusion region of the protection element included in the electrostatic protection circuit is configured to have a higher p-type impurity concentration than the p-type well diffusion region of the NMOS transistor included in the internal circuit. .

  In the semiconductor device according to the first aspect, as described above, at least a part of the p-type well diffusion region of the protection element included in the electrostatic protection circuit is more than the p-type well diffusion region of the NMOS transistor included in the internal circuit. By configuring the p-type impurity concentration to be high, the junction breakdown voltage of the protection element included in the electrostatic protection circuit can be made lower than the junction breakdown voltage of the NMOS transistor included in the internal circuit. In this case, even if an ESD (electrostatic discharge) surge is applied to the semiconductor device, the ESD current flows out through the protection element having a low junction breakdown voltage of the electrostatic protection circuit, so that the ESD current is prevented from flowing into the internal circuit. can do. As a result, damage to the internal circuit due to the ESD surge being applied to the semiconductor device can be suppressed. That is, the ESD tolerance of the semiconductor device can be improved.

  A semiconductor device according to a second aspect of the present invention includes an internal circuit formed on a semiconductor substrate and including at least a MOS transistor, and a function formed on the semiconductor substrate to protect the internal circuit from static electricity, and a MOS transistor And an electrostatic protection circuit including at least a protection element made of The MOS transistors included in the electrostatic protection circuit are connected such that the gate potential is the same as the drain side potential, and the threshold voltage of the MOS transistor included in the electrostatic protection circuit is a predetermined voltage applied during normal operation. When the static electricity is applied, the MOS transistor included in the static electricity protection circuit is turned on when the static electricity is applied. By flowing static electricity, it is configured to suppress static electricity from flowing into the internal circuit.

  In the semiconductor device according to the second aspect, since the ESD current flows out through the MOS transistor in which the electrostatic protection circuit is turned on even when an ESD surge is applied to the semiconductor device, the semiconductor device according to the second aspect is configured so that Current can be prevented from flowing into the internal circuit. As a result, damage to the internal circuit due to the ESD surge being applied to the semiconductor device can be suppressed. That is, the ESD tolerance of the semiconductor device can be improved.

  A voltage supply system according to a third aspect of the present invention includes the semiconductor device according to any one of claims 1 to 16. If comprised in this way, the voltage supply system provided with the semiconductor device with high ESD tolerance can be obtained easily.

  A method for manufacturing a semiconductor device according to a fourth aspect of the present invention has a step of forming an internal circuit including at least an NMOS transistor on a semiconductor substrate, and a function of protecting the internal circuit from static electricity on the semiconductor substrate. Forming a static electricity protection circuit including at least a protection element having a p-type well diffusion region and a first n-type region and a second n-type region facing each other at a predetermined interval in the p-type well diffusion region. I have. The step of forming the internal circuit includes a step of ion-implanting p-type impurities only in the region for forming the p-type well diffusion region of the NMOS transistor included in the internal circuit. Protection included in the electrostatic protection circuit so that at least part of the p-type well diffusion region of the protection element included in the protection circuit has a higher p-type impurity concentration than the p-type well diffusion region of the NMOS transistor included in the internal circuit. It includes a step of ion-implanting p-type impurities only in a region where the p-type well diffusion region of the element is formed.

  In the semiconductor device manufacturing method according to the fourth aspect, by configuring as described above, the p-type impurity concentration of at least a part of the p-type well diffusion region of the protective element included in the electrostatic protection circuit can be easily set. It can be made higher than the p-type impurity concentration of the p-type well diffusion region of the NMOS transistor included in the internal circuit. That is, the junction breakdown voltage of the protection element included in the electrostatic protection circuit can be easily made lower than the junction breakdown voltage of the NMOS transistor included in the internal circuit. In this case, even if an ESD surge is applied to the semiconductor device, the ESD current flows out through the protective element having a low junction withstand voltage of the electrostatic protection circuit, so that the ESD current can be easily prevented from flowing into the internal circuit. Can do. As a result, the internal circuit is prevented from being damaged due to the ESD surge being applied to the semiconductor device, so that the ESD resistance of the semiconductor device can be easily improved.

  A semiconductor device according to a fifth aspect of the present invention has a step of forming an internal circuit including at least an NMOS transistor on a semiconductor substrate, a function of protecting the internal circuit from static electricity on the semiconductor substrate, and a p-type semiconductor device. Forming a static electricity protection circuit including at least a protection element having a well diffusion region and a first n-type region and a second n-type region facing each other at a predetermined interval in the p-type well diffusion region. . The step of forming the internal circuit includes both a region for forming the p-type well diffusion region of the NMOS transistor included in the internal circuit and a region for forming the p-type well diffusion region of the protective element included in the electrostatic protection circuit. Including a step of ion-implanting a p-type impurity to form a static electricity protection circuit, wherein the step of forming an electrostatic protection circuit includes the p-type of an NMOS transistor in which at least a part of the p-type well diffusion region of the protection element included in the electrostatic protection circuit is included in the internal circuit. The method includes a step of ion-implanting the p-type impurity again only in a region where the p-type well diffusion region of the protection element included in the electrostatic protection circuit is formed so that the p-type impurity concentration is higher than that of the well diffusion region.

  In the semiconductor device manufacturing method according to the fifth aspect, by configuring as described above, the p-type impurity concentration of at least a part of the p-type well diffusion region of the protection element included in the electrostatic protection circuit can be easily set. It can be made higher than the p-type impurity concentration of the p-type well diffusion region of the NMOS transistor included in the internal circuit. That is, the junction breakdown voltage of the protection element included in the electrostatic protection circuit can be easily made lower than the junction breakdown voltage of the NMOS transistor included in the internal circuit. In this case, even if an ESD surge is applied to the semiconductor device, the ESD current flows out through the protective element having a low junction withstand voltage of the electrostatic protection circuit, so that the ESD current can be easily prevented from flowing into the internal circuit. Can do. As a result, the internal circuit is prevented from being damaged due to the ESD surge being applied to the semiconductor device, so that the ESD resistance of the semiconductor device can be easily improved.

  As described above, according to the present invention, it is possible to easily obtain a semiconductor device, a voltage supply system, and a semiconductor device manufacturing method capable of improving ESD tolerance.

(First embodiment)
FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment shown in FIG. FIG. 3 is a circuit diagram of an internal circuit of the semiconductor device according to the first embodiment shown in FIG. FIG. 4 is a plan view of a protection element included in the electrostatic protection circuit of the semiconductor device according to the first embodiment shown in FIG. FIG. 5 is a view for explaining the position of each electrode pad provided in the semiconductor device according to the first embodiment shown in FIG. First, the structure of the semiconductor device according to the first embodiment will be described with reference to FIGS. The semiconductor device according to the first embodiment is used for a voltage supply system and the like.

  As shown in FIGS. 1 and 2, the semiconductor device 20 according to the first embodiment includes an internal circuit 1 and an electrostatic protection circuit 2 for protecting the internal circuit 1 from static electricity on the same p-type semiconductor substrate 3. It has a formed structure. The internal circuit 1 according to the first embodiment is a CMOS circuit as shown in FIG. 3 and includes an NMOS transistor 31 and a PMOS transistor 32. The BVdss breakdown voltage (source-drain breakdown voltage) of the NMOS transistor 31 and the PMOS transistor 32 is set to about 15 V, for example.

  As a specific structure, as shown in FIG. 2, the p-type semiconductor substrate 3 has at least two types of regions 3a and 3b. The internal circuit 1 is disposed in the region 3 a of the p-type semiconductor substrate 3, and the electrostatic protection circuit 2 is disposed in the region 3 b of the p-type semiconductor substrate 3.

In the region 3a of the p-type semiconductor substrate 3, a p-type well diffusion region 4 having a diffusion depth of about 4 μm and an n-type well diffusion region 5 having a diffusion depth of about 4 μm are formed. The p-type well diffusion region 4 is a region in which a p-type impurity such as boron is ion-implanted into the p-type semiconductor substrate 3 with an implantation amount of about 6.0 × 10 ¹² ions / cm ² . It has a p-type impurity concentration suitable for Vth (threshold voltage). The n-type well diffusion region 5 is a region in which an n-type impurity such as phosphorus is ion-implanted into the p-type semiconductor substrate 3.

  In addition, a pair of n-type regions 6a and 6b are formed in the p-type well diffusion region 4 so as to face each other at a predetermined interval, and the n-type well diffusion region 5 has a predetermined value. A pair of p-type regions 7a and 7b facing each other is formed. Further, on the region between the n-type region 6a and the n-type region 6b of the p-type semiconductor substrate 3, a polysilicon film 9 (9a) is interposed via a thermal oxide film 8 (8a) having a thickness of about 15 nm. Is formed. Further, on the region between the p-type region 7a and the p-type region 7b of the p-type semiconductor substrate 3, a polysilicon film 9 (9b) is interposed via a thermal oxide film 8 (8b) having a thickness of about 15 nm. Is formed.

  The NMOS transistor 31 included in the internal circuit 1 includes a p-type well diffusion region 4, a pair of n-type regions (source / drain regions) 6a and 6b, a thermal oxide film (gate insulating film) 8a, polysilicon And a film (gate electrode) 9a. The PMOS transistor 32 included in the internal circuit 1 includes an n-type well diffusion region 5, a pair of p-type regions (source / drain regions) 7a and 7b, a thermal oxide film (gate insulating film) 8b, and polysilicon. And a film (gate electrode) 9b. The NMOS transistor 31 and the PMOS transistor 32 are isolated from each other by the LOCOS oxide film 10 (10a).

  1 to 3, the n-type region (source region) 6 a of the NMOS transistor 31 is connected to the GND terminal (ground terminal) on the low potential side and the p-type region of the PMOS transistor 32. (Source region) 7a is connected to a high potential side Vcc terminal (power supply voltage terminal). The polysilicon film (gate electrode) 9a of the NMOS transistor 31 and the polysilicon film (gate electrode) 9b of the PMOS transistor 32 are connected to the Vin terminal (input terminal) and the n-type region ( The drain region 6b and the p-type region (drain region) 7b of the PMOS transistor 32 are connected to the Vout terminal (output terminal). The p-type well diffusion region 4 of the NMOS transistor 31 is connected to the GND terminal, and the n-type well diffusion region 5 of the PMOS transistor 32 is connected to the Vcc terminal. The Vin terminal is an example of the “predetermined terminal to be protected” in the present invention.

  As shown in FIG. 1, the electrostatic protection circuit 2 includes a plurality of protection elements 41 to 45. The plurality of protection elements 41 to 45 are substantially the same as the protection elements 41 to 43 having substantially the same structure as the structure in which the gate electrode is omitted from the NMOS transistor, and the structure in which the gate electrode is omitted from the PMOS transistor. The protective elements 44 and 45 having a structure are classified into two types. In FIG. 1, for the sake of convenience, the protection elements 41 to 45 are represented by circuit symbols of MOS transistors.

  As shown in FIG. 2, the protection element 41 included in the electrostatic protection circuit 2 includes a p-type well diffusion region 11 formed in the region 3b of the p-type semiconductor substrate 3 to have a diffusion depth of about 4 μm, The p-type well diffusion region 11 has at least a pair of n-type regions 12a and 12b formed to face each other with a predetermined gap therebetween. The n-type regions 12a and 12b are separated from each other by the LOCOS oxide film 10 (10b). The n-type regions 12a and 12b are examples of the “first n-type region” and the “second n-type region” in the present invention, respectively.

Here, in the first embodiment, in the p-type well diffusion region 11, p-type impurities such as boron are about 7 × 10 ¹³ ions / cm ² or more (for example, about 1.0 × The ion-implanted region is formed with an implantation amount of 10 ¹⁴ ions / cm ² . That is, the p-type impurity concentration of the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2 is higher than the p-type impurity concentration of the p-type well diffusion region 4 of the NMOS transistor 31 included in the internal circuit 1. It has become. In the first embodiment, the junction breakdown voltage between the p-type well diffusion region 11 and the n-type region 12b of the protection element 41 is about 10 V, and the BVdss of the NMOS transistor 31 and the PMOS transistor 32 included in the internal circuit 1 It is lower than the breakdown voltage (about 15V). Furthermore, the current amplification factor of the parasitic bipolar transistor (an NPN transistor constituted by the p-type well diffusion region 11 and the pair of n-type regions 12a and 12b) of the protection element 41 is about 2.

  In the first embodiment, the protection element 41 further includes an n-type well diffusion region 13 formed in the region 3 b of the p-type semiconductor substrate 3. The end of the n-type region 12 b opposite to the end facing the n-type region 12 a is disposed inside the n-type well diffusion region 13. That is, the end of the n-type region 12 b opposite to the end facing the n-type region 12 a is protected by the n-type well diffusion region 13. Note that the region indicated by reference numeral 14 in FIG. 2 is a p-type region. A thermal oxide film 8 (8c) having a thickness of about 15 nm is formed on the region 3b of the p-type semiconductor substrate 3.

  As shown in FIGS. 1 and 2, the protection element 41 is connected between the GND terminal and the Vin terminal. Specifically, the n-type region 12a of the protection element 41 is connected to the GND terminal, and the n-type region 12b of the protection element 41 is connected to the Vin terminal. The p-type well diffusion region 11 (p-type region 14) of the protection element 41 is connected to the GND terminal.

  Further, as shown in FIG. 4, the protection element 41 includes a plurality of element portions 41a each having at least a p-type well diffusion region 11 and a pair of n-type regions 12a and 12b. The plurality of element portions 41a of the protection element 41 are arranged in parallel with each other when seen in a plan view. The n-type regions 12a of the plurality of element portions 41a of the protection element 41 are connected to the GND terminal, and the n-type regions 12b of the plurality of element portions 41a of the protection element 41 are connected to the Vin terminal. ing. The series resistance component of each of the plurality of element portions 41a of the protection element 41 is set to about 180Ω.

  Further, the protection elements 42 and 43 shown in FIG. 1 have the same structure as the protection element 41 described above. The protective element 42 is connected between the GND terminal and the Vout terminal, and the protective element 43 is connected between the GND terminal and the Vcc terminal.

  Further, although not shown, the protection elements 44 and 45 shown in FIG. 1 include an n-type well diffusion region and a pair of p-type regions facing each other at a predetermined interval inside the n-type well diffusion region. Have at least. The protective element 44 is connected between the Vcc terminal and the Vin terminal, and the protective element 45 is connected between the Vcc terminal and the Vout terminal. The protection elements 44 and 45 cannot have the same structure as the protection element 41 whose back gate is GND.

  By the way, as shown in FIG. 5, the electrode pad 21 corresponding to the GND terminal, the electrode pad 22 corresponding to the Vcc terminal, the electrode pad 23 corresponding to the Vin terminal, and the electrode pad 24 corresponding to the Vout terminal are formed in the wire bonding process. Arranged in consideration of workability. Specifically, the electrode pads 21 to 24 are arranged at the four corners of the semiconductor device (chip) 20, respectively. The electrode pads 21, 22 and 23 are examples of the “first electrode pad”, the “second electrode pad” and the “third electrode pad” in the present invention, respectively.

  6 and 7 are diagrams for explaining the operation of the semiconductor device according to the first embodiment of the present invention. Next, the operation of the semiconductor device according to the first embodiment will be described with reference to FIGS. The broken lines in FIGS. 6 and 7 represent ESD (electrostatic discharge) current paths.

  First, as shown in FIG. 6, when an ESD surge of about +400 V is applied to the Vin terminal with respect to the GND terminal, the voltage at the Vin terminal rises to about 10 V. At this time, since an avalanche breakdown occurs between the p-type well diffusion region 11 (see FIG. 2) and the n-type region 12b (see FIG. 2) of the protection element 41, the voltage at the Vin terminal is clamped at about 10V. . Therefore, the ESD current does not flow into the internal circuit 1 having a BVdss withstand voltage of about 15 V, but flows out via the protection element 41 and the path R2 connecting the Vin terminal and the GND terminal. At this time, since the protection element 43 operates in the same manner as the protection element 41, there is an ESD current that flows out via the path R1 connecting the Vin terminal and the GND terminal via the protection elements 43 and 44.

  When an ESD surge of about −400 V is applied to the Vin terminal with respect to the GND terminal, the p-type well diffusion region 11 (see FIG. 2) and the n-type region 12b (see FIG. 2) of the protection element 41 A forward bias is applied to the diode constituted by Therefore, the ESD current does not flow into the internal circuit 1 but flows out through the protection element 41 and the path R2 connecting the Vin terminal and the GND terminal.

  Next, as shown in FIG. 7, when an ESD surge of about +400 V is applied to the Vin terminal with respect to the Vcc terminal, the diode constituted by the n-type well diffusion region and the p-type region of the protective element 44 Thus, a forward bias is applied. For this reason, the ESD current does not flow into the internal circuit 1 but flows out via the protection element 44 via the path R3 connecting the Vin terminal and the Vcc terminal.

  Further, when an ESD surge of about −400 V is applied to the Vin terminal with respect to the Vcc terminal, if snapback occurs in the protection element 44, a path connecting the Vin terminal and the Vcc terminal via the protection element 44. ESD current flows out through R3. However, since the protective element 44 has a structure in which a current is generated when holes move, snapback hardly occurs. Therefore, in this case, the ESD current flows out via the protection element 41 and 43 and the path R4 connecting the Vin terminal and the Vcc terminal.

  8 to 12 are cross-sectional views for explaining the semiconductor device manufacturing method according to the first embodiment of the present invention. Next, with reference to FIGS. 2 and 8 to 12, the method for manufacturing the semiconductor device according to the first embodiment will be described.

  First, as shown in FIG. 8, a predetermined region (region for forming the n-type well diffusion region 5 of the PMOS transistor 32 included in the internal circuit 1) in the region 3 a of the p-type semiconductor substrate 3 and the p-type semiconductor substrate 3. An n-type impurity such as phosphorus is ion-implanted into a predetermined region of the region 3b (a region where the n-type well diffusion region 13 of the protection element 41 included in the electrostatic protection circuit 2 is formed).

Subsequently, a p-type impurity such as boron is ion-implanted only in a predetermined region of the region 3 a of the p-type semiconductor substrate 3 (region where the p-type well diffusion region 4 of the NMOS transistor 31 included in the internal circuit 1 is formed). At this time, the implantation amount of the p-type impurity is set to about 6.0 × 10 ¹² ions / cm ² .

Next, as shown in FIG. 9, boron or the like is formed only in a predetermined region of the region 3 b of the p-type semiconductor substrate 3 (region where the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2 is formed). A p-type impurity is ion-implanted. At this time, the implantation amount of the p-type impurity is set to about 7 × 10 ¹³ ions / cm ² or more (for example, about 1.0 × 10 ¹⁴ ions / cm ² ). That is, in the ion implantation process when forming the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2, the p-type well diffusion region 4 of the NMOS transistor 31 included in the internal circuit 1 is formed. The implantation amount of the p-type impurity is increased as compared with the ion implantation process.

  In the first embodiment, as described above, the ion implantation for forming the p-type well diffusion region 4 of the NMOS transistor 31 included in the internal circuit 1 and the p-type well diffusion of the protection element 41 included in the electrostatic protection circuit 2 are performed. By performing ion implantation for forming the region 11 in separate steps, the p-type impurity concentration of the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2 can be easily set. Can be made higher than the p-type impurity concentration of the p-type well diffusion region 4 of the NMOS transistor 31 included in the transistor.

  Thereafter, the p-type semiconductor substrate 3 is subjected to heat treatment. Thereby, the p-type well diffusion region 4 of the NMOS transistor 31 and the n-type well diffusion region 5 of the PMOS transistor 32 included in the internal circuit 1, the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2, and An n-type well diffusion region 13 is formed.

  Next, as shown in FIG. 10, a thermal oxide film 15 having a thickness of about 15 nm is formed on the upper surface of the p-type semiconductor substrate 3 by thermally oxidizing the entire upper surface of the p-type semiconductor substrate 3. Then, the SiN film 16 is formed on a predetermined portion (a portion corresponding to the active region) on the upper surface of the thermal oxide film 15 by using a CVD (chemical vapor deposition) method and a dry etching technique.

  Next, as shown in FIG. 11, a LOCOS oxide film (thermal oxide film) 10 is formed using a LOCOS method. Thereafter, the SiN film 16 is removed.

  Next, as shown in FIG. 12, by thermally oxidizing the upper surface of the p-type semiconductor substrate 3 again, a thermal oxide film 8 that becomes a gate insulating film or the like is formed on the upper surface of the p-type semiconductor substrate 3 with a thickness of about 15 nm. Form. Subsequently, a polysilicon film 9 to be a gate electrode is formed on a predetermined portion on the upper surface of the thermal oxide film 8 by using a CVD method and a dry etching technique. Then, n-type impurities and p-type impurities are ion-implanted into the p-type semiconductor substrate 3 using the polysilicon film 9, the LOCOS oxide film 10 and a resist (not shown) as a mask. Thereafter, the p-type semiconductor substrate 3 is subjected to a heat treatment to form a structure as shown in FIG.

  The protection elements 42 and 43 included in the electrostatic protection circuit 2 are formed using a manufacturing method similar to the manufacturing method of the protection element 41 described above. Although not shown, the protection elements 44 and 45 included in the electrostatic protection circuit 2 are formed using a known manufacturing method.

  Further, ion implantation for forming the p-type well diffusion region 4 of the NMOS transistor 31 included in the internal circuit 1 and ion implantation for forming the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2. The following procedure may be used.

  That is, the p-type well diffusion region 4 of the NMOS transistor 31 included in the internal circuit 1 and the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2 are both p-type. After ion implantation of the p-type impurity, the p-type impurity may be ion-implanted again only in a region where the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2 is formed. Even in this case, the p-type impurity concentration of the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2 can be easily set to the value of the p-type well diffusion region 4 of the NMOS transistor 31 included in the internal circuit 1. It can be higher than the p-type impurity concentration.

  In the first embodiment, as described above, the p-type impurity concentration of the p-type well diffusion region 11 of the protection element 41 (42, 43) included in the electrostatic protection circuit 2 is set to the value of the NMOS transistor 31 included in the internal circuit 1. By making the concentration higher than the p-type impurity concentration of the p-type well diffusion region 4, the junction withstand voltage of the protection element 41 (42, 43) included in the electrostatic protection circuit 2 is changed to the junction withstand voltage of the NMOS transistor 31 included in the internal circuit 1. Can be lower. In this case, even if an ESD surge is applied to the semiconductor device 20, the ESD current flows out through the protection element 41 (42, 43) having a low junction breakdown voltage of the electrostatic protection circuit 2, so that the ESD current flows into the internal circuit 1. Inflow can be suppressed. As a result, damage to the internal circuit 1 due to the ESD surge being applied to the semiconductor device 20 can be suppressed. That is, the ESD resistance of the semiconductor device 20 can be improved.

  In the first embodiment, the end of the n-type region 12b of the protection element 41 opposite to the end facing the n-type region 12a is disposed inside the n-type well diffusion region 13 as described above. By doing so, the end of the n-type region 12b opposite to the end facing the n-type region 12a can be protected by the n-type well diffusion region 13. Thereby, when an ESD surge is applied to the semiconductor device 20, a location where the avalanche breakdown generated between the p-type well diffusion region 11 and the n-type region 12b of the protection element 41 is abnormal (n of the n-type region 12b) It is possible to suppress the occurrence in the vicinity of the end opposite to the end facing the mold region 12a.

  In the first embodiment, as described above, the ESD resistance of the semiconductor device 20 can be further improved by setting the series resistance component of each of the plurality of element portions 41a of the protection element 41 to about 180Ω. it can. Here, when the series resistance component of each of the plurality of element portions 41a of the protection element 41 is small, the following inconvenience occurs. In other words, when the resistance value of the n-type region 12b of the protection element 41 is small, the time constant of the protection element 41 becomes small and the high speed operation is performed. Therefore, when an ESD surge with a steep time constant is applied, snapback is performed. Uniformity cannot be maintained in the flow of the ESD current flowing out due to the characteristics, and the ESD current does not flow uniformly in all the element portions 41a of the protection element 41. Therefore, among the plurality of element portions 41a of the protection element 41, the ESD current is concentrated on a specific element portion (element portion disposed at the end) 41a, and the ESD resistance is reduced.

  In the first embodiment, as described above, the junction breakdown voltage between the p-type well diffusion region 11 and the n-type region 12b of the protection element 41 is about 10 V, and the parasitic bipolar transistor (p (NPN transistor composed of the n-type well diffusion region 11 and the pair of n-type regions 12a and 12b) is configured to have a current amplification factor of about 2, and thus the protection element 41 itself is deteriorated. Generation | occurrence | production can be suppressed.

  In the configuration of the first embodiment described above, the internal circuit 1 includes only the p-type impurity concentration of the portion of the protection element 41 included in the electrostatic protection circuit 2 that is in contact with the n-type region 12b of the p-type well diffusion region 11. Alternatively, the p-type impurity concentration of the p-type well diffusion region 4 of the NMOS transistor 31 may be higher. With this configuration, the parasitic capacitance can be reduced as compared with the case where the p-type impurity concentration in all parts of the p-type well diffusion region 11 of the protection element 41 is increased. Become advantageous.

  In the configuration of the first embodiment described above, the structure of the protective element 44 on the high potential side (Vcc terminal side) connected to the Vin terminal may be an NPN transistor structure or a diode structure. If comprised in this way, the occupation area of the protection element 44 can be made small. In the first embodiment, since the protection element 44 only needs to have a function as a forward diode, there is no problem even if the protection element 44 has an NPN transistor structure or a diode structure.

  Further, when the occupation area of the protection element 44 is reduced, it is preferable that the junction breakdown voltage of the protection element 44 is higher than the junction breakdown voltage of the protection element 41. With this configuration, it is possible to prevent the ESD current from concentrating on the protective element 44 designed to have a small area before the protective element 41. For this reason, even if the occupation area of the protection element 44 is reduced, it is possible to suppress the deterioration of the protection element 44. If the junction breakdown voltage of the protection element 44 designed to have a small area is lower than the junction breakdown voltage of the protection element 41, the ESD current is concentrated on the protection element 44 designed to have a smaller area before the protection element 41. . In that case, the protection element 44 having a small allowable current may be unable to withstand the damage caused by the ESD current flowing and may deteriorate.

  In the configuration of the first embodiment described above, the protection element 43 connected between the GND terminal and the Vcc terminal may be configured to have a larger current path than other protection elements. If comprised in this way, the following effects can be acquired. That is, when there are many terminals to be protected, the ESD resistance can be improved by increasing the current path of the protective element connected to each terminal to be protected. However, in this case, the chip area is enlarged and the cost is increased. It becomes a factor of up. On the other hand, when there are many terminals to be protected, if the current path of the protection element 43 connected between the GND terminal and the Vcc terminal is increased, the current path of the protection element connected to each terminal to be protected is increased. Even if it is not increased, ESD resistance can be improved.

  FIG. 13 is a graph showing the relationship between the ion implantation amount and the junction breakdown voltage in the p-type well diffusion region of the protection element included in the electrostatic protection circuit, and FIG. 14 shows the p-type of the protection element included in the electrostatic protection circuit. It is the graph which showed the relationship between the amount of ion implantation in a well diffusion area | region, and a current gain. Next, with reference to FIG. 13 and FIG. 14, the result of confirming the effect of the first embodiment described above will be described.

  In the following description, the ion implantation amount is an ion implantation amount of a p-type impurity when forming the p-type well diffusion region 11 of the protection element 41 included in the electrostatic protection circuit 2 shown in FIG. Further, the junction breakdown voltage is a junction breakdown voltage between the p-type well diffusion region 11 and the n-type region 12b of the protection element 41 included in the electrostatic protection circuit 2 shown in FIG.

  First, as shown in FIG. 13, it can be seen that the junction breakdown voltage decreases as the amount of ion implantation increases. When the ion implantation amount is set so that the junction withstand voltage is about 15 V (the BVdss withstand voltage of the NMOS transistor 31 included in the internal circuit 1) or more, an ESD surge of about 400 V is applied to the semiconductor device 20. As a result, the NMOS transistor 31 included in the internal circuit 1 is damaged and a leak current is generated (see a square in FIG. 13). On the other hand, when the ion implantation amount was increased so that the junction breakdown voltage was less than about 15 V, it was possible to suppress the inconvenience as described above (see Δ mark and ○ mark in FIG. 13).

  By the way, when the ion implantation amount is set so that the junction withstand voltage is less than about 15V, if the junction withstand voltage exceeds about 10V, the protection element 41 itself deteriorates and a leak current is generated. (See the Δ mark in FIG. 13). On the other hand, when the ion implantation amount was set so that the junction breakdown voltage was about 10 V or less, the deterioration of the protective element 41 itself could be suppressed (see the circles in FIG. 13).

  As described above, if only the internal circuit 1 needs to be protected, the junction withstand voltage may be made slightly smaller than about 15 V (the BVdss withstand voltage of the NMOS transistor 31 included in the internal circuit 1) (for example, the junction withstand voltage may be reduced to about In this case, the protection element 41 itself deteriorates due to the ESD current concentrated on the protection element 41. As a result of investigating the deterioration portion of the protection element 41, it was found that the deterioration of the protection element 41 occurs at the end of the n-type region 12b of the protection element 41 facing the n-type region 12a. This is because, when an avalanche breakdown occurs between the p-type well diffusion region 11 and the n-type region 12b of the protection element 41, the parasitic bipolar transistor (the p-type well diffusion region 11 and the pair of n-type regions 12a and 12b are configured). The NPN transistor is turned on and a large current flows from the n-type region 12b to the n-type region 12a, so that the current is concentrated at the end of the n-type region 12b facing the n-type region 12a. It is done.

  Here, as shown in FIG. 14, the current amplification factor of the parasitic bipolar transistor (NPN transistor constituted by the p-type well diffusion region 11 and the pair of n-type regions 12a and 12b) of the protection element 41 is determined by the ion implantation amount. It turns out that it decreases with increasing. For this reason, if the amount of ion implantation is increased, rapid current concentration in the protection element 41 is suppressed, so that the strength of the protection element 41 itself can be increased. Note that it is preferable that the current amplification factor of the parasitic bipolar transistor (the NPN transistor constituted by the p-type well diffusion region 11 and the pair of n-type regions 12a and 12b) of the protection element 41 is set to about 2 or less. It is done.

  FIG. 15 is a view for explaining the position of each electrode pad provided in the semiconductor device according to the first modification of the first embodiment. Referring to FIG. 15, in the first modification of the first embodiment, in the configuration of the first embodiment described above, the electrode pad 21 corresponding to the GND terminal is adjacent to the electrode pad 22 corresponding to the Vcc terminal. Are arranged. In addition, the other structure of the 1st modification of 1st Embodiment is the same as that of the said 1st Embodiment.

  In the 1st modification of 1st Embodiment, the failure | damage of the internal circuit 1 can be suppressed more by comprising as mentioned above.

  Here, an inconvenience when the electrode pads are arranged so as not to be close to each other will be described. That is, since the protective element is connected to each electrode pad via the metal wiring, if each electrode pad is arranged far away, the internal circuit is damaged due to a voltage increase due to the wiring resistance and the ESD current. For example, even if the ESD current is about 6A and the wiring resistance is a small value of about 1Ω, if the avalanche breakdown voltage of the protection element is about 10V, the total is about 16V. In this case, since a voltage is applied to the internal circuit having a BVdss withstand voltage of about 15 V, the internal circuit is damaged.

  FIG. 16 is a diagram for explaining the arrangement positions of the electrode pads provided in the semiconductor device according to the second modification of the first embodiment. Referring to FIG. 16, in the second modification of the first embodiment, in the configuration of the first embodiment described above, the electrode pad 21 corresponding to the GND terminal is close to the electrode pad 22 corresponding to the Vcc terminal. An electrode pad 23 corresponding to the Vin terminal, which is a terminal to be protected, is disposed adjacent to the electrode pads 21 and 22. In addition, the other structure of the 2nd modification of 1st Embodiment is the same as that of the said 1st Embodiment.

  As described above, it is more preferable that the electrode pad 23 corresponding to the Vin terminal which is a terminal to be protected is disposed in proximity to the electrode pad 21 corresponding to the GND terminal and the electrode pad 22 corresponding to the Vcc terminal. .

(Second Embodiment)
FIG. 17 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. Next, with reference to FIG. 17, the structure of the semiconductor device according to the second embodiment will be explained.

  In the second embodiment, as shown in FIG. 17, the structure of the protection element 41 included in the electrostatic protection circuit 2 is substantially the same as the structure of the NMOS transistor 31 included in the internal circuit 1. Specifically, in the second embodiment, the n-type regions 12a and 12b of the protection element 41 are not separated from each other by the LOCOS oxide film. A polysilicon film 9 (9c) serving as a gate electrode is formed on the region between the n-type region 12a and the n-type region 12b via a thermal oxide film 8 (8c). Further, the n-type region 12a and the polysilicon film (gate electrode) 9c of the protection element 41 are short-circuited so as to have the same potential. In addition, the other structure of 2nd Embodiment is the same as that of the said 1st Embodiment.

  In the second embodiment, the configuration as described above is similarly affected by variations in the manufacturing process, so that a semiconductor device excellent in mass productivity can be easily obtained.

(Third embodiment)
FIG. 18 is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention. Next, with reference to FIG. 18, the structure of the semiconductor device according to the third embodiment will be explained.

  In the third embodiment, as shown in FIG. 18, the structure of the protection element 41 included in the electrostatic protection circuit 2 is a structure in which the polysilicon film 9 (9c) is omitted from the protection element 41 of the above-described second embodiment. Is essentially the same. The remaining configuration of the third embodiment is similar to that of the aforementioned first embodiment.

  According to the third embodiment, since it is not necessary to form a LOCOS oxide film that separates the n-type regions 12a and 12b of the protection element 41 from each other, the heat generated when the LOCOS oxide film is formed is configured. Generation | occurrence | production of the junction leak resulting from stress can be suppressed. Further, since the polysilicon film to be the gate electrode is not formed, hot carriers generated by avalanche breakdown when an ESD surge is applied to the semiconductor device are not injected into the gate.

(Fourth embodiment)
19 and 20 are circuit diagrams of the semiconductor device according to the fourth embodiment of the present invention. Next, with reference to FIGS. 19 and 20, the structure of the semiconductor device according to the fourth embodiment will be explained.

  As shown in FIG. 19, the semiconductor device 50 according to the fourth embodiment includes an internal circuit 51 and an electrostatic protection circuit 52 for protecting the internal circuit 1 from static electricity. The internal circuit 51 is a CMOS circuit similar to the internal circuit 1 of the first embodiment shown in FIG. 3, and includes an NMOS transistor and a PMOS transistor. The BVdss withstand voltage of each of the NMOS transistor and the PMOS transistor included in the internal circuit 51 is set to about 15V, for example. Furthermore, the Vth (threshold voltage) of each of the NMOS transistor and the PMOS transistor included in the internal circuit 51 is set to about 0.7 V, for example.

  The electrostatic protection circuit 52 includes protective elements 61 to 63 made of NMOS transistors and protective elements 64 and 65 made of PMOS transistors. The gates of the protection elements 61 to 65 are connected so that the potential is the same as the potential on the drain side. The protective element 61 is connected between the GND terminal and the Vin terminal, and the protective element 62 is connected between the GND terminal and the Vout terminal. The protection element 63 is connected between the GND terminal and the Vcc terminal. The protective element 64 is connected between the Vcc terminal and the Vin terminal, and the protective element 65 is connected between the Vcc terminal and the Vout terminal.

  Here, in the fourth embodiment, the Vth of each of the protection elements (MOS transistors) 61 to 65 is equal to or higher than a predetermined voltage applied to the internal circuit 51 during normal operation, and the MOS transistor included in the internal circuit 51 Is set to be equal to or lower than the BVdss withstand voltage. For example, if the maximum voltage applied to the Vin terminal during normal operation is about 7V, the Vth of each of the protection elements (MOS transistors) 61 to 65 is within a range of about 7V to about 15V (for example, about 10V ). Thereby, when an ESD surge is applied to the semiconductor device 50, the protection elements (MOS transistors) 61 to 65 included in the electrostatic protection circuit 2 are turned on, and an ESD current flows into the electrostatic protection circuit 2. Therefore, it is possible to suppress the ESD current from flowing in.

  By the way, the Vth of the MOS transistor included in the internal circuit 51 is normally set to about 0.7V. For this reason, the protection elements (MOS transistors) 61 to 65 included in the electrostatic protection circuit 52 cannot be formed by a normal manufacturing method. Therefore, when forming the protection elements (MOS transistors) 61 to 65, channel doping is performed at a high concentration or the gate insulating film is thickened.

  As an operation of the semiconductor device 50 according to the fourth embodiment, when an ESD surge is applied to the Vin terminal with respect to the GND terminal, an ESD current flows out through the path R5 and the path R6 as shown in FIG. Is done. Further, when an ESD surge is applied to the Vin terminal with respect to the Vcc terminal, an ESD current flows out through the path R7 and the path R8 as shown in FIG.

  In the fourth embodiment, by configuring as described above, it is possible to increase resistance to an ESD surge without affecting the normal operation of the semiconductor device 50.

  FIG. 21 is a circuit diagram of a semiconductor device according to a modification of the fourth embodiment. Referring to FIG. 21, in the modification of the fourth embodiment, in the configuration of the fourth embodiment, each gate of protection elements (MOS transistors) 61 to 65 included in electrostatic protection circuit 52 is polysilicon. It is connected to the potential on the drain side through a protective resistor 66 composed of the above. In addition, the other structure of the modification of 4th Embodiment is the same as that of the said 4th Embodiment.

  In the modification of the fourth embodiment, the gate insulating films of the protection elements (MOS transistors) 61 to 65 are formed even when an ESD surge having a steep time constant is applied to the semiconductor device 50 by configuring as described above. Can be protected.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the above embodiment, the internal circuit is a CMOS circuit, but the present invention is not limited to this, and the internal circuit may be a circuit other than the CMOS circuit.

  In the above embodiment, the BVdss withstand voltage of the MOS transistor included in the internal circuit is set to about 15V. However, the present invention is not limited to this, and the BVdss withstand voltage of the MOS transistor included in the internal circuit is a value other than about 15V. There may be.

1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment shown in FIG. 1. FIG. 2 is a circuit diagram of an internal circuit of the semiconductor device according to the first embodiment shown in FIG. 1. FIG. 2 is a plan view of a protection element included in the electrostatic protection circuit of the semiconductor device according to the first embodiment shown in FIG. 1. It is a figure for demonstrating the arrangement position of each electrode pad provided in the semiconductor device by 1st Embodiment shown in FIG. It is a figure for demonstrating operation | movement of the semiconductor device by 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device by 1st Embodiment of this invention. It is the graph which showed the relationship between the amount of ion implantation in the p-type well diffusion area | region of a protection element contained in an electrostatic protection circuit, and junction withstand voltage. It is the graph which showed the relationship between the amount of ion implantation in the p-type well diffusion area | region of a protection element contained in an electrostatic protection circuit, and a current gain. It is a figure for demonstrating the arrangement position of each electrode pad provided in the semiconductor device by the 1st modification of 1st Embodiment. It is a figure for demonstrating the arrangement position of each electrode pad provided in the semiconductor device by the 2nd modification of 1st Embodiment. It is sectional drawing of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device by 3rd Embodiment of this invention. It is a circuit diagram of the semiconductor device by 4th Embodiment of this invention. It is a circuit diagram of the semiconductor device by 4th Embodiment of this invention. It is a circuit diagram of the semiconductor device by the modification of 4th Embodiment.

Explanation of symbols

1, 51 Internal circuit 2, 52 Static electricity protection circuit 3 p-type semiconductor substrate (semiconductor substrate)
4, 11 p-type well diffusion region 9c polysilicon film (gate electrode)
12a n-type region (first n-type region)
12b n-type region (second n-type region)
13 n-type well diffusion region 20, 50 semiconductor device 31 NMOS transistor 32 PMOS transistor 41, 42, 43, 61, 62, 63, 64, 65 protection element 41a element part 66 protection resistance

Claims (19)

An internal circuit formed on a semiconductor substrate and including at least an NMOS transistor;
A first n-type formed on the semiconductor substrate and having a function of protecting the internal circuit from static electricity, and facing the p-type well diffusion region and the p-type well diffusion region with a predetermined distance therebetween An electrostatic protection circuit including at least a protection element having a region and a second n-type region,
At least part of the p-type well diffusion region of the protection element included in the electrostatic protection circuit is configured to have a higher p-type impurity concentration than the p-type well diffusion region of the NMOS transistor included in the internal circuit. A semiconductor device. The protective element further includes an n-type well diffusion region,
2. The end portion of the second n-type region of the protection element opposite to the end portion facing the first n-type region is disposed in the n-type well diffusion region. Semiconductor device.   2. The p-type impurity concentration of only the portion of the protection element in contact with the second n-type region of the p-type well diffusion region is higher than that of the p-type well diffusion region of the NMOS transistor included in the internal circuit. Or the semiconductor device according to 2; An NPN transistor is constituted by the p-type well diffusion region, the first n-type region and the second n-type region of the protection element,
The semiconductor device according to claim 1, wherein a current amplification factor of the NPN transistor of the protection element is set to 2 or less.   The semiconductor device according to claim 1, wherein a junction breakdown voltage between the p-type well diffusion region and the second n-type region of the protection element is set to 10 V or less. 6. The p-type well diffusion region of the protection element comprises a predetermined region of the semiconductor substrate into which p-type impurities are ion-implanted with an implantation amount of 7 × 10 ¹³ ions / cm ² or more. The semiconductor device according to any one of the above. The protective element includes a plurality of element portions having the p-type well diffusion region, the first n-type region, and the second n-type region,
2. The plurality of element portions of the protection element are arranged in parallel with each other, and the series resistance component of each of the plurality of element portions of the protection element is set to 180Ω or more. The semiconductor device in any one of -6. The protection element further includes a gate electrode formed on a region between the first n-type region and the second n-type region,
The semiconductor device according to claim 1, wherein the first n-type region and the gate electrode of the protection element are short-circuited to have the same potential.   8. The semiconductor device according to claim 1, wherein a gate electrode is not formed on a region between the first n-type region and the second n-type region of the protection element. The electrostatic protection circuit further includes an NPN transistor or a diode,
The protective element is connected between a ground terminal on the low potential side and a predetermined terminal to be protected,
The semiconductor device according to claim 1, wherein the NPN transistor or the diode is connected between a power supply voltage terminal on a high potential side and the predetermined terminal to be protected.   The NPN transistor or the diode connected between the power supply voltage terminal and the predetermined terminal to be protected has a higher junction breakdown voltage than the protective element connected between the ground terminal and the predetermined terminal to be protected. The semiconductor device according to claim 10, wherein the semiconductor device is configured to be high. The protection element is connected between a ground terminal and a predetermined terminal to be protected, and between the ground terminal and a power supply voltage terminal,
The protection element connected between the ground terminal and the power supply voltage terminal is configured to have a larger current path than the protection element connected between the ground terminal and the predetermined terminal to be protected. The semiconductor device according to claim 1, wherein the semiconductor device is formed. An internal circuit formed on a semiconductor substrate and including at least a MOS transistor;
An electrostatic protection circuit formed on the semiconductor substrate, having a function of protecting the internal circuit from static electricity, and including at least a protection element made of a MOS transistor,
The MOS transistors included in the electrostatic protection circuit are connected so that the potential of the gate is the same as the potential on the drain side,
The threshold voltage of the MOS transistor included in the electrostatic protection circuit is set to be equal to or higher than a predetermined voltage applied during normal operation and lower than the breakdown voltage between the source and drain of the MOS transistor included in the internal circuit.
When static electricity is applied, the MOS transistor included in the static electricity protection circuit is turned on to cause static electricity to flow into the static electricity protection circuit, thereby preventing static electricity from flowing into the internal circuit. A semiconductor device characterized by comprising:   14. The semiconductor device according to claim 13, wherein the gate of the MOS transistor included in the electrostatic protection circuit is connected to a drain-side potential through a protective resistor. A first electrode pad corresponding to the ground terminal and a second electrode pad corresponding to the power supply voltage terminal;
The semiconductor device according to claim 1, wherein the first electrode pad and the second electrode pad are disposed close to each other. A first electrode pad corresponding to the ground terminal, a second electrode pad corresponding to the power supply voltage terminal, and a third electrode pad corresponding to the predetermined terminal to be protected;
The semiconductor device according to claim 1, wherein the first electrode pad, the second electrode pad, and the third electrode pad are arranged close to each other.   A voltage supply system comprising the semiconductor device according to claim 1. Forming an internal circuit including at least an NMOS transistor on a semiconductor substrate;
The semiconductor substrate has a function of protecting the internal circuit from static electricity, and a p-type well diffusion region and a first n-type region facing each other at a predetermined interval in the p-type well diffusion region, and Forming an electrostatic protection circuit including at least a protection element having a second n-type region,
The step of forming the internal circuit includes a step of ion-implanting p-type impurities only in a region for forming a p-type well diffusion region of an NMOS transistor included in the internal circuit,
The step of forming the electrostatic protection circuit includes the step of forming at least a part of the p-type well diffusion region of the protection element included in the electrostatic protection circuit more than the p-type impurity concentration of the p-type well diffusion region of the NMOS transistor included in the internal circuit. The method for manufacturing a semiconductor device includes a step of ion-implanting a p-type impurity only in a region where a p-type well diffusion region of a protection element included in the electrostatic protection circuit is formed. Forming an internal circuit including at least an NMOS transistor on a semiconductor substrate;
The semiconductor substrate has a function of protecting the internal circuit from static electricity, and a p-type well diffusion region and a first n-type region facing each other at a predetermined interval in the p-type well diffusion region, and Forming an electrostatic protection circuit including at least a protection element having a second n-type region,
The step of forming the internal circuit includes a region for forming a p-type well diffusion region of an NMOS transistor included in the internal circuit and a region for forming a p-type well diffusion region of a protection element included in the electrostatic protection circuit. A step of ion-implanting a p-type impurity in both of them,
The step of forming the electrostatic protection circuit includes the step of forming at least a part of the p-type well diffusion region of the protection element included in the electrostatic protection circuit more than the p-type impurity concentration of the p-type well diffusion region of the NMOS transistor included in the internal circuit. And a step of ion-implanting the p-type impurity again only in a region where the p-type well diffusion region of the protection element included in the electrostatic protection circuit is formed. .

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