JP2006074012A - Bidirectional type electrostatic discharge protection element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To optionally set trigger voltages to ESDs of positive polarity and negative polarity. <P>SOLUTION: A bidirectional type electrostatic discharge protection element uses a lateral SCR appearing in a manufacturing process of a semiconductor integrated circuit in such a form that it is provided with: NPN transistors 1 and 3 with collector electrodes connected commonly and emitter electrodes connected with terminals 1q and 1r of the semiconductor integrated circuit; and a PNP transistor 2 with base electrodes connected with the collector electrode connection terminals of the NPN transistors 1 and 3 and the bidirectional emitter electrodes connected with the corresponding base electrodes of the NPN transistors 1 and 3 and connected with the corresponding emitter electrodes of the NPN transistors 1 and 3 through resistive elements R1 and R2. With the NPN transistors 1 and 3, NMOS transistors 4 and 5 are integrally formed in parallel, respectively. Gate electrodes of the NMOS transistors 4 and 5 are connected with the corresponding emitter electrodes of the NPN transistors 1 and 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bidirectional electrostatic discharge protection element used for electrostatic discharge protection in a semiconductor integrated circuit having a MOS structure.

  In particular, it is known that a semiconductor integrated circuit (IC) having a MOS structure is sensitive to static electricity and easily broken. Therefore, in the MOS structure IC, in order to protect the internal circuit from a high voltage (hereinafter simply referred to as “ESD”) due to electrostatic discharge (ESD) generated due to charging, it has been conventionally performed. An ESD protection circuit or an ESD protection element is provided between the input / output terminal of the IC and the ground terminal. As an ESD protection element, a lateral SCR (silicon controlled rectifier) that appears in a CMOS process is the most efficient ESD protection element with a small on-resistance, and various protection methods using it have been proposed (for example, Patent Documents 1 to 4).

  By the way, since the trigger voltage of the SCR depends on the P-type and N-type junction breakdown voltages, the trigger voltage in the horizontal SCR that appears in the CMOS process tends to be high. Therefore, in Non-Patent Document 1, for example, when a lateral SCR that appears in a CMOS process is configured as an ESD protection element, in order to reduce a trigger voltage that tends to be high without adding a mask or an implantation step, for example, FIG. As shown in FIG. 2, a structure in which NMOS transistors are combined has been proposed. 11 and 12 are an equivalent circuit and a cross-sectional structure diagram of a horizontal SCR used for positive ESD shown as Conventional Example 1. FIG.

  Non-Patent Document 1 also proposes a bidirectional lateral SCR that can protect against positive and negative ESD, as shown in FIGS. 13 and 14, for example. FIGS. 13 and 14 are an equivalent circuit and a cross-sectional structure diagram of a bidirectional lateral SCR that can cope with both the positive ESD and the negative ESD shown as Conventional Example 2. FIG. Here, in order to facilitate understanding of the present invention, a horizontal SCR will be described with reference to FIGS.

  In FIG. 12, an N-type diffusion layer (N +) 6w is formed on a P-type substrate (P−) 6x, and a P-type diffusion layer (P +) 6v as an element isolation layer is formed around the N-type diffusion layer 6w. Is provided. An N-type diffusion layer (N−) 6e formed by epitaxial growth is formed on the N-type diffusion layer 6w, and a P-type diffusion layer (P−) 6g which is a P well is formed in a partial region on the surface side.

  Above the junction between the N-type diffusion layer (N−) 6e and the P-type diffusion layer (P−) 6g, an N-type diffusion layer (N +) 6d constituting the drain region is formed straddling both sides. Above the diffusion layer (N +) 6d to the element isolation layer 6v on the N-type diffusion layer (N−) 6e side, a P-type diffusion layer constituting a back gate contact with an element isolation insulating film 6y interposed therebetween (P +) 6a and an N-type diffusion layer (N +) 6b constituting the source region are formed. The P-type diffusion layer (P +) 6a and the N-type diffusion layer (N +) 6b are connected to the terminal 6q.

  Further, a gate electrode 6p is provided above the P-type diffusion layer (P−) 6g on the N-type diffusion layer (N +) 6d side via an insulating film 6n, and the element isolation insulating film 6y is interposed therebetween. Thus, an N type diffusion layer (N +) 6h constituting a source region and a P type diffusion layer (P +) 6j constituting a back gate contact are formed. The gate electrode 6p, the N-type diffusion layer (N +) 6h, and the P-type diffusion layer (P +) 6j are connected to the terminal 6r.

  Here, in the configuration shown in FIG. 12, as the lateral SCR, on the terminal 6q side, the P-type diffusion layer (P +) 6a is used as the emitter electrode, the N-type diffusion layer (N−) 6e is used as the base electrode, and the P-type diffusion layer is used. A PNP transistor 11 shown in FIG. 11 having (P−) 6 g as a collector electrode is formed. Further, on the terminal 6r side, an N type diffusion layer (N +) 6d is used as a collector electrode, a P type diffusion layer (P−) 6g is used as a base electrode, and an N type diffusion layer (N +) 6h is used as an emitter electrode in FIG. The NPN transistor 10 shown is formed. At this time, the base electrode of the PNP transistor 11 and the collector electrode of the NPN transistor 10 are connected to the terminal 6q via the resistor element R11, and the base electrode of the NPN transistor 10 and the collector electrode of the PNP transistor 11 are connected to the terminal via the resistor element R12. 6r is connected to 6r.

  Furthermore, it is shown in FIG. 11 between the P-type substrate (P−) 6x and the N-type diffusion layer (N−) 6e, between the P-type diffusion layer (P−) 6g and the N-type diffusion layer (N +) 6d. The parasitic diode 13 shown is formed. Note that such a parasitic diode does not appear in an SOI (Silicon On Insulator) type MOS structure.

  The NMOS transistor 12 shown in FIG. 11 includes an N-type diffusion layer (N +) 6d as a drain region, an insulating film 6n, a gate electrode (conductive wiring) 6p, an N-type diffusion layer (N +) 6h as a source region, and a back gate. Since it is composed of a P-type diffusion layer (P +) 6j as a contact and a P-type diffusion layer (P−) 6g as a P-well, they are integrally provided in parallel with the NPN transistor 10.

  Next, the operation will be described. When the positive ESD is applied to the terminal 6q with reference to the terminal 6r, the voltage due to the positive ESD flows from the P-type diffusion layer (P +) 6a through the N-type diffusion layer (N−) 6e to the N-type diffusion layer ( N +) 6d is reached. The voltage due to this positive ESD is the junction breakdown voltage between the N type diffusion layer (N +) 6d and the P type diffusion layer (P−) 6g, and the N type diffusion layer (N +) 6d and the N type diffusion layer (N +) 6h. When the lower breakdown voltage of the drain-source breakdown voltage between the positive and negative electrodes is exceeded, the current due to the positive polarity ESD is changed to the terminal 6q → P type diffusion layer (P +) 6a → N type diffusion layer (N−) 6e → N type. Diffusion layer (N +) 6d → P type diffusion layer (P−) 6g → P type diffusion layer (P +) 6j or N type diffusion layer (N +) 6h → terminal 6r.

  When this current increases and exceeds the trigger voltage, the NPN transistor 10 is turned on. When this current further increases, the NPN transistor 11 is turned on and the current further increases. Therefore, the potential of the terminal 6q is lowered and the SCR operation state is entered. Since the current flowing by the positive ESD flows between the terminal 6q and the terminal 6r under a voltage lower than the trigger voltage, the internal circuit is protected.

  In FIG. 14, an N-type diffusion layer (N +) 7w is formed on a P-type substrate (P−) 7x, and a P-type diffusion layer (P +) as an inter-element isolation layer is formed around the N-type diffusion layer 7w. 7v is provided. An N-type diffusion layer (N−) 7e is formed on the N-type diffusion layer 7w, and a P-type diffusion layer (P−) 7c that is a P-well and an N-type diffusion layer that is an N-well are formed on the surface side region thereof. (N−) 7f and a P-type diffusion layer (P−) 7g which is a P well are formed.

  Above the P-type diffusion layer (P−) 7c, the P-type diffusion layer (P +) 7a constituting the back gate contact and the N-type diffusion layer (the source region) (with the element isolation insulating film 7y interposed therebetween) N +) 7b is formed. Above the P-type diffusion layer (P−) 7g, a P-type diffusion layer (P +) 7j constituting a back gate contact and an N-type diffusion constituting a source region are sandwiched between element isolation insulating films 7y. A layer (N +) 7h is formed. Further, an N-type diffusion layer (N +) 7d constituting a drain region is formed above the N-type diffusion layer (N−) 7f across the junction with both sides. The P-type diffusion layer (P +) 7a and the N-type diffusion layer (N +) 7b are connected to the terminal 7q. The N type diffusion layer (N +) 7h and the P type diffusion layer (P +) 7j are connected to the terminal 7r.

  Here, in the configuration shown in FIG. 14, as a lateral SCR, on the terminal 7q side, an N-type diffusion layer (N +) 7b is used as an emitter electrode, an N-type diffusion layer (N +) 7d is used as a collector electrode, and a P-type diffusion layer ( The NPN transistor 21 shown in FIG. 13 having the base electrode P-) 7c is formed. Further, on the terminal 7r side, an N type diffusion layer (N +) 7d is used as a collector electrode, an N type diffusion layer (N +) 7h is used as an emitter electrode, and a P type diffusion layer (P−) 7g is used as a base electrode in FIG. The NPN transistor 23 shown is formed.

  Between the two, an N-type diffusion layer (N +) 7d, an N-type diffusion layer (N-) 7e, or an N-type diffusion layer (N-) 7f is used as a base electrode, and a P-type diffusion layer (P- ) 7c is used as one emitter electrode, and the P-type diffusion layer (P−) 7g is used as the other emitter electrode to form the PNP transistor 22 shown in FIG. At this time, the emitter electrode of the PNP transistor 22 and the emitter electrodes of the NPN transistors 21 and 23 are connected via the resistance elements R21 and R22.

  Further, between the P-type substrate (P−) 7x and the N-type diffusion layer (N−) 7e, between the P-type diffusion layer (P−) 7g and the N-type diffusion layer (N−) 7f, FIG. The parasitic diode 24 shown in FIG. In the SOI type MOS structure, such a parasitic diode does not appear.

  Next, the operation will be described. When the positive ESD is applied to the terminal 7q with respect to the terminal 7r, the voltage due to the positive ESD is changed from the P-type diffusion layer (P +) 7a to the P-type diffusion layer (P−) 7c and the N-type diffusion layer (N + ) It reaches 7g of P-type diffusion layer (P-) via 7d. When the voltage generated by the positive ESD exceeds the junction breakdown voltage between the N-type diffusion layer (N +) 7d and the P-type diffusion layer (P-) 7g, the current due to the positive ESD is changed to the terminal 7q → P-type diffusion layer. (P +) 7a → P type diffusion layer (P−) 7c → N type diffusion layer (N +) 7d → P type diffusion layer (P−) 7g → P type diffusion layer (P +) 7j → terminal 7r.

  When this current increases and exceeds the trigger voltage, the NPN transistor 23 including the N-type diffusion layer (N +) 7d, the P-type diffusion layer (P−) 7g, and the N-type diffusion layer (N +) 7h operates. When this current further increases, the PNP transistor 22 including the P-type diffusion layer (P−) 7g, the N-type diffusion layer (N−) 7f, and the P-type diffusion layer (P−) 7c becomes the N-type diffusion layer (N + ) 7d and the N-type diffusion layer (N−) 7f, the current flows from the P-type diffusion layer (P−) 7c, and the current further increases. Therefore, the potential of the terminal 7q is lowered and the SCR operation state is entered. Since the current flowing through the positive ESD flows between the terminal 7q and the terminal 7r under a voltage lower than the trigger voltage, the internal circuit is protected.

  When negative polarity ESD is applied to the terminal 7q, the voltage due to the negative polarity ESD reaches the N type diffusion layer (N +) 7d via the P type diffusion layer (P +) 7a and the P type diffusion layer (P−) 7c. To do. When the voltage due to the negative polarity ESD exceeds the junction breakdown voltage between the N type diffusion layer (N +) 7d and the P type diffusion layer (P−) 7c, the current due to the negative polarity ESD is changed to the terminal 7r → P type diffusion layer (P +) 7j. → P type diffusion layer (P−) 7g → P type diffusion layer (P−) 7c → P type diffusion layer (P +) 7a → terminal 7q.

  When this current increases and exceeds the trigger voltage, the NPN transistor 21 including the N-type diffusion layer (N +) 7d, the P-type diffusion layer (P−) 7c, and the N-type diffusion layer (N +) 7b operates, and the terminal 7q Increases in potential (decreases in absolute value). When this current further increases, a PNP comprising a P-type diffusion layer (P-) 7g, an N-type diffusion layer (N-) 7f, an N-type diffusion layer (N-) 7e, and a P-type diffusion layer (P-) 7c. Since the transistor 22 is also operated and the parasitic diode 24 is also turned on, the current is further increased. As a result, the potential of the terminal 7q increases (decreases in absolute value) and enters the SCR operation state.

JP 7-235604 A JP-A-8-37284 JP 2003-203985 A JP 7-183394 A "On-Chip Esd Protection for Integrated Circuit: An IC Design Prospective" (Kluuwer International Series in Engineering and Computer Science Secs663)

  However, in the conventional bidirectional ESD protection element, as described with reference to FIGS. 13 and 14, the trigger voltage is determined by the P-type and N-type junction breakdown voltages, so that the trigger voltage can be set without adding a mask or an implantation process. It is difficult to optimize.

  Further, in the case of having the trigger voltage control structure by the NMOS transistor only for the positive polarity ESD described in FIGS. 11 and 12, the trigger voltage for the negative polarity ESD is determined by the junction breakdown voltage of the P type and the N type. Even in this case, it is difficult to optimize the trigger voltage for negative polarity ESD without adding a mask or an injection process.

  The present invention has been made in view of the above, and has a structure in which positive and negative trigger voltages can be arbitrarily set when protective operation is performed for both positive polarity ESD and negative polarity ESD, and the device structure is miniaturized. It is an object to obtain a bidirectional electrostatic discharge protection element (bidirectional lateral SCR) that can increase the ESD tolerance.

  To achieve the above object, the present invention provides a first and second bipolar transistor having a collector electrode connected in common and an emitter electrode connected to first and second terminals of a semiconductor integrated circuit, a base An electrode is connected to the collector electrode connection end of the first and second bipolar transistors, and a bidirectional emitter electrode is connected to the corresponding base electrode of the first and second bipolar transistors, and through a resistance element. Bidirectional static electricity using a bidirectional lateral SCR that appears in the manufacturing process of a semiconductor integrated circuit in a form including a third bipolar transistor connected to a corresponding emitter electrode of the first and second bipolar transistors A discharge protection element, wherein the first and second bipolar transistors are respectively connected in parallel with each other. And the second NMOS transistor is integrally formed, and the gate electrodes of the first and second NMOS transistors are connected to the corresponding emitter electrodes of the first and second bipolar transistors. To do.

  According to the present invention, when the high voltage due to electrostatic discharge applied to the terminal exceeds the drain-source breakdown voltage of the first and second NMOS transistors, the first and second lateral SCRs start operating. Since the structure of the second NMOS transistor can be determined, the positive and negative trigger voltages can be arbitrarily optimized without adding a mask or an implantation step.

  According to the present invention, it is possible to arbitrarily optimize the positive and negative trigger voltages for the bidirectional electrostatic discharge protection element using the bidirectional lateral SCR that appears in the manufacturing process of the semiconductor integrated circuit. Play.

  Exemplary embodiments of a bidirectional electrostatic discharge protection element (bidirectional lateral SCR) according to the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG.
1 and 2 are diagrams showing the configuration of a bidirectional electrostatic discharge protection element (bidirectional lateral SCR) according to Embodiment 1 of the present invention. 1 is an equivalent circuit diagram, and FIG. 2 is a cross-sectional view of a CMOS structure in which the bidirectional lateral SCR shown in FIG. 1 appears.

  In FIG. 2, an N-type diffusion layer (N +) 1w is formed on a P-type substrate (P−) 1x, and a P-type diffusion layer (P +) 1v as an element isolation layer is formed around the N-type diffusion layer 1w. Is provided. An N-type diffusion layer (N−) 1e is formed on the N-type diffusion layer (N +) 1w by epitaxial growth, and a P-type diffusion layer (P−) 1c, which is a P well, is formed on the surface side region of the N-type diffusion layer (N−) 1w. An N type diffusion layer (N−) 1f and a P type diffusion layer (P−) 1g which is a P well are formed.

  Above the P-type diffusion layer (P−) 1c, the P-type diffusion layer (P +) 1a constituting the back gate contact and the N-type diffusion layer constituting the source region (with the element isolation insulating film 1y interposed therebetween) N +) 1b is formed. Above the P-type diffusion layer (P−) 1g, a P-type diffusion layer (P +) 1j constituting a back gate contact and an N-type diffusion constituting a source region with an element isolation insulating film 1y interposed therebetween. A layer (N +) 1h is formed. Further, an N-type diffusion layer (N +) 1d that forms a drain region is formed above the N-type diffusion layer (N−) 1f across the junction with both sides.

  Above the P-type diffusion layer (P−) 1c interposed between the N-type diffusion layer (N +) 1d and the N-type diffusion layer (N +) 1b, a gate electrode (conductive wiring) is interposed via an insulating film 1k. ) 1m is provided, and an insulating film 1n is provided above the P-type diffusion layer (P−) 1g interposed between the N-type diffusion layer (N +) 1d and the N-type diffusion layer (N +) 1h. A gate electrode (conductive wiring) 1p is provided therethrough. The P-type diffusion layer (P +) 1a, the N-type diffusion layer (N +) 1b, and the gate electrode (conductive wiring) 1m are connected to the terminal 1q. The N-type diffusion layer (N +) 1h, the P-type diffusion layer (P +) 1j, and the gate electrode (conductive wiring) 1p are connected to the terminal 1r.

  Here, in the configuration shown in FIG. 2, as a lateral SCR, on the terminal 1q side, an N-type diffusion layer (N +) 1b is used as an emitter electrode, an N-type diffusion layer (N +) 1d is used as a collector electrode, and a P-type diffusion layer ( The NPN transistor 1 shown in FIG. 1 having P−) 1c as a base electrode is formed. Further, in FIG. 1, the N-type diffusion layer (N +) 1d is a collector electrode, the N-type diffusion layer (N +) 1h is an emitter electrode, and the P-type diffusion layer (P−) 1g is a base electrode on the terminal 1r side. The NPN transistor 3 shown is formed.

  Between the two, an N-type diffusion layer (N +) 1d, an N-type diffusion layer (N−) 1e, or an N-type diffusion layer (N−) 1f is used as a base electrode, and a P-type diffusion layer (P− 1) is used as one emitter electrode, and the PNP transistor 2 shown in FIG. 1 is formed using the P-type diffusion layer (P−) 1g as the other emitter electrode. At this time, the emitter electrode of the PNP transistor 2 and the emitter electrodes of the NPN transistors 1 and 3 are connected via the resistance elements R1 and R2.

  Furthermore, it is between the P-type substrate (P−) 1x and the N-type diffusion layer (N−) 1e, between the P-type diffusion layer (P−) 1g and the N-type diffusion layer (N−) 1f, etc. The parasitic diode 6 shown in FIG. Note that such a parasitic diode does not appear in an SOI (Silicon On Insulator) type MOS structure.

  The NMOS transistor 4 including the resistance element R1 shown in FIG. 1 includes an N-type diffusion layer (N +) 1d that is a drain region, an insulating film 1k, a gate electrode (conductive wiring) 1m, and an N-type diffusion layer (N +) that is a source region. ) 1b, a P-type diffusion layer (P +) 1a which is a back gate contact, and a P-type diffusion layer (P-) 1c which is a P-well, so that they are integrated in parallel with the NPN transistor 1.

  1 includes an N-type diffusion layer (N +) 1d that is a drain region, an insulating film 1n, a gate electrode (conductive wiring) 1p, and an N-type diffusion layer that is a source region. Since it is composed of (N +) 1h, P-type diffusion layer (P +) 1j, and P-type diffusion layer (P−) 1g which is a P-well, it is integrated in parallel with the NPN transistor 3.

  As described above, the bidirectional lateral SCR according to the first embodiment is an element in which the NMOS transistor 4 is arranged in parallel with the NPN transistor 1 on the terminal 1q side and the NMOS transistor 5 is arranged in parallel with the NPN transistor 3 on the terminal 1r side. It has a structure. According to this configuration, the trigger voltages for positive and negative ESD are individually changed by changing the structure of the NMOS transistors 4 and 5 (gate length, distance between the back gate contact and the source region, gate wiring). Adjustment can be set.

  Next, the operation will be described. When the positive ESD is applied to the terminal 1q with reference to the terminal 1r, the voltage due to the positive ESD passes through the P-type diffusion layer (P +) 1a and the P-type diffusion layer (P-) 1c (N-type diffusion layer ( N +) 1d is reached. At this time, the voltage due to the positive polarity ESD has a lower one of the junction breakdown voltage between the N-type diffusion layer (N +) 1d and the P-type diffusion layer (P−) 1g and the drain-source breakdown voltage of the NMOS transistor 5. If exceeded, the current due to the positive polarity ESD is changed to the terminal 1q → P type diffusion layer (P +) 1a → P type diffusion layer (P−) 1c → N type diffusion layer (N +) 1d → P type diffusion layer (P−) 1g. → P-type diffusion layer (P +) 1j or N-type diffusion layer (N +) 1h → terminal 1r.

  When this current increases and exceeds the trigger voltage, the NPN transistor 3 including the N-type diffusion layer (N +) 1d, the P-type diffusion layer (P−) 1g, and the N-type diffusion layer (N +) 1h is turned on. More current flows through the NPN transistor 3, and the potential of the N-type diffusion layer (N +) 1d decreases. When this current further increases, the PNP transistor 2 is turned on and the current is further increased, so that the potential at the terminal 1q is lowered and the SCR operation state is entered. As a result, the current flowing through the positive ESD flows between the terminal 1q and the terminal 1r under a voltage lower than the trigger voltage, so that the internal circuit is protected.

  Here, for the positive ESD, the drain-source breakdown voltage of the NMOS transistor 5 can be set lower than the junction breakdown voltage of 1 g between the N-type diffusion layer (N +) 1d and the P-type diffusion layer (P-). For example, the trigger voltage can be lowered by the NMOS transistor 5. For example, the gate length of the NMOS transistor 5 is reduced, or the distance between the P-type diffusion layer (P +) 1a constituting the back gate contact and the N-type diffusion layer (N +) 1b constituting the source region is increased. It can be realized by doing.

  When negative polarity ESD is applied to the terminal 1q with reference to the terminal 1r, the voltage due to the negative polarity ESD is N-type diffused through the P-type diffusion layer (P +) 1a and the P-type diffusion layer (P-) 1c. Reach layer (N +) 1d. At this time, the voltage due to the negative polarity ESD is higher of the junction breakdown voltage between the N-type diffusion layer (N +) 1d and the P-type diffusion layer (P−) 1c and the drain-source breakdown voltage of the NMOS transistor 4 (that is, absolute When the breakdown voltage of the smaller value is exceeded, the current due to the negative polarity ESD is changed from the terminal 1r → P type diffusion layer (P +) 1j → P type diffusion layer (P−) 1g → N type diffusion layer (N +) 1d → P. It flows from the type diffusion layer (P−) 1c → P type diffusion layer (P +) 1a or N type diffusion layer (N +) 1b → terminal 7q.

  When this current increases and exceeds the trigger voltage, the NPN transistor 1 composed of the N-type diffusion layer (N +) 1d, the P-type diffusion layer (P−) 1c, and the N-type diffusion layer (N +) 1b operates. Flows more through the NPN transistor 1, and the potential of the terminal 1q rises (decreases in absolute value). When this current further increases, the PNP transistor 2 is also turned on, the parasitic diode 6 is turned on, and the current further increases, so that the potential of the terminal 7q rises (decreases in absolute value) and enters the SCR operation state.

  Here, since the drain-source breakdown voltage of the NMOS transistor 4 can be set so as to define the trigger voltage as described above, the negative ESD is affected by the parasitic diode 6 even when it exists. The trigger voltage can be set to an optimum value without any problem.

  As described above, according to the first embodiment, since the NMOS transistor is provided in parallel to each of the two NPN transistors that act on the positive polarity ESD and the negative polarity ESD, both positive polarity and negative polarity ESD are provided. The trigger voltage for can be arbitrarily optimized.

Embodiment 2. FIG.
FIG. 3 is a cross-sectional structure diagram of a CMOS structure in which a bidirectional lateral SCR which is a bidirectional electrostatic discharge protection element according to Embodiment 2 of the present invention appears. In FIG. 3, the same reference numerals are given to components that are the same as or equivalent to those shown in FIG. 2 (Embodiment 1). Here, the description will focus on the parts related to the second embodiment.

  The bidirectional horizontal SCR according to the second embodiment can be expressed by the equivalent circuit shown in FIG. 1, but the structure in which the PNP transistor 2 appears is different from that in FIG. That is, as shown in FIG. 3, the CMOS structure for causing the bidirectional lateral SCR to appear according to the second embodiment is a structure without the N-type diffusion layer (N−) 1f in the CMOS structure shown in FIG. Yes.

  Therefore, NPN transistors 1 and 3 and NMOS transistors 4 and 5 are formed in the same relationship as in the first embodiment. However, in this second embodiment, PNP transistor 2 is N-type diffusion layer (N +) 1d or The N type diffusion layer (N−) 1e is used as a base electrode, the P type diffusion layer (P−) 1c is used as one emitter electrode, and the P type diffusion layer (P−) 1g is used as the other emitter electrode.

  Also in the configuration shown in FIG. 3, since the same operation as that of the first embodiment is performed on the positive polarity ESD and the negative polarity ESD, the same operation and effect can be obtained.

Embodiment 3 FIG.
FIG. 4 is an equivalent circuit diagram showing a bidirectional lateral SCR which is a bidirectional electrostatic discharge protection element according to Embodiment 3 of the present invention. In the bidirectional lateral SCR according to the third embodiment, the CMOS structure is the same as in FIG. 2, but in FIG. 2, the distance between the P-type diffusion layer (P−) 1g and the P-type diffusion layer (P−) 1c is set. The PNP transistor 2 has a current amplification factor of 1 or less by increasing the impurity concentration of the N-type diffusion layer (N−) 1f, and does not enter the SCR operation. Therefore, in FIG. 4, the PNP transistor 2 shown in FIG. 1 does not appear on the equivalent circuit. In FIG. 4, the terminals 1q and 1r shown in FIG. 1 are terminals 3q and 3r.

  Next, the operation will be described. As described in the first embodiment, the NPN transistor 3 is turned on for the positive polarity ESD, and the NPN transistor 1 is turned on for the negative polarity ESD. Thereafter, since the current amplification factor of the PNP transistor 2 is 1 or less, the SCR operation is not performed, and a current flows through the parasitic diode 6 for the negative polarity ESD. Therefore, the voltage between the terminal 3q and the terminal 3r is higher than the voltage during the SCR operation even when the current increases, but is lower than the trigger voltage.

  As described above, according to the third embodiment, the protection operation against ESD can be performed without any trouble even if the MOS structure reduces the capability of the PNP transistor.

Embodiment 4 FIG.
5 to 7 are diagrams showing the configuration of a bidirectional lateral SCR which is a bidirectional electrostatic discharge protection element according to Embodiment 4 of the present invention. 5 is an equivalent circuit diagram, FIG. 6 is a top layout view of the CMOS structure in which the bidirectional lateral SCR shown in FIG. 5 appears, and FIG. 7 is a cross section of the CMOS structure in which the bidirectional lateral SCR shown in FIG. 5 appears. FIG.

  As shown in FIG. 5, in the fourth embodiment, in the equivalent circuit shown in FIG. 1, the terminals 1q and 1r are terminals 4q and 4r, but the gate electrodes of the NMOS transistors 4 and 5 and the terminals 4q and 4r 4r is not directly connected, but has a configuration in which resistance elements 6 and 7 are interposed. This is realized by adding a structure as shown in FIGS. 6 and 7 to the upper surface side of the CMOS structure shown in FIG.

  6 and 7, conductive wirings 5m and 5p constituting the gate electrode are wired on the element isolation insulating film 1y via the insulating film 5aa to form a resistor (resistive elements 6 and 7), which is electrically conductive. The conductive wires 5z are connected to the conductive wires constituting the terminals 4q and 4p.

  Next, the operation will be described. When the gate electrodes of the NMOS transistors 4 and 5 that determine the trigger voltage are connected to the terminals 4q and 4r through the resistance elements 6 and 7, when a positive or negative ESD is applied, the corresponding gate electrode has a resistance. A pulse voltage determined by a time constant between the elements 6 and 7 and the parasitic capacitance element (capacitance element between the drain and source of the NMOS transistors 4 and 5) is applied. As a result, the gate potential rises, and the corresponding ones of the NMOS transistors 4 and 5 are turned on.

  That is, according to the fourth embodiment, the trigger voltage can be set to a more optimal value by connecting the gate electrodes of the NMOS transistors 4 and 5 to the terminals 4q and 4r via the resistance elements 6 and 7, respectively. it can.

Embodiment 5. FIG.
FIG. 8 is a cross-sectional structure diagram of a CMOS structure in which a bidirectional lateral SCR which is a bidirectional electrostatic discharge protection element according to Embodiment 5 of the present invention appears. In FIG. 8, components that are the same as or equivalent to the components shown in FIG. 2 (Embodiment 1) are given the same reference numerals. Here, the description will be focused on the portion related to the fifth embodiment.

  As shown in FIG. 8, in the bidirectional electrostatic discharge protection element (bidirectional lateral SCR) according to the fifth embodiment, in the configuration shown in FIG. 2 (first embodiment), P as an element isolation layer is formed. Instead of the type diffusion layer (P +) 1v and the element isolation insulating film 1y formed thereon, a trench isolation insulating film 2a is provided.

According to this configuration, since the element isolation by the PN junction is changed to the element isolation by the oxide film (SiO ₂ ), the isolation width can be made smaller than that of the first embodiment, and the entire element structure can be reduced.

Embodiment 6 FIG.
FIG. 9 is a cross-sectional view of a CMOS structure in which a bidirectional lateral SCR that is a bidirectional electrostatic discharge protection element according to Embodiment 6 of the present invention appears. In FIG. 9, the same reference numerals are given to the same or equivalent components as those shown in FIG. 2 (Embodiment 1). Here, the description will be focused on the portion related to the sixth embodiment.

  As shown in FIG. 9, in the bidirectional electrostatic discharge protection element (bidirectional lateral SCR) according to the sixth embodiment, in the configuration shown in FIG. 2 (first embodiment), an N type diffusion layer (N +) Instead of 1w, an SOI insulating film 2b is provided.

  According to this configuration, since the PN junction between the P-type substrate (P−) 1x and the N-type diffusion layer (N +) 1w in the configuration shown in FIG. 2 is eliminated, negative ESD is applied to the terminal 1q. Sometimes, the diode forward characteristic from the N-type diffusion layer (N−) 1e to the N-type diffusion layer (N +) 1w to the P-type substrate (P−) 1x is lost, and the influence on the peripheral elements from the substrate may be eliminated. In addition, the separation width from the peripheral elements can be reduced.

  Further, since there is no diode element composed of the P-type substrate (P−) 1x and the N-type diffusion layer (N +) 1w, when negative ESD is applied to the terminal 1q, the P-type diffusion layer (P−) 1g In the PNP transistor composed of the N-type diffusion layer (N−) 1f and the P-type diffusion layer (P−) 1c, the base current is not injected from the P-type substrate (P−) 1x. As a transistor, the transistor can operate reliably, and the negative ESD tolerance can be increased.

Embodiment 7 FIG.
FIG. 10 is a cross-sectional structure diagram of a CMOS structure in which a bidirectional lateral SCR which is a bidirectional electrostatic discharge protection element according to Embodiment 7 of the present invention appears. In FIG. 10, the same reference numerals are given to the same or equivalent components as those shown in FIG. 2 (Embodiment 1). Here, the description will be focused on the portion related to the seventh embodiment.

  As shown in FIG. 10, in the bidirectional electrostatic discharge protection element (bidirectional lateral SCR) according to the seventh embodiment, in the configuration shown in FIG. 2 (first embodiment), P as an element isolation layer is formed. Instead of the type diffusion layer (P +) 1v and the element isolation insulating film 1y formed thereon, the trench isolation insulating film 2a shown in FIG. 8 (Embodiment 5) is provided, and the N type diffusion layer ( In place of (N +) 1w, an SOI insulating film 2b shown in FIG. 9 (Embodiment 6) is provided.

  According to this configuration, since a so-called box-type isolation structure that simultaneously realizes isolation from peripheral elements and isolation from the substrate is achieved, the isolation width between elements can be minimized, and negative ESD tolerance can be simultaneously reduced. Can be increased.

  In the fifth to seventh embodiments, the application example to the first embodiment has been described. Needless to say, the present invention can be similarly applied to the second to fourth embodiments.

  As described above, the bidirectional lateral SCR, which is a bidirectional electrostatic discharge protection element according to the present invention, is useful for optimizing both the positive and negative trigger voltages, and particularly has a small element structure. It is suitable for increasing the resistance to ESD and ESD.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an equivalent circuit diagram showing a bidirectional lateral SCR that is a bidirectional electrostatic discharge protection element according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional structure diagram of a CMOS structure in which the bidirectional lateral SCR shown in FIG. 1 appears. It is sectional drawing of the CMOS structure which makes the bidirectional | two-way horizontal SCR which is a bidirectional | two-way type electrostatic discharge protection element by Embodiment 2 of this invention appear. It is an equivalent circuit diagram which shows the bidirectional | two-way horizontal SCR which is a bidirectional | two-way type electrostatic discharge protection element by Embodiment 3 of this invention. It is an equivalent circuit diagram which shows the bidirectional | two-way horizontal SCR which is a bidirectional | two-way type electrostatic discharge protection element by Embodiment 4 of this invention. FIG. 6 is a top layout view of a CMOS structure in which the bidirectional lateral SCR shown in FIG. 5 appears. FIG. 6 is a cross-sectional structure diagram of a CMOS structure in which the bidirectional lateral SCR shown in FIG. 5 appears. It is sectional drawing of the CMOS structure which makes the bidirectional | two-way lateral SCR which is a bidirectional | two-way type electrostatic discharge protection element by Embodiment 5 of this invention appear. It is sectional drawing of the CMOS structure which makes the bidirectional | two-way horizontal SCR which is a bidirectional | two-way type electrostatic discharge protection element by Embodiment 6 of this invention appear. It is sectional drawing of the CMOS structure which makes the bidirectional | two-way horizontal SCR which is a bidirectional | two-way type electrostatic discharge protection element by Embodiment 7 of this invention appear. It is an equivalent circuit diagram of the horizontal SCR used for positive polarity ESD (conventional example 1). FIG. 12 is a cross-sectional structure diagram of a CMOS structure in which the horizontal SCR shown in FIG. 11 appears. It is an equivalent circuit diagram of bidirectional SCR which can respond to both positive polarity ESD and negative polarity ESD (conventional example 2). FIG. 14 is a cross-sectional structure diagram of a CMOS structure in which the bidirectional lateral SCR shown in FIG. 13 appears.

Explanation of symbols

1q, 1r, 3q, 3r, 4q, 4r Terminals 1, 3 NPN transistor 2 PNP transistor 4, 5 NMOS transistor 7, 8 Resistance element 1a P-type diffusion layer (P +: back gate contact)
1b N-type diffusion layer (N +: source)
1c P-type diffusion layer (P-: P well)
1d N-type diffusion layer (N +: drain)
1e N-type diffusion layer (N-: epitaxial growth film)
1f N type diffusion layer (N-: N well)
1g P-type diffusion layer (P-: P well)
1h N-type diffusion layer (N +: source)
1j P-type diffusion layer (P +: back gate contact)
1k Insulating film 1m Gate electrode (conductive wiring)
1n Insulating film 1p Gate electrode (conductive wiring)
1w N-type diffusion layer (N +)
1x P-type substrate (P-)
1y Element isolation insulating film 1v P-type diffusion layer (P +: element isolation layer)
2a Trench isolation insulating film 2b SOI insulating film

Claims (6)

First and second bipolar transistors whose collector electrodes are connected in common and whose emitter electrodes are connected to the first and second terminals of the semiconductor integrated circuit, and whose base electrode is the collector of the first and second bipolar transistors A bidirectional emitter electrode is connected to an electrode connection end, and is connected to a corresponding base electrode of each of the first and second bipolar transistors, and corresponding to each of the first and second bipolar transistors via a resistance element. A bidirectional electrostatic discharge protection element using a bidirectional lateral SCR that appears in a manufacturing process of a semiconductor integrated circuit with a third bipolar transistor connected to an emitter electrode,
In the first and second bipolar transistors, first and second NMOS transistors are integrally formed in parallel, respectively, and the gate electrodes of the first and second NMOS transistors are the first and second NMOS transistors, respectively. Connected to the corresponding emitter electrode of the bipolar transistor of
A bidirectional electrostatic discharge protection element characterized by the above.   The bidirectional electrostatic discharge protection element according to claim 1, wherein the third bipolar transistor has a current amplification factor of 1 or less.   The gate electrodes of the first and second NMOS transistors are connected to the corresponding emitter electrodes of the first and second bipolar transistors via a resistor composed of a gate wiring wired on the element isolation insulating film. The bidirectional electrostatic discharge protection element according to claim 1 or 2, characterized in that:   3. The bidirectional electrostatic discharge protection element according to claim 1, wherein a trench isolation insulating film is formed on an outer periphery of a formation region of each of the first and second NMOS transistors.   3. The bidirectional electrostatic discharge protection element according to claim 1, wherein an SOI insulating film is formed between the formation region of the first and second NMOS transistors and the semiconductor substrate. 4. .   A trench isolation insulating film is formed around the formation region of the first and second NMOS transistors, and an SOI is formed between the formation region and the semiconductor substrate of the first and second NMOS transistors. The bidirectional electrostatic discharge protection element according to claim 1, wherein an insulating film is formed.

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