[go: up one dir, main page]

JP2009099655A - Lead-free soldering method for wide gap semiconductor chips - Google Patents

Lead-free soldering method for wide gap semiconductor chips Download PDF

Info

Publication number
JP2009099655A
JP2009099655A JP2007267697A JP2007267697A JP2009099655A JP 2009099655 A JP2009099655 A JP 2009099655A JP 2007267697 A JP2007267697 A JP 2007267697A JP 2007267697 A JP2007267697 A JP 2007267697A JP 2009099655 A JP2009099655 A JP 2009099655A
Authority
JP
Japan
Prior art keywords
lead
gap semiconductor
free
soldering
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007267697A
Other languages
Japanese (ja)
Inventor
Hiroshi Nakagawa
博 仲川
Yasunori Tanaka
保宣 田中
Kenji Fukuda
憲司 福田
Masahiro Aoyagi
昌広 青柳
Hiromichi Ohashi
弘通 大橋
Hitomoto Tokuda
人基 徳田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Sumitomo Electric Industries Ltd
Original Assignee
National Institute of Advanced Industrial Science and Technology AIST
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute of Advanced Industrial Science and Technology AIST, Sumitomo Electric Industries Ltd filed Critical National Institute of Advanced Industrial Science and Technology AIST
Priority to JP2007267697A priority Critical patent/JP2009099655A/en
Publication of JP2009099655A publication Critical patent/JP2009099655A/en
Pending legal-status Critical Current

Links

Landscapes

  • Die Bonding (AREA)

Abstract

【課題】ワイドギャップ半導体チップの電極構造において鉛フリー半田を用いた半田付けを行った場合の接合状態を良好なものとできる、ワイドギャップ半導体チップの鉛フリー半田付け方法、および鉛フリー半田付けによるワイドギャップ半導体チップを提供する。
【解決手段】ワイドギャップ半導体チップの電極上に、鉛フリー半田付け時の電極最表面の酸化を防ぐ保護層を形成し、該保護層上に鉛フリー半田で半田付けを行う、ことを特徴とするワイドギャップ半導体チップの鉛フリー半田付け方法。
【選択図】図1
A lead-free soldering method for a wide-gap semiconductor chip, and a lead-free soldering method capable of improving the bonding state when soldering using lead-free solder is performed in an electrode structure of a wide-gap semiconductor chip A wide gap semiconductor chip is provided.
A protective layer for preventing oxidation of the outermost electrode surface during lead-free soldering is formed on an electrode of a wide gap semiconductor chip, and soldering is performed on the protective layer with lead-free solder. Lead-free soldering method for wide gap semiconductor chips.
[Selection] Figure 1

Description

本発明は、SiC等のワイドギャップ半導体チップの電極を鉛フリー半田で半田付けする方法に関するものである。   The present invention relates to a method of soldering electrodes of a wide gap semiconductor chip such as SiC with lead-free solder.

従来、たとえば図1(a)および図2(a)に例示したように、ワイドギャップ半導体チップにおいて、Agの酸化膜(図中「Ag層」)がチップ電極最表面に形成されていても、鉛系の半田を使用した場合では、その濡れ性が鉛フリー半田よりも良いため、電極間の接合状態に大きな問題は生じていなかった。
しかし、錫−銀−銅(Sn-Ag-Cu)や金−錫(Au-Sn)などの鉛フリー半田は、鉛系半田に比べ濡れ性が悪いため、電極表面の状態による影響が大きい。このため、鉛系半田と同様な条件で半田付けを行ったとしても、図2(b)に例示したような未接合部が生じてしましい、鉛系半田と同等の接合状態を作り出すことは、極めて困難である。
この鉛フリー半田を使用した場合の問題点を克服する手法としては、たとえば以下のものが考えられる。
1.電極最表面の酸化物層を化学薬品により除去する(いわゆるウェットエッチング)。
2.ドライエッチングなど物理的な手法で除去する。
Conventionally, for example, as illustrated in FIG. 1A and FIG. 2A, in a wide gap semiconductor chip, an Ag oxide film (“Ag layer” in the figure) is formed on the outermost surface of the chip electrode. When lead-based solder is used, the wettability thereof is better than that of lead-free solder, so that no major problem has occurred in the bonding state between the electrodes.
However, lead-free solders such as tin-silver-copper (Sn-Ag-Cu) and gold-tin (Au-Sn) have poor wettability compared to lead-based solder, and are therefore greatly affected by the state of the electrode surface. For this reason, even if soldering is performed under the same conditions as lead-based solder, an unjoined portion as illustrated in FIG. 2B may be produced, and a joint state equivalent to lead-based solder is created. It is extremely difficult.
As a technique for overcoming the problems in the case of using this lead-free solder, for example, the following can be considered.
1. The oxide layer on the outermost surface of the electrode is removed with chemicals (so-called wet etching).
2. It is removed by a physical method such as dry etching.

しかしながら、1の手法では、例えば、亜鉛と塩酸の溶液を使用することで除去することは可能であるものの、これはチップの表面電極を犯してしまうという問題あり、また亜鉛が残留すると更に半田濡れ性が低下する。
2の手法としては、例えば、プラズマエッチング方法などがあるが、チップ自体の温度が上昇してしまうため、電極に使用している金属へのダメージが懸念される。
また、1,2ともに、除去後即時に半田付けしなければ、最表面に酸化物層が再び構成されてしまい、半田付けとのタイミング設定に難がある。
However, in one method, for example, it can be removed by using a solution of zinc and hydrochloric acid. However, this has a problem that the surface electrode of the chip is violated. Sex is reduced.
As the second method, for example, there is a plasma etching method or the like. However, since the temperature of the chip itself increases, there is a concern about damage to the metal used for the electrode.
If both 1 and 2 are not soldered immediately after removal, an oxide layer is formed again on the outermost surface, which makes it difficult to set the timing for soldering.

本発明は、以上の事情に鑑みてなされたものであり、ワイドギャップ半導体チップの電極構造において、鉛フリー半田を用いた半田付けを行った場合の接合状態を良好なものとし、上記各種手法と同様な問題点も生じることのない、ワイドギャップ半導体チップの鉛フリー半田付け方法、および鉛フリー半田付けによるワイドギャップ半導体チップを提供することを課題としている。   The present invention has been made in view of the above circumstances, and in the electrode structure of a wide gap semiconductor chip, the bonding state when soldering using lead-free solder is made favorable, It is an object of the present invention to provide a lead-free soldering method for a wide gap semiconductor chip and a wide gap semiconductor chip by lead-free soldering without causing the same problems.

本発明は、上記の課題を解決するものとして、ワイドギャップ半導体チップの電極上に、鉛フリー半田付け時の電極最表面の酸化を防ぐ保護層を形成し、該保護層上に鉛フリー半田で半田付けを行う、ことを特徴とするワイドギャップ半導体チップの鉛フリー半田付け方法を提供する。
また、本発明は、上記の課題を解決するものとして、ワイドギャップ半導体チップの電極上に、鉛フリー半田付け時の電極最表面の酸化を防ぐ保護層が設けられ、該保護層上に鉛フリー半田で半田付けが行われている、ことを特徴とする鉛フリー半田付けによるワイドギャップ半導体チップを提供する。
上記のとおりの特徴を有する本発明によれば、ワイドギャップ半導体チップの電極構造において、上記保護層を1層以上設けることにより、鉛フリー半田付け時に酸化物層自体が電極最表面に構成されず、よって、図2(b)に例示したような電極最表面と鉛フリー半田との間の未接合部が生じない、良好な接合状態を持つ鉛フリー半田付けを実現することができる。
保護層としては、半田付け前に除去する必要のない材料であって、なおかつ鉛フリー半田となじみが良い、もしくは半田付けの際に鉛フリー半田に吸収される材質のものを選択する。候補として考えられる材料は、例えば、金、プリフラックスなどが挙げられる。金の製膜は真空蒸着もしくはめっきで行うことができる。
In order to solve the above problems, the present invention forms a protective layer on the electrode of a wide gap semiconductor chip to prevent oxidation of the outermost surface of the electrode during lead-free soldering, and the lead-free solder is formed on the protective layer. Provided is a lead-free soldering method for a wide gap semiconductor chip, characterized by performing soldering.
In order to solve the above problems, the present invention provides a protective layer for preventing oxidation of the outermost surface of the electrode during lead-free soldering on the electrode of the wide gap semiconductor chip, and the lead-free coating is provided on the protective layer. Provided is a wide gap semiconductor chip by lead-free soldering, which is characterized by being soldered with solder.
According to the present invention having the features as described above, in the electrode structure of the wide gap semiconductor chip, by providing one or more protective layers, the oxide layer itself is not formed on the outermost electrode surface during lead-free soldering. Therefore, it is possible to realize lead-free soldering having a good joined state in which an unjoined portion between the electrode outermost surface and lead-free solder as illustrated in FIG. 2B does not occur.
As the protective layer, a material that does not need to be removed before soldering and that is compatible with lead-free solder or that is absorbed by lead-free solder during soldering is selected. Examples of materials considered as candidates include gold and preflux. Gold film formation can be performed by vacuum evaporation or plating.

[第一実施形態]
図2(b)は、本発明の一実施形態であり、上記のとおりの保護層として1層の金層が電極最表面をカバーして設けられている。
ここで、図2(a)の金薄膜層(厚さ100nm以上)で電極最表面をカバーしていないワイドギャップ半導体チップと図2(b)の金薄膜層でカバーしたものそれぞれに対してSn-Ag-Cuの鉛フリー半田を用いた半田付け付けを行ったところ、図3(a)(b)に示すようなX線透視装置による画像が得られた。この画像データから算出した結果、同じ鉛フリー半田を使用して同じ条件で半田付けした場合、未接合部分であるいわゆるボイドが35%から15%に減少していることが分かった。
ボイドが多いとShear強度が低くなる、熱伝導が悪くなるといった、特にパワーデバイスでは致命的な問題が生じるが、本発明によれば、極めて良好な接合状態が得られ、Shear強度ならびに熱伝導の向上を図ることができる。
なお、半田付けの条件としては、窒素などの不活性ガス中での加熱、真空中での加熱など極力酸素を排した環境での半田付けが望ましい。
[First embodiment]
FIG. 2B shows an embodiment of the present invention, and a single gold layer is provided to cover the outermost surface of the electrode as the protective layer as described above.
Here, Sn is applied to each of the wide gap semiconductor chip that does not cover the outermost surface of the electrode with the gold thin film layer (thickness of 100 nm or more) in FIG. 2A and the gold thin film layer that is covered with the gold thin film layer in FIG. When soldering using a lead-free solder of -Ag-Cu was performed, an image obtained by an X-ray fluoroscopic apparatus as shown in FIGS. 3A and 3B was obtained. As a result of calculation from this image data, it was found that when the same lead-free solder was used and soldered under the same conditions, so-called voids, which are unjoined portions, decreased from 35% to 15%.
When there are many voids, the shear strength becomes low and the heat conduction becomes bad, especially in power devices, but a fatal problem arises.However, according to the present invention, a very good bonding state can be obtained, and the shear strength and heat conduction are reduced. Improvements can be made.
The soldering conditions are preferably soldering in an environment where oxygen is eliminated as much as possible, such as heating in an inert gas such as nitrogen or heating in a vacuum.

(a)(b)は各々、従来例および本発明の一実施形態の概略図。(A) and (b) are schematic diagrams of a conventional example and an embodiment of the present invention, respectively. (a)(b)は各々、従来例および本発明の一実施例の電子顕微鏡写真図。(A) and (b) are electron micrographs of a conventional example and an embodiment of the present invention, respectively. (a)(b)は各々、従来例および本発明の一実施例のX線透視画像図。(A) and (b) are the X-ray fluoroscopic image figure of a prior art example and one Example of this invention, respectively.

Claims (8)

ワイドギャップ半導体チップの電極上に、鉛フリー半田付け時の電極最表面の酸化を防ぐ保護層を形成し、該保護層上に鉛フリー半田で半田付けを行う、ことを特徴とするワイドギャップ半導体チップの鉛フリー半田付け方法。   A wide-gap semiconductor, characterized in that a protective layer that prevents oxidation of the outermost electrode surface during lead-free soldering is formed on the electrode of the wide-gap semiconductor chip, and soldering is performed on the protective layer with lead-free solder Chip lead-free soldering method. 前記保護層は、半田付け前に除去する必要がなく、且つ鉛フリー半田となじみが良いもしくは鉛フリー半田に吸収される材料からなる、請求項1記載のワイドギャップ半導体チップの鉛フリー半田付け方法。   2. The lead-free soldering method for a wide gap semiconductor chip according to claim 1, wherein the protective layer does not need to be removed before soldering and is made of a material that is compatible with lead-free solder or is absorbed by lead-free solder. . 前記保護層は金からなる、請求項1または2記載のワイドギャップ半導体チップの鉛フリー半田付け方法。   3. The lead-free soldering method for a wide gap semiconductor chip according to claim 1, wherein the protective layer is made of gold. 前記保護層を1層以上形成する、請求項1ないし3のいずれかに記載のワイドギャップ半導体チップの鉛フリー半田付け方法。   4. The lead-free soldering method for a wide gap semiconductor chip according to claim 1, wherein one or more protective layers are formed. ワイドギャップ半導体チップの電極上に、鉛フリー半田付け時の電極最表面の酸化を防ぐ保護層が設けられ、該保護層上に鉛フリー半田で半田付けが行われている、ことを特徴とする鉛フリー半田付けによるワイドギャップ半導体チップ。   A protective layer for preventing oxidation of the outermost electrode surface during lead-free soldering is provided on the electrode of the wide gap semiconductor chip, and soldering is performed on the protective layer with lead-free solder. Wide gap semiconductor chip by lead-free soldering. 前記保護層は、半田付け前に除去する必要がなく、且つ鉛フリー半田となじみが良いもしくは鉛フリー半田に吸収される材料からなる、請求項6記載の鉛フリー半田付けによるワイドギャップ半導体チップ。   7. The wide gap semiconductor chip by lead-free soldering according to claim 6, wherein the protective layer does not need to be removed before soldering and is made of a material that is compatible with lead-free solder or is absorbed by lead-free solder. 前記保護層は金からなる、請求項5または6記載のワイドギャップ半導体チップの鉛フリー半田付け方法。   7. The lead-free soldering method for a wide gap semiconductor chip according to claim 5, wherein the protective layer is made of gold. 前記保護層は1層以上設けられている、請求項5ないし7のいずれかに記載の鉛フリー半田付けによるワイドギャップ半導体チップ。   The wide gap semiconductor chip by lead-free soldering according to any one of claims 5 to 7, wherein at least one protective layer is provided.
JP2007267697A 2007-10-15 2007-10-15 Lead-free soldering method for wide gap semiconductor chips Pending JP2009099655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007267697A JP2009099655A (en) 2007-10-15 2007-10-15 Lead-free soldering method for wide gap semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007267697A JP2009099655A (en) 2007-10-15 2007-10-15 Lead-free soldering method for wide gap semiconductor chips

Publications (1)

Publication Number Publication Date
JP2009099655A true JP2009099655A (en) 2009-05-07

Family

ID=40702406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007267697A Pending JP2009099655A (en) 2007-10-15 2007-10-15 Lead-free soldering method for wide gap semiconductor chips

Country Status (1)

Country Link
JP (1) JP2009099655A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2460168C2 (en) * 2009-12-31 2012-08-27 Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" Method of soldering silicon carbide-based chips
RU2753171C1 (en) * 2020-11-25 2021-08-12 федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский политехнический университет Петра Великого" (ФГАОУ ВО "СПбПУ") Method for non-damaging surface mounting of silicon crystals and a3b5 type crystals by using shs foil deposited in form of metallizing multilayer nanostructured coating on surface of these crystals

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000353709A (en) * 1999-06-14 2000-12-19 Hitachi Ltd Semiconductor device and electronic device using the same
JP2002158393A (en) * 2000-09-11 2002-05-31 Fuji Photo Film Co Ltd Semiconductor laser element and semiconductor laser device
JP2003059860A (en) * 2001-08-13 2003-02-28 Mitsubishi Electric Corp Semiconductor device
JP2003060276A (en) * 2001-08-09 2003-02-28 Sharp Corp Semiconductor light emitting device and method of manufacturing the same
JP2004304111A (en) * 2003-04-01 2004-10-28 Sharp Corp Multi-wavelength laser device
JP2005109484A (en) * 2003-10-01 2005-04-21 Samsung Electronics Co Ltd SnAgAu solder bump, manufacturing method thereof, and bonding method of light emitting device using the method
JP2005229021A (en) * 2004-02-16 2005-08-25 Sharp Corp Semiconductor light emitting device and manufacturing method thereof
JP2007013002A (en) * 2005-07-01 2007-01-18 Fujifilm Holdings Corp Semiconductor laser equipment
JP2007281412A (en) * 2006-03-17 2007-10-25 Toyota Central Res & Dev Lab Inc Power semiconductor module

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000353709A (en) * 1999-06-14 2000-12-19 Hitachi Ltd Semiconductor device and electronic device using the same
JP2002158393A (en) * 2000-09-11 2002-05-31 Fuji Photo Film Co Ltd Semiconductor laser element and semiconductor laser device
JP2003060276A (en) * 2001-08-09 2003-02-28 Sharp Corp Semiconductor light emitting device and method of manufacturing the same
JP2003059860A (en) * 2001-08-13 2003-02-28 Mitsubishi Electric Corp Semiconductor device
JP2004304111A (en) * 2003-04-01 2004-10-28 Sharp Corp Multi-wavelength laser device
JP2005109484A (en) * 2003-10-01 2005-04-21 Samsung Electronics Co Ltd SnAgAu solder bump, manufacturing method thereof, and bonding method of light emitting device using the method
JP2005229021A (en) * 2004-02-16 2005-08-25 Sharp Corp Semiconductor light emitting device and manufacturing method thereof
JP2007013002A (en) * 2005-07-01 2007-01-18 Fujifilm Holdings Corp Semiconductor laser equipment
JP2007281412A (en) * 2006-03-17 2007-10-25 Toyota Central Res & Dev Lab Inc Power semiconductor module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2460168C2 (en) * 2009-12-31 2012-08-27 Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" Method of soldering silicon carbide-based chips
RU2753171C1 (en) * 2020-11-25 2021-08-12 федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский политехнический университет Петра Великого" (ФГАОУ ВО "СПбПУ") Method for non-damaging surface mounting of silicon crystals and a3b5 type crystals by using shs foil deposited in form of metallizing multilayer nanostructured coating on surface of these crystals

Similar Documents

Publication Publication Date Title
JP5725060B2 (en) Bonded body, power module substrate, and power module substrate with heat sink
KR102272865B1 (en) Joined body, substrate for power module provided with heat sink, heat sink, method for manufacturing joined body, method for manufacturing substrate for power module provided with heat sink, and method for manufacturing heat sink
JP6369085B2 (en) Power module
KR102336484B1 (en) Assembly, power-module substrate provided with heat sink, heat sink, method for manufacturing assembly, method for manufacturing power-module substrate provided with heat sink, and method for manufacturing heat sink
JP2003007764A (en) Semiconductor device and method of manufacturing the same
JP4904767B2 (en) Semiconductor device
JP6443568B2 (en) Bonding material, bonding method and bonding structure using the same
WO2014103955A1 (en) Power module
JP5725061B2 (en) Power module substrate and power module substrate with heat sink
JP4208863B2 (en) Semiconductor device and manufacturing method thereof
JP6432208B2 (en) Method for manufacturing power module substrate, and method for manufacturing power module substrate with heat sink
JP6528559B2 (en) Method of manufacturing ceramic / aluminum bonded body, method of manufacturing power module substrate, ceramic / aluminum bonded body, power module substrate
JP2009099655A (en) Lead-free soldering method for wide gap semiconductor chips
JP2001060760A (en) Circuit electrode and method for forming the same
JP6327058B2 (en) Power module substrate with heat sink, method of manufacturing joined body, method of manufacturing power module substrate, and method of manufacturing power module substrate with heat sink
JP6566634B2 (en) Junction structure and manufacturing method of junction structure
JP6958156B2 (en) Manufacturing method of semiconductor devices
JP4910789B2 (en) Power element mounting substrate, power element mounting substrate manufacturing method, and power module
JP6287681B2 (en) Manufacturing method of joined body, manufacturing method of power module substrate, and manufacturing method of power module substrate with heat sink
JP6299442B2 (en) Power module
JP4434106B2 (en) Manufacturing method of semiconductor device
JP2007123577A (en) Semiconductor device
JP4745878B2 (en) Solder film and soldering method using the same
JP5055625B2 (en) Lead-free vacuum soldering method for wide gap semiconductor chips
JP2004174594A (en) Component joining method and joining structure

Legal Events

Date Code Title Description
A621 Written request for application examination

Effective date: 20091005

Free format text: JAPANESE INTERMEDIATE CODE: A621

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091009

A521 Written amendment

Effective date: 20091106

Free format text: JAPANESE INTERMEDIATE CODE: A523

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110915

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110920

A02 Decision of refusal

Effective date: 20120130

Free format text: JAPANESE INTERMEDIATE CODE: A02