JP2009098171A - Image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image forming apparatus having a motor driver circuit which is simply design-changeable and is high in versatility. <P>SOLUTION: An operation amplifier AMP forms a buffer circuit by being externally connected to a resistance element. One input node (minus side) of the operation amplifier AMP and the output node thereof are connected to the resister element R1 via an external pin EP. The other input node (plus side) of the operation amplifier AMP is connected to a reference voltage Vref. The one input node (minus side) of the operation amplifier AMP is connected to the output node of a signal output section 220 (not shown in figure) of a CPU 200 via the resistance element R2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus in which a DC brushless motor is used as a drive mechanism.

  In image forming apparatuses such as copiers, printers, and MFPs (Multi Function Peripheral) that are multifunctional printers, DC brushless motors, AC motors, or stepping motors are selected for use according to the purpose. There is.

  When a DC brushless motor is used for the drive configuration, a feedback gain, a phase compensation constant, and the like may be set in hardware in the motor control board of the DC brushless motor.

FIG. 8 is a diagram illustrating the configuration of a conventional DC brushless motor.
Referring to FIG. 8, control circuit 1005 in control board 1000 outputs a control signal (clock signal) that is a command signal in order to set the target speed (rotation speed). A motor driver circuit 1020 in the motor control board 1010 receives a control signal (clock signal) and controls a current supplied to the DC brushless (DCBL) motor unit 1015 so as to reach a target speed. In the motor control board 1010, feedback control is executed so that the DC brushless motor rotates at a constant rate.

FIG. 9 is a diagram illustrating the configuration inside the motor control board.
Referring to FIG. 9, a DC brushless motor unit 1015 and a motor driver circuit 1020 are provided in the motor control board, and the resistor element and the capacitor element are designed to be externally connected to the motor driver circuit 1020. ing.

  The DC brushless motor unit 1015 includes a motor 1016 and an FG sensor 1017 for detecting the rotation speed (number of rotations) of the motor 1016. The FG sensor 1017 generates an FG signal (FG pulse) that is a rotation signal based on a change in magnetic flux according to the rotation speed (rotation speed) of the rotor of the motor 1016.

FG pulse frequency = motor rotation speed (rpm) ÷ 60 × FG pulse number Here, the FG pulse number is the number of pulses output from a so-called FG pattern per one motor rotation.

  The motor driver circuit 1020 includes a speed detection unit 1025 that detects an FG pulse from the FG sensor 1017 that is a rotation signal of the motor 1016, and a control corresponding to the frequency of the FG pulse and the target speed in response to the detection result of the speed detection unit 1025. A speed deviation signal generation unit 1022 that generates a frequency deviation signal with a control signal (clock signal) input from the circuit, a phase of the FG pulse in response to a detection result of the speed detection unit 1025, and a control signal input from the control circuit A phase deviation signal generation unit 1024 that generates a phase deviation signal with respect to the phase of the (clock signal), an operational amplifier AMP, and a PWM (for setting an amount of current supplied to the current supply unit 1028 in response to an output signal of the operational amplifier AMP. PWM chopper unit 1026 for generating a signal (Pules Width Modulation) A current supply unit 1028 for adjusting a current supplied to the motor 1016 in accordance with the PWM signal of the PWM chopper unit 1026.

  The operational amplifier AMP forms a proportional integration circuit by connecting a resistance element and a capacitance element externally. Specifically, resistance elements R1 and R2 are provided in parallel between the speed deviation signal generation unit 1022 and the phase deviation signal generation unit 1024 and the input node of the operational amplifier. Further, the resistor element R3 and the capacitor element C1 are connected in series, and are connected between the input node and the output node of the operational amplifier. In parallel, the capacitive element C2 is connected between the input node and the output node. The other input node of the operational amplifier is supplied with the reference voltage Vref.

  With this configuration, a proportional integration circuit 1030 is formed, and PI (propotional and integral) control, which is one of so-called feedback control methods, is executed.

  Specifically, the speed deviation signal and the phase deviation signal are added to amplify the deviation, and the DUTY ratio of the PWM signal of the PWM chopper unit 1020 is adjusted to control the amount of current supplied to the motor 1016.

  However, when forming a proportional integration circuit using such hardware, in conventional DC brushless motors, for example, the load fluctuations in each model and each application are different. The gain tuning of the proportional integration circuit was executed.

  Therefore, for example, a complicated operation is required to perform gain tuning by adjusting the resistance values of the external resistor element and the capacitor element forming the proportional integration circuit 1030.

  As a related prior document, Japanese Patent Laid-Open No. 9-76563 discloses a method of generating an acceleration instruction signal and a deceleration instruction signal based on an FG pulse to control a motor.

In Japanese Patent Laid-Open No. 10-66374, PID (propotional integral and differential) control, which is feedback control using a CPU, is executed during acceleration and deceleration, and control is performed by switching to a hard logic circuit at a constant speed. Thus, a method for reducing the load on the CPU is disclosed.
JP-A-9-76563 Japanese Patent Laid-Open No. 10-66374

  However, since the method described in Japanese Patent Laid-Open No. 9-76563 needs to design a motor driver circuit for driving a motor in response to an acceleration instruction signal and a deceleration instruction signal, it is specific to the motor control in response to each signal. It is necessary to provide an interface.

  In Japanese Patent Laid-Open No. 10-66374, since the control is performed by switching to a hard logic circuit at a constant speed, it is necessary to provide a motor control mechanism on the hard logic circuit side separately from the CPU. There is a possibility that the layout area increases and the control becomes complicated.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an image forming apparatus having a highly versatile motor driver circuit capable of simple design change from a conventional circuit. And

  An image forming apparatus according to a claim of the present invention includes a direct current brushless motor, a motor driver circuit that supplies a current corresponding to a command signal according to a target speed to the direct current brushless motor, and a motor driver circuit. And a control circuit that adjusts a command signal output by the PID calculation control process so that the motor driver circuit follows the target speed. The motor driver circuit includes an operational amplifier capable of connecting a circuit element provided outside the motor driver circuit between one of the two input nodes and the output node to execute a predetermined function, and a direct current based on the output of the operational amplifier. And a current control unit for controlling the amount of current supplied to the brushless motor. It further includes a first external resistor provided between one input node and the output node of the operational amplifier, and a second external resistor provided between the control circuit and one input node of the operational amplifier. A reference voltage is supplied to the other input node of the operational amplifier, and the operational amplifier forms a buffer circuit having a change rate based on the resistance values of the first and second external resistors.

  Preferably, the motor driver circuit is formed on a semiconductor chip provided with a plurality of packaged input or output pins, and the first external resistor is one input of an operational amplifier among the plurality of input or output pins. Connection is made using pins corresponding to the node and the output node.

Preferably, the command signal is an analog signal.
Preferably, the command signal is output as a PWM signal, and further includes a smoothing circuit that smoothes the PWM signal between the control circuit and one input node of the operational amplifier.

  Preferably, the control circuit detects a deviation from the number of pulses of the rotation signal as the PID calculation control process, executes a first PID calculation control process for adjusting a frequency error, and detects a phase error of the pulse of the rotation signal. Then, the second PID calculation control process for adjusting the phase error is executed in parallel, and the command signal is adjusted based on the calculation results of the first and second PID calculation control processes.

  The image forming apparatus according to the claims of the present invention has a configuration including a motor driver circuit that can easily change the design of an operational amplifier, which has been conventionally used as a proportional integration circuit, as a buffer circuit. Gain tuning, which has been performed by adjusting the resistance value of the element, is executed on the CPU side, and a motor driver circuit with high versatility can be realized by sharing the motor driver circuit.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same parts and components are denoted by the same reference numerals. Their names and functions are also the same.

  In the present embodiment, a case where the image forming apparatus according to the present invention is applied to a tandem digital color copying machine (hereinafter referred to as a copying machine) will be described.

  However, the image forming apparatus according to the present invention is not limited to a copying machine, and an MFP (Multi Function Peripheral), which is a printer, a facsimile machine, or a complex machine thereof, as long as the image forming apparatus uses a DC brushless motor as a drive mechanism. It may be. Further, the printing method is not limited to the tandem method, and is not limited to the digital method. Furthermore, it may be a monochrome machine instead of a color machine.

  The color tandem type image forming apparatus is composed of four color image forming units each including a developing device arranged along an intermediate transfer belt as an intermediate transfer member. The image is transferred to the intermediate transfer belt (primary transfer), and a multicolor image is formed by superimposing each color toner. Further, the image superimposed on the intermediate transfer belt is transferred onto a sheet as a printing medium (secondary transfer), and output through a fixing process.

  FIG. 1 is a schematic cross-sectional view showing an outline of a hardware configuration of a copying machine 1 according to the present embodiment, to which the image forming apparatus according to the present invention is applied. The copying machine 1 is a tandem digital color copying machine, and sequentially superimposes four color toners of yellow (Y), magenta (M), cyan (C), and black (K) to form a color image. Form.

  Referring to FIG. 1, the copying machine 1 according to the present embodiment includes an image reading unit 10, a paper transport unit 20, an image forming unit 30, and a paper storage unit 40.

The image reading unit 10 includes a loading table 3 for setting a document, a document table glass 11, a conveyance unit 2 that automatically conveys documents set on the loading table 3 one by one to the document table glass 11, And a discharge table 4 for discharging the read document. Further, the document reading unit 10 includes a scanner (not shown). The scanner moves parallel to the platen glass 11 by a scan motor. The scanner has an exposure lamp that illuminates the document, a reflection mirror that changes the direction of the reflected light from the document, a mirror that changes the optical path from the reflection mirror, a lens that collects the reflected light, and an electrical signal depending on the received reflected light 3 row (R, G, B) CCD (Charge Coupled Device)
) And the like.

  The document transported by the transport unit 2 is set on the document table glass 11 and is exposed and scanned when the scanner moves in parallel with the document table glass 11. The reflected light from the document is converted into an electrical signal by the photoelectric conversion element and input to the image forming unit 30.

  The image forming unit 30 is suspended by a plurality of rollers 32, 33, and 34 so as not to be loosened, and these rollers rotate counterclockwise (in the direction of arrow A in FIG. 1) in FIG. And an intermediate transfer belt 31 that is an endless belt rotating in the same direction, and yellow (Y), magenta (M), cyan (C), and black (K) colors arranged along the intermediate transfer belt 31 at predetermined intervals. The image forming units 21Y, 21M, 21C, and 21K corresponding to the toner (representing these as the image forming units 21), the developing device included in each image forming unit 21, the photosensitive member, and the intermediate transfer belt 31 are used. A pair of transfer rollers 25Y, 25M, 25C, and 25K (these are representatively referred to as transfer rollers 25), and a fixing device 36 that fixes the toner image transferred to the intermediate transfer belt 31 after being transferred to the paper. Although not shown includes a controller 100, including CPU (Central Processing Unit), a memory 101 for storing a program executed by the controller 100.

  The paper storage unit 40 includes a paper feed cassette 41 that stores the paper S, which is a printing medium, and the paper transport unit 20 includes rollers 42, 43, 35, 37 for transporting the paper S from the paper feed cassette 41, and A paper discharge tray 38 for discharging printed paper is included.

  The controller 100 reads out and executes a program from the memory 101 based on an instruction signal input from an operation panel (not shown) or the like, and controls the above-described units. Further, the controller 100 may be provided with a timer such as a timer, and execute the program when a predetermined time is measured. The controller 100 and the memory 101 may be provided in the image reading unit 10 or the paper transport unit 20 other than the image forming unit 30.

  The controller 100 executes the above-described program, performs predetermined image processing on the image signal input from the image reading unit 10 or an external device, and performs color conversion to each color of yellow, magenta, cyan, and black. Create a signal. The image color data for cyan, the image color data for magenta, the image color data for yellow, and the image color data for black created by the controller 100 for each color are the controller 100 to the exposure unit of the image forming unit 21.

  The exposure device outputs a laser beam to the photoconductor based on the image data input from the controller 100, so that the surface of the uniformly charged photoconductor is exposed according to the image data, and the electrostatic latent image is generated. It is formed. A developing bias voltage is applied to the developing roller, and a potential difference is generated between the developing roller and the latent image potential of the photoreceptor. In this state, charged toner is supplied to form a toner image on the surface of the photoreceptor. The toner image formed on the surface of the photosensitive member is transferred to the intermediate transfer belt 31 as an image carrier by a constant voltage or constant current transfer roller 25. This is called primary transfer.

  The toner image primarily transferred to the intermediate transfer belt 31 is transferred onto the paper S conveyed from the paper feed cassette 41 by the roller 34. This is called secondary transfer. The toner image secondarily transferred to the paper is fixed on the paper by the fixing device 36 and is discharged to the paper discharge tray 38 as an electrophotographic image.

  Of the above-described configuration of the copying machine 1, as a driving mechanism, for example, a mechanism for driving the photosensitive member and various rollers in the image forming unit 21, a mechanism for driving the fixing device 36, and the rollers 42, 43, and 35 of the paper transport unit 20 , 37 can be used as a mechanism for driving the DC brushless motor. In the present invention, there is no limitation on which drive mechanism the DC brushless motor is used in, and any DC brushless motor may be used. Moreover, you may be used with the other mechanism.

  In the copying machine 1 according to the present embodiment, the driving of the DC brushless motor is controlled by the CPU 200 in the controller 100.

  FIG. 2 is a diagram for explaining a configuration in which the driving of the DC brushless motor is controlled by the CPU 200 in the controller 100.

  Referring to FIG. 2, the functions shown in CPU 200 are functions mainly formed in CPU 200 when CPU 200 reads and executes a program from memory 101, and at least some of them are shown in FIG. It may be formed by a hardware configuration.

  A motor unit 60 controlled by the CPU 200 and a motor driver circuit 300 for driving the motor 62 of the motor unit 60 are shown as hardware configurations.

  The motor control system according to the embodiment of the present invention is a system in which the feedback control of the motor unit is not realized by hardware as in the conventional configuration described in FIG.

  The motor unit 60 includes a motor 62 and an FG sensor 64 that generates an FG pulse that is a rotation signal based on a change in magnetic flux according to the rotation speed of the rotor of the motor 62.

  The motor driver circuit 300 receives a control signal input from the CPU 200 and adjusts a current for driving the motor 62.

  The CPU 200 compares the pulse detection unit 215 that detects the FG pulse from the FG sensor 64 with the target speed signal (clock signal) input from the outside and the FG pulse detected by the pulse detection unit 215 to obtain an error value. And a control for outputting the result of the PID calculation processing to the motor driver circuit 300. The PID calculation processing unit 210 calculates the proportional term P, the integral term I and the differential term D according to the detected error value. A signal output unit 220 for generating a signal.

  Although not shown, a clock signal corresponding to the target speed is generated and input to the CPU 200 using an oscillation circuit or the like built in the controller 100. A clock signal corresponding to the target speed can be generated inside the CPU 200, or can be input from the outside of the controller 100. It is assumed that information necessary for generating a clock signal corresponding to the target speed is stored in the memory 101.

FIG. 3 is a diagram illustrating a block diagram of the servo mechanism according to the embodiment of the present invention.
Referring to FIG. 3, the feedback control system is configured as shown here. Specifically, a pulse of a clock signal corresponding to the target speed is input, and a frequency deviation (error) from the current motor FG pulse is given to the frequency PID block 70. The phase deviation between the pulse of the clock signal corresponding to the target speed and the current FG pulse of the motor is given to the phase PID block 78.

  Then, the low-pass filter 72 included in the signal output unit 220 which is a digital filter is obtained by adding the processing result obtained by the PID calculation processing from the frequency PID block 70 and the processing result obtained by the PID calculation processing from the phase PID block 78. To the motor block 74 as a motor output instruction.

  The low-pass filter 72 is provided as noise removal means. Here, it is assumed that the digital filter is formed of an FIR filter, an IIR filter, or a notch filter.

  A speed signal (N (r / m)) is output from the motor block 74, the speed of the motor block 74 is converted into an FG pulse by the FG block 76, and a deviation (error) from the target speed signal (clock signal) is calculated. Is done.

FIG. 4 is a block diagram inside the motor block 74.
Referring to FIG. 4, a motor output instruction input via low-pass filter 72 is converted into a voltage value by a PWM chopping gain.

Then, by calculating the difference between the converted voltage value by the feedback voltage and the PWM chopping gain calculated by the induced voltage coefficient K _E, drive winding impedance (1 / Ra) based on the difference value between the voltage value / (1 + sτ _E ) is converted into current. Then, it is converted into an output torque according to the converted current value and the torque constant K _T. The output torque is converted into a rotational speed by the rotor inertia (kj / sT _M ). The converted rotation speed is converted into a feedback voltage by the induced voltage coefficient K _E as described above.

FIG. 5 is a flowchart illustrating a motor control method according to the embodiment of the present invention.
Referring to FIG. 5, first, a target speed is set (step S0). Specifically, a target speed signal (clock signal) is input.

  Then, motor driving is started (step S1). It is assumed that a control signal is output from the CPU 200 so that the target speed (rotation speed) is reached at the start. For example, it is possible to store a correspondence table between the target speed and the control signal level in the memory 101 and set the control signal level corresponding to the target speed signal input with reference to the correspondence table. It is.

  Next, the detection of the speed error is started (step S2), the frequency error of the FG pulse is detected (step S3), and the phase error of the FG pulse is detected (step S4). Specifically, the PID arithmetic processing unit 210 receives an FG pulse detected by the pulse detection unit 215, compares the frequency of the target speed signal (clock signal) with the frequency of the FG pulse, and detects a frequency error. Execute. Similarly, the PID arithmetic processing unit 210 compares the phase of the target speed signal (clock signal) with the phase of the FG pulse to detect a phase error.

  Then, regarding the frequency error, it is determined whether or not there is a frequency error (step S4). Regarding the frequency error, it is possible to determine that there is a frequency error when there is an error in a range exceeding the error margin by looking at a certain margin of error (margin) with the target value.

  If it is determined in step S4 that there is a frequency error, a frequency PID calculation process is executed based on a preset gain (step S5).

And it progresses to the addition process of step S6.
Further, regarding the phase error, it is determined whether or not there is a phase error (step S8). Regarding the phase error, it is possible to determine that there is a phase error when there is an error in a range exceeding the error margin by looking at a certain margin of error (margin) with the target value.

  If it is determined in step S8 that there is a phase error, a phase PID calculation process is executed based on a preset gain (step S9).

And it progresses to the addition process of step S6.
On the other hand, if it is determined in step S4 that there is no frequency error, the process proceeds to step S6. In this case, since there is no frequency error, there is no new error calculation result. That is, the same result as the previous time is output.

  If it is determined in step S8 that there is no phase error, the process proceeds to step S6. In this case, since there is no phase error, the new calculation result is set to 0 and the process proceeds to addition processing.

  In the addition process, the result of the phase PID calculation process and the result of the frequency PID calculation process are added (step S6). When there is no frequency error, the calculation result obtained by the previous frequency PID calculation process is used. When there is no phase error, the calculation result obtained by the previous phase PID calculation process is used.

  Then, based on the addition result, which is the processing result of the PID arithmetic processing unit 210, the signal output unit 220 instructs the motor driver circuit to output a control signal (step S10).

  Then, as described above, it is determined whether or not a motor stop instruction is input (step S11). If a motor stop instruction is not input, the process proceeds to step S2, and the above-described steps are repeated until the motor stops. .

If a motor stop instruction is input in step S11, the process ends (END).
As an example, the motor stop instruction can be determined to have been input when the input of the target speed signal is stopped. In particular, the motor stop instruction does not follow the input of the target speed signal, and any means can be used as long as the motor stop instruction can be recognized.

  The motor control system according to the embodiment of the present invention is a system in which feedback control of the motor is executed on the CPU side instead of forming a proportional integration circuit using hardware as in the conventional configuration. Therefore, unlike the conventional circuit that performs gain tuning by changing parts in response to load fluctuations in each model and each application, it is possible to share the motor control board because it is configured to allow gain tuning on the CPU side. Is possible.

FIG. 6 is a diagram illustrating a motor control board according to the embodiment of the present invention.
Referring to FIG. 6, DC brushless motor unit 60 and motor driver circuit 300 are provided in the motor control board according to the embodiment of the present invention. In addition, it is designed so that a resistance element or the like can be connected to the motor driver circuit 300 externally. Specifically, the motor driver circuit is formed by one packaged chip, and has external pins EP serving as a plurality of input or output pins, and the CPU 200 provided on the control board side via the external pins EP. And are electrically coupled.

  The motor driver circuit 300 is connected to the DC brushless motor unit 60 via the external pin EP.

  As described above, the DC brushless motor unit 60 includes the motor 62 and the FG sensor 64 for detecting the rotation speed (the number of rotations) of the motor 62. The FG sensor 64 generates an FG signal (FG pulse) that is a rotation signal based on a change in magnetic flux according to the rotation speed (number of rotations) of the rotor of the motor 62. Then, the FG signal is input to the pulse detection unit 215 of the CPU 200 as described above.

  The motor driver circuit 300 generates an operational amplifier AMP that receives a control signal input from the CPU 200 and a PWM (Pules Width Modulation) signal for setting an amount of current that is supplied to the current supply unit 310 by receiving an output signal from the operational amplifier AMP. A PWM chopper unit 305 for adjusting the current supplied to the motor 62 in accordance with the PWM signal of the PWM chopper unit 305.

  The operational amplifier AMP is externally connected to a resistance element to form an amplifier circuit. Specifically, one input node (− side) and the output node of the operational amplifier AMP are connected to the resistance element R1 via the external pin EP. The other input node (+ side) of the operational amplifier AMP is connected to the reference voltage Vref. Further, one input node (− side) of the operational amplifier AMP is connected to an output node of a signal output unit 220 (not shown) of the CPU 200 via a resistance element R2.

  With this configuration, the operational amplifier AMP forms an inverting amplifier circuit whose amplification factor (−R1 / R2) is based on the resistance values of the resistance elements R1 and R2.

  In this example, as an example, the resistance values of the resistance elements R1 and R2 are made equal to form a buffer circuit (inverting amplifier circuit) having an amplification factor of 1. That is, a control signal that is an analog signal output from the CPU 200 is input to the PWM chopper unit 305 via the buffer circuit, and motor control of the DC brushless motor unit 60 is executed.

  Compared with the configuration of the conventional motor control board described with reference to FIG. 9, a speed detection unit 1025, a speed deviation signal generation unit 1022, a phase deviation signal generation unit 1024, and a proportional integration circuit for executing feedback control that is PI control This is equivalent to a configuration in which a resistor, a capacitive element, and the like for forming are removed.

  Therefore, the layout area is simpler than that of the conventional motor control board. In addition, the operational amplifier AMP used as a proportional integration circuit in the conventional motor control board can be easily changed to a buffer circuit, that is, the resistance value of the external resistor element and the capacitor element can be adjusted and executed. Since the gain tuning can be executed on the CPU side, it is easy to share the motor driver circuit, and a motor driver circuit with high versatility can be realized.

  In addition, the motor is not controlled based on two instruction signals such as the acceleration instruction signal and the deceleration instruction signal as in the conventional system, but is a system controlled using a single control signal. It becomes possible to control.

  In the above description, the control signal that is an analog signal is output from the signal output unit 220 of the CPU 200 and is directly input to the operational amplifier AMP. However, for example, a case where a PWM signal is output from the CPU is also conceivable.

  FIG. 7 is a diagram illustrating a part of CPU 200 # according to the modification of the embodiment of the present invention.

  Referring to FIG. 7, here, CPU 200 # and smoothing circuit 240 are shown. For example, when a PWM signal is output as a control signal from the PWM signal generation circuit 230 in the signal output section of the CPU 200 #, a smoothing circuit 240 can be provided between the CPU 200 # and the motor driver circuit 300.

  The PWM signal output from the CPU 200 # by the circuit can be smoothed by the smoothing circuit 240 and input to the operational amplifier AMP that is a buffer circuit as an analog signal control signal.

  The smoothing circuit 240 can be provided outside or inside the CPU 200 #.

  Note that it is also possible to provide a program that causes a computer to function as a controller that controls the image forming apparatus and executes the control described with reference to FIG. Such a program is stored in a computer-readable recording medium such as a flexible disk attached to the computer, a CD-ROM (Compact Disk-Read Only Memory), a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card. And can be provided as a program product. Alternatively, the program can be provided by being recorded on a recording medium such as a hard disk built in the computer. A program can also be provided by downloading via a network.

  The program may be a program module that is provided as a part of a computer operation system (OS) and calls a required module at a predetermined timing in a predetermined arrangement to execute processing. In that case, the program itself does not include the module, and the process is executed in cooperation with the OS. A program that does not include such a module can also be included in the program according to the present invention.

  The program may be provided by being incorporated in a part of another program. Even in this case, the program itself does not include the module included in the other program, and the process is executed in cooperation with the other program. Such a program incorporated in another program can also be included in the program according to the present invention.

The provided program product is installed in a program storage unit such as a hard disk and executed. The program product includes the program itself and a recording medium on which the program is recorded.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic cross-sectional view showing an outline of a hardware configuration of a copier 1 according to an embodiment to which an image forming apparatus according to the present invention is applied. It is a figure explaining the structure by which the drive of a DC brushless motor is controlled by CPU200 in the controller 100. FIG. It is a figure explaining the block diagram of the servo mechanism according to the embodiment of the present invention. 4 is a block diagram inside a motor block 74. FIG. It is a flowchart explaining the motor control system according to the embodiment of the present invention. It is a figure explaining the motor control board according to the embodiment of the present invention. It is a figure explaining some CPU200 # according to the modification of embodiment of this invention. It is a figure explaining the structure of the conventional DC brushless motor. It is a figure explaining the structure in a motor control board.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Copier, 3 Loading stand, 2 Conveying part, 4 Ejection stand, 10 Image reading part, 11 Document glass, 20 Paper conveying part, 21,21Y, 21M, 21C, 21K Image forming part, 25, 25Y, 25M, 25C, 25K transfer roller, 30 image forming unit, 31 intermediate transfer belt, 32, 33, 34, 35, 37, 42, 43 roller, 38 paper discharge tray, 40 paper storage unit, 41 paper feed cassette, 60 motor unit, 62 motor, 64 FG sensor, 70 frequency PID block, 72 low-pass filter, 74 motor block, 76 FG block, 78 phase PID block, 100 controller, 101 memory, 200, 200 # CPU, 210 PID arithmetic processing unit, 215 pulse detection Part, 220 signal output part, 1000 control board, 1005 controller Circuit, 1010 motor circuit board, 1015 DCBL motor unit, 1016 motor, 1017 FG sensor, 300, 1020 motor driver circuit, 1022 speed deviation signal generation unit, 1024 phase deviation signal generation unit, 1025 speed detection unit, 1026 PWM chopper unit, 1028 Current supply unit, 1030 Proportional integration circuit.

Claims (5)

DC brushless motor,
A motor driver circuit for supplying a current corresponding to a command signal according to a target speed to the DC brushless motor in order to drive the DC brushless motor;
A control circuit that receives the rotation signal output from the motor driver circuit and adjusts the command signal output by the PID calculation control process so that the motor driver circuit follows the target speed;
The motor driver circuit is
An operational amplifier capable of connecting a circuit element provided outside the motor driver circuit to perform a predetermined function between one of two input nodes and an output node;
A current control unit for controlling the amount of current supplied to the DC brushless motor based on the output of the operational amplifier;
A first external resistor provided between one input node and an output node of the operational amplifier;
A second external resistor provided between the control circuit and one input node of the operational amplifier;
A reference voltage is supplied to the other input node of the operational amplifier,
The image forming apparatus, wherein the operational amplifier forms a buffer circuit having a change rate based on resistance values of the first and second external resistors. The motor driver circuit is formed on a semiconductor chip provided with a plurality of packaged input or output pins,
The image forming apparatus according to claim 1, wherein the first external resistor is connected using pins corresponding to one input node and an output node of the operational amplifier among the plurality of input or output pins.   The image forming apparatus according to claim 1, wherein the command signal is an analog signal. The command signal is output as a PWM signal,
The image forming apparatus according to claim 1, further comprising a smoothing circuit that smoothes the PWM signal between the control circuit and one input node of the operational amplifier.   The control circuit detects a deviation from the number of pulses of the rotation signal as the PID calculation control process, executes a first PID calculation control process for adjusting a frequency error, and calculates a phase error of the pulse of the rotation signal. The second PID calculation control process that detects and adjusts the phase error is executed in parallel, and the command signal is adjusted based on the calculation results of the first and second PID calculation control processes. The image forming apparatus described.

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