JP2009089132A - Solid-state imaging device - Google Patents

Abstract

A signal from a pixel corresponding to a focus detection area is preferentially output.
In a photoelectric conversion unit having a plurality of pixels arranged in two dimensions, a pixel corresponding to a preset focus detection region includes a focus detection pixel. The vertical shift register circuit 14 and the vertical drive circuit 16 can preferentially select a row of pixels corresponding to the focus detection area among the pixels 11 of the photoelectric conversion unit 10. The horizontal shift register circuit 18 can preferentially select a signal corresponding to a column of pixels corresponding to the focus detection area among signals read by the reading circuit 19 from each pixel in the selected row. The read circuit 19 outputs a signal selected by the horizontal shift register circuit 18 among the read signals.
[Selection] Figure 1

Description

  The present invention relates to a solid-state imaging device capable of partial reading.

  In recent years, video cameras and electronic cameras have been widely used. For these cameras, CCD type or CMOS type solid-state imaging devices are used. In these solid-state imaging devices, a plurality of pixels that generate signal charges according to the amount of incident light are arranged in a matrix. A signal charge generated in each pixel or an electric signal corresponding to the signal charge is output to the outside via a CCD or a signal line in accordance with a drive signal output from the scanning circuit under the instruction of the timing generator.

  In the solid-state imaging device as described above, focus detection pixels are arranged corresponding to a preset focus detection region, and passed through different positions of the photographing lens based on signals output from the focus detection pixels. It is known that a pupil division phase difference type focus detection can be performed by detecting a shift amount of a pair of images due to a light beam (see Patent Document 1).

JP 2000-156823 A

  Since the solid-state imaging device disclosed in Patent Document 1 cannot preferentially output signals from the pixels corresponding to the focus detection area, even when only focus detection is desired, the signals from other pixels can be output. The output must also be read. Therefore, there is a problem that focus detection cannot be performed at high speed.

The invention according to claim 1 is a photoelectric conversion unit having a plurality of pixels arranged in two dimensions, a vertical scanning circuit for selecting a row of pixels, and a signal output from each pixel in the row selected by the vertical scanning circuit. A solid-state imaging device comprising: a readout circuit that reads out a signal; and a horizontal scanning circuit that selects one of the signals read out by the readout circuit in association with a column of pixels and outputs the selected signal from the readout circuit The pixel corresponding to a preset focus detection area among the pixels includes a focus detection pixel that outputs a signal for use in focus detection, and the vertical scanning circuit corresponds to the focus detection area. The horizontal scanning circuit can preferentially select a signal corresponding to a pixel column corresponding to the focus detection area.
According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, as a readout circuit, a signal output from each pixel in a row selected by the vertical scanning circuit is read out for each of different pixel columns. The horizontal scanning circuit has a readout circuit and a second readout circuit, and causes the first readout circuit and the second readout circuit to select and output signals corresponding to different columns of pixels, respectively. is there.
According to a third aspect of the present invention, in the solid-state imaging device according to the second aspect, the pair of focus detection areas are set side by side in the pixel row direction, and the first readout circuit is the row selected by the vertical scanning circuit. The signal output from each pixel is read out from the pixel column including the pixel corresponding to one of the pair of focus detection regions, and the second readout circuit outputs from each pixel in the row selected by the vertical scanning circuit The horizontal scanning circuit reads two signals corresponding to two columns of pixels respectively corresponding to the pair of focus detection areas. At the same time, the selected signals are output from the first readout circuit and the second readout circuit, respectively.
According to a fourth aspect of the present invention, in the solid-state imaging device according to the third aspect, the photoelectric conversion unit outputs a focus detection pixel and a signal for use in imaging corresponding to the focus detection region to the photoelectric conversion unit. Are arranged in a predetermined arrangement pattern, and the arrangement pattern is configured such that the arrangement of the focus detection pixels and the imaging pixels in each of the pair of focus detection areas is reversed. Two signals corresponding to two columns of inverted pixels are simultaneously selected.
According to a fifth aspect of the present invention, in the solid-state imaging device according to any one of the second to fourth aspects, the focus detection region is divided into two regions at equal positions in the row direction of the pixels, and the first readout is performed. The circuit reads out a signal output from each pixel in the row selected by the vertical scanning circuit for a pixel column including a pixel corresponding to one of the two regions, and the second readout circuit is read by the vertical scanning circuit. The signal output from each pixel in the selected row is read out for the column of pixels including the pixel corresponding to the other of the two regions, and the horizontal scanning circuit corresponds to two columns of pixels corresponding to the two regions, respectively. These two signals are simultaneously selected, and the selected signals are output from the first readout circuit and the second readout circuit, respectively.
According to a sixth aspect of the present invention, in the solid-state imaging device according to the fifth aspect, the photoelectric conversion unit outputs a focus detection pixel and a signal for use in imaging corresponding to the focus detection region. Are arranged in a predetermined arrangement pattern, and the arrangement pattern is configured such that the arrangement of the focus detection pixels and the imaging pixels in each of the two regions is inverted, and the horizontal scanning circuit is inverted. The two signals corresponding to two columns of the selected pixels are simultaneously selected.

  According to the present invention, a signal from a pixel corresponding to a focus detection region can be output with priority.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

-First embodiment-
FIG. 1 is a schematic configuration diagram showing a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing the pixel 11 in FIG. FIG. 3 is a circuit diagram showing the vertical drive circuit 16 in FIG. FIG. 4 is a circuit diagram showing the readout circuit 19 in FIG. FIG. 5 is a circuit diagram showing the vertical shift register circuit 14 in FIG.

  The solid-state imaging device according to the present embodiment is mounted on a digital camera or the like, and is used to capture a subject image formed by an incident light beam from a photographing lens. Furthermore, during autofocus, pupil detection is performed by detecting the amount of deviation between a pair of images caused by light beams that have passed through different positions of the photographic lens using focus detection pixels arranged in a portion corresponding to a preset focus detection area. Perform phase difference detection.

  As shown in FIG. 1, the solid-state imaging device according to the present embodiment includes a CMOS type image sensor 2, a timing generator 3, and a control circuit 4. The timing generator 3 supplies drive pulses and the like to each part of the image sensor 2 as will be described later. Further, as will be described later, the control circuit 4 supplies control signals CONV1 to CONVj and CONH1 to CONHk to the vertical shift register circuit 14 and the horizontal shift register circuit 18.

  As shown in FIG. 1, the image sensor 2 includes a photoelectric conversion unit 10 in which a plurality of pixels 11 are arranged in a two-dimensional matrix in n rows and m columns, a vertical shift register circuit 14 that constitutes a vertical scanning circuit, and A vertical drive circuit 16, a horizontal shift register circuit 18 constituting a horizontal scanning circuit, and a readout circuit 19 are provided.

  Each pixel 11 of the photoelectric conversion unit 10 photoelectrically converts incident light to generate a signal corresponding to the incident light. As will be described later, the photoelectric conversion unit 10 outputs, as will be described later, a normal imaging pixel that outputs a signal for imaging a subject image and a signal that is used for focus detection during autofocus. There are focus detection pixels.

  In this embodiment, as shown in FIG. 2, each pixel 11 includes a selection transistor Ta, a source follower amplification transistor Tb, a reset transistor Tc, a transfer transistor Td, and a photodiode PD. . These transistors Ta to Td are assumed to be N channel MOS transistors. Therefore, the transistors Ta, Tc, and Td are turned on when their gates become H level. In FIG. 2, Vcc is a power source.

  In the present embodiment, each pixel 11 has the circuit configuration shown in FIG. 2 regardless of whether the pixel is an imaging pixel or a focus detection pixel. In the imaging pixel, an opening for allowing a light beam to pass through is provided in the entire light receiving surface of the photodiode PD. On the other hand, as will be described later, in the focus detection pixel, an opening is provided only for a part of the light receiving surface of the photodiode PD, and the other parts are shielded from light.

  As shown in FIGS. 1 and 2, the gates of the selection transistors Ta of the pixels 11 are commonly connected to the selection line 20 for each row. The gate of the reset transistor Tc of the pixel 11 is commonly connected to the reset line 21 for each row. The gates of the transfer transistors Td of the pixels 11 are commonly connected to the transfer line 22 for each row. The sources of the amplification transistors Tb of the pixels 11 are commonly connected to the vertical signal lines 32-1 to 32-m for each column. As shown in FIG. 1, source follower read constant current sources 33-1 to 33-m are connected to the vertical signal lines 32-1 to 32-m. 2 indicates the pixel 11 in the nth row and the first column.

  Selection pulses φsel1 to φseln are applied to the selection lines 20 of the respective rows of the pixels 11, reset pulses φrst1 to φrstn are applied to the reset lines 21 of the respective rows of the pixels 11, and transfer pulses φtx1 to φtxn are applied to the transfer lines 22 of the respective rows of the pixels 11. Are respectively supplied from the vertical drive circuit 16 as pixel row drive pulses. Each pixel 11 in the row to which the pixel row driving pulse is supplied performs a signal read operation to the corresponding vertical signal line 32-1 to 32-m.

  The vertical shift register circuit 14 receives the vertical start pulse φSTV and the two-phase clock signals φV1 and φV2 as drive pulses from the timing generator 3 and receives control signals CONV1 to CONVj from the control circuit 4, and selects a row according to them. Vertical shift pulses φSV <b> 1 to φSVn are output for each row of the pixels 11 as a signal defining the period and timing according to the H level. The configuration of the vertical shift register circuit 14 will be described in detail later.

  As shown in FIG. 3, the vertical drive circuit 16 includes unit circuits 60 provided for each row of the pixels 11. Each unit circuit 60 includes an AND gate 61, a level shift circuit 62, a NAND gate 63, and an AND gate 64. Each unit circuit 60 includes a selection pulse φSEL that is the source of the selection pulses φsel1 to φseln described above, a reset pulse φRST that is a source of the reset pulses φrst1 to φrstn, and a transfer pulse φTX that is a source of the transfer pulses φtx1 to φtxn. From the timing generator 3 as a drive pulse.

  Each unit circuit 60 takes the AND of the vertical shift pulse and transfer pulse φTX in the same row among the vertical shift pulses φSV1 to φSVn from the vertical shift register circuit 14 by the AND gate 61, and sets the level of the output thereof. By changing the level to a required level by the shift circuit 62, a transfer pulse (for example, φtx2 if the row is the second row) constituting the pixel row driving pulse of the row is generated, and this is transferred to the transfer line 22 of the row. To supply. In addition, each unit circuit 60 takes the NAND of the vertical shift pulse and reset pulse φRST in the same row among the vertical shift pulses φSV1 to φSVn from the vertical shift register circuit 14 by the NAND gate 63, so that the pixel in the row A reset pulse constituting the row driving pulse (for example, φrst2 if the row is the second row) is generated and supplied to the reset line 21 of the row. Each unit circuit 60 takes an AND of the vertical shift pulse and the selection pulse φSEL in the same row among the vertical shift pulses φSV1 to φSVn from the vertical shift register circuit 14 by the AND gate 64, thereby A selection pulse constituting the pixel row driving pulse (for example, φsel2 if the row is the second row) is generated and supplied to the selection line 20 of the row.

  The horizontal shift register circuit 18 receives the horizontal start pulse φSTH and the two-phase clock signals φH1 and φH2 as drive pulses from the timing generator 3, and receives control signals CONH1 to CONHk from the control circuit 4, and selects a column according to them. Horizontal shift pulses [phi] SH1 to [phi] SHm are output as signals defining the period and timing.

  The readout circuit 19 is the same as the readout circuit employed in, for example, the solid-state imaging device disclosed in FIG. 5 of JP-A-8-295991. Briefly, as shown in FIG. 4, the readout circuit 19 includes a signal output line 38, a dark output line 39, output amplifiers 38a and 39a, an optical signal clock line 41a, a dark output clock line 42a, and a horizontal readout selection. MOS transistors THS1, THS2, THS3, THD1, THD2, THD3, dark light signal transfer MOS transistors TS1, TS2, TS3, dark output transfer MOS transistors TD1, TD2, TD3, light signal output storage capacitors CS1, CS2, CS3, dark output storage capacitors CD1, CD2, and CD3 are included. CHS and CHD indicate parasitic capacitances of the signal output line 38 and the dark output line 39, respectively. The read circuit 19 operates according to drive pulses φRH, φTS, and φTD supplied from the timing generator 3.

  Here, the configuration of the vertical shift register circuit 14 will be described in detail with reference to FIG. For convenience of explanation, in FIG. 5, the number of rows n of the pixels 11 is assumed to be 9, but it is needless to say that the number is not limited to this.

  In the present embodiment, the vertical shift register circuit 14 includes n-stage (9 stages in FIG. 5) unit circuits 70 connected in cascade. The output of the unit circuit 70 in each stage is vertical shift pulses φSV1 to φSVn for each row of the pixels 11. For example, the output of the unit circuit 70 in the second stage is the vertical shift pulse φSV2 in the second row of the pixels 11.

  The unit circuit 70 in each stage transmits a signal corresponding to an input signal to the unit circuit 70 as an output signal from the unit circuit by a shift operation according to the clock signals φV1 and φV2, and the clock signal φV1. , ΦV2 and the second operation mode in which a signal corresponding to an input signal to the unit circuit 70 is transmitted as an output signal from the unit circuit 70 can be selectively performed immediately. .

  In the present embodiment, as shown in FIG. 5, the unit circuit 70 in each stage includes an input unit a to which the input signal is input, an output unit f to which the output signal is output, and a clock of one phase. Clock input part b to which signal φV1 is input, clock input part c to which clock signal φV2 of the other phase is input, clock input part d to which an inverted signal of clock signal φV1 is input, and inversion of clock signal φV2 And a clock input unit e to which a signal is input.

  An example of the configuration of the unit circuit 70 is shown in FIG. In the example illustrated in FIG. 6, the unit circuit 70 is configured as a dynamic D-type flip-flop using a clocked inverter, and includes clocked inverters 71 and 72 that are sequentially cascaded from the input unit a to the output unit f. Has been. C1 and C2 in FIG. 6 are parasitic capacitances.

  FIG. 7 is a circuit diagram showing a more specific configuration of the unit circuit 70 shown in FIG. In FIG. 7, the same or corresponding elements as those in FIG. 6 are denoted by the same reference numerals. In this example, the clocked inverter 71 includes P-channel MOSFETs Q1 and Q2 and N-channel MOSFETs Q3 and Q4 connected in series between the power supply Vcc and the ground, as shown in FIG. Similarly, the clocked inverter 72 includes P-channel MOSFETs Q5 and Q6 and N-channel MOSFETs Q7 and Q8 connected in series between the power supply Vcc and the ground. The gates of Q4, Q8, Q1, and Q5 are connected to the clock input sections b, c, d, and e, respectively, the gates of Q2 and Q3 are connected to the input section a, and the gates of Q6 and Q7 are shared. Are connected to the connection midpoint between Q2 and Q3, and the connection midpoint between Q6 and Q7 is connected to the output section f.

  In the example shown in FIGS. 6 and 7, the clock signal φV1 of one phase and its inverted signal are inputted to the clock input parts b and d, respectively, and the clock signal φV2 of the other phase is inputted to the clock input parts c and e. When the inverted signal is input, the unit circuit 70 outputs a signal corresponding to the input signal (signal input to the input unit a) to the unit circuit 70 from the unit circuit by the shift operation according to the clock signals φV1 and φV2. The first operation mode transmitted as a signal (a signal output from the output unit f) is performed. On the other hand, when the clock input units b and c are set to the H level and the clock input units d and e are set to the L level, the unit circuit 70 causes the clocked inverters 71 and 72 to operate as simple inverters, respectively, and the clock signal φV1, Secondly, a signal corresponding to an input signal (signal input to the input unit a) to the unit circuit 70 is immediately transmitted as an output signal (signal output from the output unit f) from the unit circuit 70 regardless of φV2. The operation mode is performed.

  Other examples of the configuration of the unit circuit 70 are shown in FIGS. In the example shown in FIG. 8, the unit circuit 70 is configured as a dynamic D-type flip-flop using a transmission gate, and is connected in cascade from the input part a to the output part f, an inverter 74, and a transmission gate. 75 and an inverter 76. C3 and C4 in FIG. 8 are parasitic capacitances.

  In the example shown in FIG. 9, the unit circuit 70 is configured as a static D-type flip-flop using a clocked inverter, and is connected in cascade from the input unit a to the output unit f, an inverter 78, A clocked inverter 79 and an inverter 80, a clocked inverter 81 connected in reverse parallel to the inverter 78, and a clocked inverter 82 connected in reverse parallel to the inverter 80 are configured.

  In the example shown in FIG. 10, the unit circuit 70 is configured as a static D-type flip-flop using a transmission gate, and is connected in cascade from the input part a to the output part f, an inverter 84, and a transmission gate. 85, an inverter 86, a first feedback circuit composed of a series circuit of an inverter 87 and a transmission gate 88, a first feedback circuit connected in parallel to the inverter 84, and a series circuit of an inverter 89 and a transmission gate 90 The second feedback circuit is a second feedback circuit connected in parallel to the inverter 86.

  The unit circuits 70 in each stage may all be circuits having the same configuration, or some of the unit circuits 70 may be configured differently from other unit circuits 70. For example, all the unit circuits 70 may be configured by the circuits having the configurations shown in FIGS. 6 and 7, or some of the unit circuits 70 may be configured by the circuits having the configurations shown in FIGS. 6 and 7 and other units. The circuit 70 may be configured by a circuit having the configuration shown in FIG.

  In the present embodiment, as shown in FIG. 5, in the vertical shift register circuit 14, the nine-stage unit circuit 70 is divided into a plurality of blocks BV1 to BVj. In FIG. 5, the number j of the blocks is 3, but the number is not limited to this. In the example shown in FIG. 5, each of the blocks BV1 to BVj is composed of three unit circuits 70. However, the number of unit circuits 70 belonging to each block may be an arbitrary number of one or more stages. The number of unit circuits 70 belonging to the block may be different.

  In the present embodiment, as shown in FIG. 5, the vertical shift register circuit 14 makes the operation mode performed by the unit circuit 70 at each stage of the block independent of other blocks for each of all the blocks BV1 to BVj. In addition, a switching setting unit that switches to and sets one of the first and second operation modes according to the control signals CONV1 to CONVj is provided.

  In the present embodiment, the switching setting unit is configured by individual switching setting units S1 to Sj provided on a one-to-one basis with respect to the blocks BV1 to BVj. As shown in FIG. 5, each individual switching setting unit S <b> 1 to Sj includes OR gates 91 and 92 and knot gates 93 and 94. Thereby, each individual switching setting unit S1 to Sj indicates that the unit circuit 70 of each stage of the corresponding block is set to the first mode at the L level and that the unit mode 70 is set to the second mode at the H level. Control signal (corresponding control signal among control signals CONV1 to CONVj from the control circuit 4) and when this control signal is at L level, the clock input part b of the unit circuit 70 of each stage of the corresponding block , D are inputted with the clock signal φV1 of one phase and its inverted signal, respectively, and the clock signal φV2 of the other phase and its inverted signal are inputted to the clock input portions c, e of the unit circuit 70 of each stage of the corresponding block. When the control signal is at the H level, the clock input parts b and c are set to the H level and the clock signals φV1 and φV2 regardless of the clock signals φV1 and φV2. Tsu has click input section d, the e so that the L level.

  In FIG. 5, one set of knot gates 93 and 94 is arranged in each block BV1 to BVj. However, the present invention is not limited to this configuration. The unit circuit 70 has a rule that an inverted signal of b input is connected to d and an inverted signal of c input is connected to e. Therefore, for example, each unit circuit 70 may have a configuration in which one set of knot gates 93 and 94 is arranged. In this case, the number of knot gates required increases, but the drive load per knot gate may be small, and the size may be small. As in the circuit of FIG. 5, one set of knot gates 93 and 94 is provided for each block (however, since a large number of unit circuits 70 need to be driven, a large size and high driving capability is required). Whether the small-sized knot gates 93 and 94 are arranged for each of the unit circuits 70 may be arbitrarily selected depending on the layout.

  Although the configuration of the horizontal shift register circuit 18 is not shown in the drawing, the horizontal shift register circuit 18 is configured in the same manner as the vertical shift register circuit 14. Regarding the configuration of the horizontal shift register circuit 18, in FIG. 5 and the description thereof related to the vertical shift register circuit 14, the vertical shift register circuit 14 is the horizontal shift register circuit 18, the vertical start pulse φSTV is the horizontal start pulse φSTH, and the clock signal φV1. , ΦV2 are clock signals φH1 and φH2, vertical shift pulses φSV1 to φSVn are horizontal shift pulses φSH1 to φSHm, n stages are m stages, block number j is block number k, blocks BV1 to BVj are blocks BH1 to BHk ( And control signals CONV1 to CONVj should be read as control signals CONH1 to CONHk, respectively.

  Next, an operation example of the solid-state imaging device according to the present embodiment will be described focusing on the operation of the vertical shift register circuit 14.

  FIG. 11 is a timing chart showing signals input to and output from the vertical shift register circuit 14 during normal all-pixel reading.

  11 assumes that the configuration of the vertical shift register circuit 14 is the number of stages (n = 9) and the number of blocks (j = 3) shown in FIG. In FIG. 11, the start pulse φSTV is determined at the falling edge of the clock signal φV1, and the vertical shift pulses φSV1 to φSVn are determined at the rising edge of the clock signal φV2. This also applies to FIGS. 12 and 13 described later.

  During normal all-pixel readout, as shown in FIG. 11, all control signals CONV1 to CONVj are set to the L level. As a result, the unit circuits 70 in the respective stages of all the blocks BV1 to BVj of the vertical shift register circuit 14 perform the first operation mode by the shift operation according to the clock signals φV1 and φV2, and the vertical shift pulses φSV1 to φSVn are sequentially performed. It becomes H level indicating selection. Similarly, during normal all pixel readout, all the control signals CONH1 to CONHj are set to the L level. As a result, the unit circuits 70 at the respective stages of all the blocks BH1 to BHk of the horizontal shift register circuit 18 perform the first operation mode by the shift operation according to the clock signals φH1 and φH2, and the horizontal shift pulses φSH1 to φSHn are sequentially applied to the columns. It becomes H level indicating selection. Although not shown in the drawing, each pulse from the timing generator 3 is supplied at the same timing as in the conventional solid-state imaging device. This is the same not only when reading all pixels but also when reading partially.

  Accordingly, all pixels 11 are sequentially read during normal all pixel reading.

  FIG. 12 is a timing chart showing an example of each signal inputted to and outputted from the vertical shift register circuit 14 at the time of partial reading.

  At the time of partial reading, for example, as shown in FIG. 12, control signals (of control signals CONV1 to CONVj) corresponding to the pixel range to be skipped from among the blocks BV1 to BVj of the vertical shift register circuit 14 are displayed. The corresponding control signal) is set to the H level, and the control signal (corresponding control signal among the control signals CONV1 to CONVj) corresponding to the pixel range to be read is set to the L level. FIG. 12 shows an example in which the pixel range to be skipped is the fourth to sixth lines. Therefore, in FIG. 12, the control signal CONV2 of the second block BV2 corresponding to the fourth to sixth rows is set to the H level, and the control signals CONV1 and CONV3 of the blocks BV1 and BV3 corresponding to the other rows are set to the L level. Yes. As a result, as shown in FIG. 12, the unit circuit 70 in each stage of the first and third blocks BV1 and BV3 of the vertical shift register circuit 14 performs the first operation mode, while the second block BV2 Since the unit circuit 70 of each stage performs the second operation mode, the jumping operation of jumping from the vertical shift pulse φSV3 of the last stage of the first block BV1 to the vertical shift pulse φSV7 of the first stage of the third block BV3 Is done.

  At the time of partial reading, the control signals (corresponding to control signals CONH1 to CONHk) corresponding to the pixel range to be skipped among the blocks BH1 to BHk (not shown) of the horizontal shift register circuit 18. Control signal) is set to the H level, and the control signal (corresponding control signal among the control signals CONH1 to CONHk) corresponding to the pixel range to be read is set to the L level. As a result, the unit circuit 70 at each stage of the block of the horizontal shift register circuit 18 corresponding to the pixel range to be skipped performs the first operation mode, while the unit circuit 70 at each stage of the other block In order to perform the second operation mode, the same interlace operation as that of the vertical shift register circuit 14 is performed.

  In this way, the interlaced scanning is performed on the pixels that are not read out while keeping the frequencies of the clock signals φV1 and φV2 and the clock signals φH1 and φH2 the same as when reading out all the pixels, and some of the pixels are all Reading is performed only for.

  By the way, as shown in FIG. 12, if the control signal CONV2 of the block BV2 corresponding to the pixel range to be skipped is set to H level over the entire period of partial reading, each stage of the corresponding block BV2 The vertical shift pulses φSV4 to φSV6 which are the outputs of the unit circuit 70 are also at the H level simultaneously with the shift pulse φSV3 which is the output of the last unit circuit 70 of the preceding block BV1, and when the third row is selected, the four rows The sixth to sixth rows are also selected at the same time. Therefore, as shown in FIG. 12, if the control signal CONV2 is set to the H level over the entire period at the time of partial reading, the pixels cannot actually be read normally.

  Therefore, in order to prevent this, actually, even if the vertical shift pulse, which is the output of the unit circuit 70 in each stage of the block corresponding to the pixel range to be skipped, becomes H level at the same time, readout of the pixel to be read out is performed. Is set to the H level timing of the control signal of the block corresponding to the pixel range to be skipped. Specifically, for example, the control signal of the block corresponding to the pixel range to be skipped is the pixel readout period of the row corresponding to the last unit circuit 70 of the readout block closest to the front side of the skipped block. The period required to transmit the signal (H level) to the unit circuit 70 in the foremost stage of the read block closest to the rear side of the skipped block in the period after the read period is set to the H level, and the rest is left. This period may be either the H level or the L level.

An example is shown in FIG. In FIG. 13, the block B corresponding to the pixel range to be skipped is read.
The control signal CONV2 of V2 becomes L at a time slightly earlier than the start time t1 of the pixel readout period P of the third row corresponding to the last unit circuit 70 of the readout block BV1 closest to the front side of the skipped block BV2. Is set to the H level at the time between the falling edge of the shift pulse φSV3 of the pixel in the third row corresponding to the unit circuit 70 in the final stage of the block BV1 and the end point of the period P, and the rising edge of the shift pulse φSV3. It remains at the H level from the falling point to a slightly later point. Other periods (periods with hatching in FIG. 13) may be either the H level or the L level.

  When the H level timing of the control signal CONV2 is set in this way, the vertical shift pulses φSV4 to φSV6 that are the outputs of the unit circuits 70 in the respective stages of the block BV2 corresponding to the pixel range to be skipped become H level. However, since the readout of the pixels in the third row corresponding to the unit circuit 70 in the final stage of the previous stage block BV1 has been completed at that time, the readout is not affected and the readout is performed normally. It can be carried out.

  The actual timing of the control signals CONV1 to CONVj of the vertical shift register circuit 14 has been described above, but the same applies to the actual timing of the control signals CONH1 to CONHk of the horizontal shift register circuit 18.

  Here, an example of the relationship between each region of the photoelectric conversion unit 10 and the block division method of the unit circuit 70 of the vertical shift register circuit 14 and the block division method of the unit circuit 70 of the horizontal shift register circuit 18 is shown in FIG. .

  In the example illustrated in FIG. 14, six focus detection regions R1 to R6 are set in advance in a region where the pixels 11 of the photoelectric conversion unit 10 are two-dimensionally arranged. Pixels 11 corresponding to the focus detection regions R1 to R6 include focus detection pixels in addition to normal imaging pixels. On the other hand, the pixels 11 corresponding to the regions other than the focus detection regions R1 to R6 do not include the focus detection pixels and are configured by only the imaging pixels.

  In the focus detection areas R3 and R4, the pixels 11 are arranged in an arrangement pattern as shown in FIG. 15, for example. In the focus detection region R3, focus detection pixels 11a and imaging pixels 11e are alternately arranged in the left column, and imaging pixels 11e and focus detection pixels 11b are alternately arranged in the right column. Yes.

  The focus detection pixels 11a and 11b are provided with a microlens 110 and an opening 111, respectively. The opening 111 is provided only for a part of the light receiving surface of each pixel. As a result, part of the incident light incident from the photographing lens and collected by the microlens 110 passes through the opening 111 and reaches the light receiving surface. Note that a portion where the opening 111 is not provided is shielded, and incident light does not reach the light receiving surface.

  Incident light that has passed through the opening 111 is photoelectrically converted in each focus detection pixel, and is output from each focus detection pixel to the readout circuit 19 as a light reception signal. Here, as shown in FIG. 15, in the focus detection pixel 11a and the focus detection pixel 11b, the position of the opening 111 is upside down. Therefore, a pair of images are formed on the respective light receiving surfaces by the light beams that have passed through different positions of the photographing lens. In the arrangement of FIG. 15, approximate images are formed on the focus detection pixels 11 a in the left column and the focus detection pixels 11 b in the right column as almost the same line.

  Therefore, when the focus position of the photographic lens is on the imaging surface of the photoelectric conversion unit 10, the image formed in each focus detection pixel 11a in the left column and each focus detection in the right column. Since the image formed on the pixel 11b substantially coincides, no phase difference occurs in the received light signal. However, when the focus position is ahead of the imaging surface (front pin) or behind (back pin), the image formed on each focus detection pixel 11a in the left column and the right column There is a deviation from the image formed on each focus detection pixel 11b. At this time, the image shift direction is reversed between the front pin and the rear pin. By detecting the amount and direction of the image shift as the phase difference of the light reception signal, the focus adjustment state of the photographing lens is detected.

  On the other hand, in the focus detection region R4, the focus detection pixels 11c and the imaging pixels 11e are alternately arranged in the upper row, and the imaging pixels 11e and the focus detection pixels 11d are alternately arranged in the lower column. ing. In the focus detection pixel 11c and the focus detection pixel 11d, the position of the opening 111 is reversed left and right. As a result, as described above, the focus adjustment state of the photographing lens is detected as the phase difference between the received light signals by the focus detection pixels 11c and 11d.

  In the other focus detection regions R1, R2, R5, and R6, similarly to the focus detection pixel R3 or R4, the focus detection pixels and the imaging pixels are alternately arranged to adjust the focus of the photographing lens. The state is detected as the phase difference of the received light signal.

  During autofocus, one or more of the focus detection areas R1 to R6 are selected, and the pixels corresponding to the selected focus detection area are partially read out. That is, the vertical shift register circuit 14 and the vertical drive circuit 16 preferentially select the row of the pixels 11 corresponding to any one of the focus detection areas R1 to R6. As a result, the light receiving signal output from each pixel 11 in the row is read by the reading circuit 19. Then, each light reception signal read by the readout circuit 19 by the horizontal shift register circuit 18, that is, one of the light reception signals from each pixel 11 in the row selected as described above, is converted into the pixel 11. Select in association with the column. The light reception signal thus selected is output from the readout circuit 19. Such readout operation is sequentially performed on each pixel 11 in the selected focus detection region, and by detecting the phase difference in the light reception signal from the focus detection pixel among the read light reception signals, the focus of the photographing lens is detected. It is possible to detect the adjustment state and perform focus adjustment according to the detection result.

  In the example shown in FIG. 14, the block division of the unit circuit 70 in the vertical shift register circuit 14 is performed at the boundaries in the vertical direction of the regions R1 to R6 in FIG. That is, the unit circuit 70 of the vertical shift register circuit 14 may be divided according to the blocks BV1 to BV9 in FIG. Further, the block division of the unit circuit 70 in the horizontal shift register circuit 18 is performed at the boundaries in the horizontal direction of the regions R1 to R6 in FIG. That is, the unit circuit 70 of the horizontal shift register circuit 18 may be divided according to the blocks BH1 to BH9 in FIG.

  By performing block division as described above, any of the focus detection regions R1 to R6 can be arbitrarily selected and partially read out. For example, when partially reading the focus detection region R1, the blocks BV1 to BV3 are skipped in the row direction and the block BH1 is skipped in the column direction. Then, pixels in a range specified by the blocks BV4 to BV6 and the block BH2 are sequentially selected and read out.

  According to the present embodiment, the vertical shift register circuit 14 and the vertical drive circuit 16 select the row of the pixels 11 of the photoelectric conversion unit 10, and the signal output from each pixel of the selected row is read by the readout circuit 19. read out. The horizontal shift register circuit 18 selects one of the signals read by the read circuit 19 in association with the column of the pixels 11, and outputs the selected signal from the read circuit 19. At this time, the vertical shift register circuit 14 and the vertical drive circuit 16 can preferentially select the row of pixels corresponding to the focus detection area, and further the horizontal shift register circuit 18 sets the pixel column corresponding to the focus detection area. The corresponding signal can be selected with priority. Therefore, the signal from the pixel can be preferentially read and output by the reading circuit 19. Since it did in this way, the signal from the pixel corresponding to a focus detection area can be preferentially output from a solid-state imaging device.

-Second Embodiment-
FIG. 16 is a schematic configuration diagram of a solid-state imaging device according to the second embodiment of the present invention. In FIG. 16, the same or corresponding elements as those of the solid-state imaging device according to the first embodiment shown in FIG. In FIG. 16, some of the signal lines shown in FIG. 1 are omitted. Further, although the arrangement of the pixels 11 in the photoelectric conversion unit 10 is omitted in 5 rows and 6 columns, in practice, a large number of pixels are arranged in a two-dimensional matrix as in FIG.

  The solid-state imaging device according to the present embodiment has two horizontal shift register circuits 18a and 18b and two read circuits 19a and 19b instead of the horizontal shift register circuit 18 and the read circuit 19 shown in FIG. . Further, column selection switches 51a and 51b for respectively selecting columns of the pixels 11 connected to the readout circuit 19a or 19b, and column selection transistors 53-1 to 53- controlled to be turned on / off by the column selection switches 51a and 51b. 6 and 54-1 to 54-6. In the solid-state imaging device according to the present embodiment, the horizontal shift register circuits 18a and 18b, the column selection switches 51a and 51b, and the column selection transistors 53-1 to 53-6 and 54-1 to 54-6 are used. A horizontal scanning circuit is configured.

  When an H level signal is applied to the gates of the column selection transistors 53-1, 53-3 and 53-5 by the column selection switch 51a, for example, the signal lines 32-1, 32-3 and 32-5 are applied to the signal lines 32-1, 32-3 and 32-5. The connected pixel 11 is connected to the horizontal shift register 18a and the readout circuit 19a. At this time, an L level signal is applied to the gates of the column selection transistors 54-1, 54-3, and 54-5 by the column selection switch 51b. Thereby, the pixel 11, the horizontal shift register 18b, and the readout circuit 19b are disconnected.

  Further, an L level signal is applied to each gate of the column selection transistors 53-2, 53-4, and 53-6 by the column selection switch 51a, and the column selection transistors 54-2, 54-4, and 54-. An H level signal is applied to each gate 6 by the column selection switch 51b. As a result, the pixel 11 connected to the signal lines 32-2, 32-4, and 32-6 is connected to the horizontal shift register 18b and the readout circuit 19b.

  If the same operation as described in the first embodiment is performed in the vertical shift register circuit 14, the vertical drive circuit 16, and the horizontal shift register circuits 18a and 18b in the connection state as described above, A row of the pixels 11 is selected, and light reception signals from the respective pixels in the row are read out by the readout circuits 19a and 19b. At this time, among the light reception signals read by the read circuit 19a by the horizontal shift register circuit 18a, that is, among the light reception signals from the pixels 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16, One of the light reception signals corresponding to the column of the pixels 11 connected to the signal lines 32-1, 32-3, or 32-5 is selected and output from the readout circuit 19. In addition, among the light reception signals read by the readout circuit 19b by the horizontal shift register circuit 18b, that is, among the light reception signals from the pixels 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16, the signal One of the light reception signals corresponding to the column of the pixels 11 connected to the line 32-2, 32-4, or 32-6 is selected and output from the readout circuit 19. Note that the selection of the two light reception signals by the horizontal shift register circuits 18a and 18b can be performed simultaneously. In addition, reading and outputting of the received light signals by the reading circuits 19a and 19b can be performed simultaneously.

  As described above, the read circuits 19a and 19b read the light reception signals output from the pixels 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16 for the columns of the pixels 11 different from each other. Then, light reception signals corresponding to different columns of the pixels 11 respectively selected by the horizontal shift register circuits 18a and 18b can be output.

  If the levels of the signals applied from the column selection switches 51a and 51b to the gates of the column selection transistors 53-1 to 53-6 and 54-1 to 54-6 are inverted, the operation opposite to the above is performed. Done. At this time, among the light reception signals read by the read circuit 19a by the horizontal shift register circuit 18a, that is, among the light reception signals from the pixels 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16, One of the received light signals corresponding to the column of the pixels 11 connected to the signal lines 32-2, 32-4, or 32-6 is selected and output from the readout circuit 19. In addition, among the light reception signals read by the readout circuit 19b by the horizontal shift register circuit 18b, that is, among the light reception signals from the pixels 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16, the signal One of the light reception signals corresponding to the column of the pixels 11 connected to the line 32-1, 32-3 or 32-5 is selected and output from the readout circuit 19. Such operation switching can be performed for each row of the pixels 11.

  In the solid-state imaging device according to the present embodiment, the block of the unit circuit 70 can be divided in the vertical shift register circuit 14 and the horizontal shift register circuits 18a and 18b in the same manner as in the first embodiment. That is, for example, as shown in FIG. 14, block division is performed corresponding to preset focus detection regions R1 to R6.

  In the present embodiment, the pixels 11 are arranged in a pair of focus detection regions R1 and R6 set side by side in the row direction of the pixels 11, for example, in an arrangement pattern as shown in FIG. The arrangement in the focus detection area R1 is the same as the arrangement in the focus detection area R3 shown in FIG. That is, the focus detection pixels 11a and the imaging pixels 11e are alternately arranged in the left column n1, and the imaging pixels 11e and the focus detection pixels 11b are alternately arranged in the right column n2. On the other hand, in the focus detection region R6, the arrangement pattern of the pixels 11 is configured to be reversed from the arrangement in the focus detection region R1. That is, the imaging pixels 11e and the focus detection pixels 11a are alternately arranged in the left column n3 in the reverse order to the column n1, and the focus detection pixels in the right column n4 in the reverse order to the column n2. 11b and imaging pixels 11e are alternately arranged.

  When signals are read out from the pixels 11 having the arrangement pattern as shown in FIG. 17, the horizontal shift register circuits 18a and 18b, the column selection switches 51a and 51b, and the column selection transistors corresponding to the columns include the focus detection region R1. Two signals corresponding to two columns of pixels 11 corresponding to each of R6 and whose arrangements are inverted are selected simultaneously.

  For example, when the row m1 is selected, the column selection switch 51a turns on the column selection transistor corresponding to the column n1 and turns off the column selection transistor corresponding to the column n2, and the column selection switch 51b The column selection transistor corresponding to the column n4 is turned on, and the column selection transistor corresponding to the column n3 is turned off. Then, simultaneously with the horizontal shift register circuit 18a selecting the light reception signal corresponding to the column n1, the horizontal shift register circuit 18b selects the light reception signal corresponding to the column n4. As a result, the light receiving signal from the focus detection pixel 11a located at the coordinates (m1, n1) is output by the readout circuit 19a, and the focus detection pixel 11b located at the coordinates (m1, n4) is output by the readout circuit 19b. The received light signal is output.

  On the other hand, when row m2 is selected, the signal levels from column selection switches 51a and 51b are inverted. That is, the column selection switch 51a turns on the column selection transistor corresponding to the column n2 and turns off the column selection transistor corresponding to the column n1, and the column selection switch 51b turns on the column selection transistor corresponding to the column n3. Is turned on and the column selection transistor corresponding to the column n4 is turned off. Then, simultaneously with the horizontal shift register circuit 18a selecting the light reception signal corresponding to the column n2, the horizontal shift register circuit 18b selects the light reception signal corresponding to the column n3. As a result, a light reception signal is output from the focus detection pixel 11b located at the coordinates (m2, n2) by the readout circuit 19a, and from the focus detection pixel 11a located at the coordinates (m2, n3) by the readout circuit 19b. The received light signal is output.

  By alternately switching the operation described above for each row of the pixels 11, signals from the focus detection pixels respectively corresponding to the focus detection regions R1 and R6 can be quickly read and output. Therefore, quick autofocus control can be performed in the camera.

  In the focus detection area R2, the pixels 11 are arranged in an arrangement pattern as shown in FIG. 18, for example. In the upper row m11, focus detection pixels 11c and imaging pixels 11e are alternately arranged in a region on the left side from the center, and imaging pixels 11e and focus detection pixels 11d are alternately arranged in a region on the right side from the center. Has been placed. On the contrary, in the lower row m12, the imaging pixels 11e and the focus detection pixels 11d are alternately arranged in the region on the left side from the center, and the focus detection pixels 11c in the region on the right side from the center. The imaging pixels 11e are alternately arranged. Thus, when the focus detection region R2 is divided into two regions at equal positions in the row direction, the pixels 11 are arranged so that the arrangement of the focus detection pixels and the imaging pixels in each region is inverted. The arrangement pattern is configured.

  When a signal is read from the pixels 11 having the arrangement pattern as shown in FIG. 18, the focus detection region R2 is divided into two regions at equal positions in the row direction of the pixels 11. The horizontal shift register circuits 18a and 18b, the column selection switches 51a and 51b, and the column selection transistor corresponding to each column are two pixels 11 of which the arrangements are inverted with respect to each of the divided areas. Two signals corresponding to the column are selected simultaneously.

  For example, when the row m11 is selected, the column selection switch 51a first turns on the column selection transistor corresponding to the column n11 and turns off the column selection transistor corresponding to the column n12 in the left region. The column selection switch 51b turns on the column selection transistor corresponding to the column n22 and turns off the column selection transistor corresponding to the column n21 in the right region. Then, simultaneously with the horizontal shift register circuit 18a selecting the light reception signal corresponding to the column n11, the horizontal shift register circuit 18b selects the light reception signal corresponding to the column n22. As a result, a light reception signal is output from the focus detection pixel 11c located at the coordinates (m11, n11) by the readout circuit 19a, and from the focus detection pixel 11d located at the coordinates (m11, n22) by the readout circuit 19b. The received light signal is output.

  By performing the same operation for each column of the pixels 11, in the row m11, the focus detection pixels 11c arranged in every other column in the left region obtained by dividing the focus detection region R2 into two left and right. The light reception signal from is read out by the readout circuit 19a and output. For the right region, the light reception signals from the focus detection pixels 11d arranged in every other column are read out and output by the readout circuit 19b.

  On the other hand, when the row m12 is selected, the signal levels from the column selection switches 51a and 51b are inverted. That is, first, the column selection switch 51a turns on the column selection transistor corresponding to the column n12 and turns off the column selection transistor corresponding to the column n11 in the left region, and the column selection switch 51b turns on the right region. Then, the column selection transistor corresponding to the column n21 is turned on, and the column selection transistor corresponding to the column n22 is turned off. The horizontal shift register circuit 18a selects the light reception signal corresponding to the column n12, and at the same time, the horizontal shift register circuit 18b selects the light reception signal corresponding to the column n21. As a result, a light reception signal is output from the focus detection pixel 11d located at the coordinates (m12, n12) by the readout circuit 19a, and from the focus detection pixel 11c located at the coordinates (m12, n21) by the readout circuit 19b. The received light signal is output.

  By performing the same operation for each column of the pixels 11 in the row m12, the focus detection pixels arranged in every other column in the left region obtained by dividing the focus detection region R2 into two on the left and right sides. The light reception signal from 11d is read and output by the read circuit 19a. For the right region, the light reception signals from the focus detection pixels 11c arranged in every other column are read and output by the read circuit 19b.

  By performing the operation described above, signals from each focus detection pixel corresponding to the focus detection region R2 can be quickly read and output. Therefore, quick autofocus control can be performed in the camera.

  Note that signals from each pixel can be read out using the same method as described above for the focus detection regions R1 and R3 to R6 other than the focus detection region R2. At this time, the same applies to not only the focus detection regions R4 and R5 having a horizontally long shape, but also the focus detection regions R1, R3, and R5 having a vertically long shape as in the focus detection region R2. Further, the same applies to the focus detection regions having substantially the same length and width.

  Alternatively, instead of configuring the arrangement pattern of the pixels 11 so that the arrangement of the focus detection pixels and the imaging pixels is inverted at equal positions in the row direction, the operation of the column selection transistor may be inverted. Good. Even in this case, signals from each pixel can be read out in the same manner as described above.

According to the present embodiment, the following operational effects are obtained.
(1) The signals output from the pixels 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16 are read out from different columns by the readout circuits 19a and 19b, respectively. The horizontal shift register circuits 18a and 18b, the column selection switches 51a and 51b, and the column selection transistors 53-1 to 53-6 and 54-1 to 54-6 are connected to the pixel 11 with respect to the readout circuits 19a and 19b. Since signals corresponding to different columns are selected and output, the signals can be read quickly.

(2) The readout circuit 19a outputs a signal output from each pixel 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16 to one focus detection region R1 of the pair of focus detection regions R1 and R6. The columns n1 and n2 including the pixels corresponding to are read out. Further, the readout circuit 19b outputs a signal output from each pixel 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16 for the columns n3 and n4 including the pixel corresponding to the other focus detection region R6. read out. The horizontal shift register circuits 18a and 18b, the column selection switches 51a and 51b, and the column selection transistors 53-1 to 53-6 and 54-1 to 54-6 are combined into a pair of focus detection regions R1 and R6. Two signals corresponding to two columns of the corresponding pixels 11 are simultaneously selected, and the selected signals are output from the readout circuit 19a and the readout circuit 19b, respectively. Since it did in this way, the signal from each pixel corresponding to a pair of focus detection area | region can be read in parallel. Therefore, quick control is possible when performing autofocus control using a pair of focus detection areas in the camera.

(3) In the photoelectric conversion unit 10, focus detection pixels and imaging pixels are arranged in a predetermined arrangement pattern corresponding to the preset focus detection regions R <b> 1 to R <b> 6. This arrangement pattern is configured such that the arrangement of focus detection pixels and imaging pixels in each of the pair of focus detection regions R1 and R6 is inverted. Two signals corresponding to two columns of the pixels 11 in which the array is inverted are supplied to the horizontal shift register circuits 18a and 18b, the column selection switches 51a and 51b, and the column selection transistors 53-1 to 53-6 and 54-. From 1 to 54-6, it was decided to select simultaneously. Since it did in this way, only the signal from the focus detection pixel can be read out for each of the pair of focus detection areas.

(4) When reading a signal from the pixel 11 corresponding to the focus detection region R2, the focus detection region R2 is divided into two regions at equal positions in the row direction of the pixel 11. At this time, the readout circuit 19a outputs a signal output from each pixel 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16 to the column n11 including a pixel corresponding to one of the two regions. , N12, etc. The readout circuit 19b outputs a signal output from each pixel 11 in the row selected by the vertical shift register circuit 14 and the vertical drive circuit 16 to a column n21 including a pixel corresponding to the other of the two regions. Read about n22 and the like. The horizontal shift register circuits 18a and 18b, the column selection switches 51a and 51b, and the column selection transistors 53-1 to 53-6 and 54-1 to 54-6 correspond to the above two regions, respectively. Two signals corresponding to two columns of the pixels 11 are simultaneously selected, and the selected signals are output from the readout circuit 19a and the readout circuit 19b, respectively. Since it did in this way, the signal from each pixel corresponding to one focus detection area | region can be read quickly. Therefore, quick autofocus control can be performed in the camera.

(5) In the photoelectric conversion unit 10, focus detection pixels and imaging pixels are arranged in a predetermined arrangement pattern corresponding to the focus detection regions R1 to R6 set in advance. This arrangement pattern is configured such that the arrangement of the focus detection pixels and the imaging pixels in each of the areas obtained by dividing the focus detection area R2 into two is inverted. Two signals corresponding to two columns of the pixels 11 in which the array is inverted are supplied to the horizontal shift register circuits 18a and 18b, the column selection switches 51a and 51b, and the column selection transistors 53-1 to 53-6 and 54-. From 1 to 54-6, it was decided to select simultaneously. Since it did in this way, only the signal from the focus detection pixel can be read out for each of the divided areas.

  As mentioned above, although each embodiment of this invention and its modification were demonstrated, this invention is not limited to these. For example, in each of the above-described embodiments, the unit circuit 70 is a two-phase drive circuit. However, in the present invention, for example, a single-phase drive circuit may be employed as the unit circuit 70. In the above embodiments, the operations of the vertical scanning circuit and the horizontal scanning circuit may be interchanged.

1 is a schematic configuration diagram illustrating a solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram which shows the pixel in FIG. It is a circuit diagram which shows the vertical drive circuit in FIG. FIG. 2 is a circuit diagram showing a readout circuit in FIG. 1. FIG. 2 is a circuit diagram showing a vertical shift register circuit in FIG. 1. FIG. 6 is a circuit diagram illustrating an example of a unit circuit in FIG. 5. FIG. 7 is a circuit diagram showing a more specific configuration of the unit circuit shown in FIG. 6. FIG. 6 is a circuit diagram showing another example of the unit circuit in FIG. 5. FIG. 6 is a circuit diagram showing still another example of the unit circuit in FIG. 5. FIG. 6 is a circuit diagram showing still another example of the unit circuit in FIG. 5. 6 is a timing chart showing signals input to and output from the vertical shift register circuit shown in FIG. 5 during normal all-pixel reading. 6 is a timing chart showing signals input to and output from the vertical shift register circuit shown in FIG. 5 during partial reading. FIG. 6 is another timing chart showing signals inputted to and outputted from the vertical shift register circuit shown in FIG. 5 during partial reading. It is a figure which shows an example of the relationship between each area | region of a photoelectric conversion part, and a block division | segmentation method. It is a figure which shows an example of the arrangement pattern of the pixel in a focus detection area. It is a schematic block diagram which shows the solid-state imaging device by the 2nd Embodiment of this invention. It is a figure which shows an example of the arrangement pattern of the pixel in a pair of focus detection area. It is a figure which shows the other example of the arrangement pattern of the pixel in a focus detection area.

Explanation of symbols

2 Image sensor 3 Timing generator 4 Control circuit 10 Photoelectric conversion unit 11 Pixel 14 Vertical shift register circuit 18 Horizontal shift register circuit 70 Unit circuit BV1 to BVj Block CONV1 to CONVj, CONH1 to CONHk Control signal S1 to Sj Individual switching setting unit R1 R6 focus detection area

Claims (6)

A photoelectric conversion unit having a plurality of pixels arranged two-dimensionally;
A vertical scanning circuit for selecting a row of pixels;
A readout circuit for reading out a signal output from each pixel in the row selected by the vertical scanning circuit;
A solid-state imaging device comprising: a horizontal scanning circuit that selects one of the signals read out by the readout circuit in association with the column of pixels and outputs the selected signal from the readout circuit. There,
Among the pixels, pixels corresponding to a preset focus detection region include focus detection pixels that output signals for use in focus detection,
The vertical scanning circuit can preferentially select a row of pixels corresponding to the focus detection area,
The solid-state imaging device, wherein the horizontal scanning circuit can preferentially select a signal corresponding to a column of pixels corresponding to the focus detection area. The solid-state imaging device according to claim 1,
The readout circuit includes a first readout circuit and a second readout circuit that respectively read out signals output from the pixels in the row selected by the vertical scanning circuit for the different pixel columns,
The horizontal scanning circuit causes the first readout circuit and the second readout circuit to select and output signals corresponding to different columns of the pixels, respectively. The solid-state imaging device according to claim 2,
A pair of focus detection areas are set side by side in the row direction of the pixels,
The first readout circuit reads out a signal output from each pixel in a row selected by the vertical scanning circuit for the column of pixels including a pixel corresponding to one of the pair of focus detection regions,
The second readout circuit reads out a signal output from each pixel in a row selected by the vertical scanning circuit for the column of pixels including a pixel corresponding to the other of the pair of focus detection regions,
The horizontal scanning circuit simultaneously selects two signals corresponding to two columns of the pixels respectively corresponding to the pair of focus detection regions, and selects the selected signals from the first readout circuit and the second readout circuit. A solid-state imaging device characterized in that each is output. The solid-state imaging device according to claim 3,
In the photoelectric conversion unit, the focus detection pixels and imaging pixels that output signals for use in imaging are arranged in a predetermined arrangement pattern corresponding to the focus detection region,
The array pattern is configured so that the array of the focus detection pixels and the imaging pixels in each of the pair of focus detection regions is inverted,
The horizontal scanning circuit simultaneously selects two signals corresponding to two columns of the pixels in which the arrangement is inverted. In the solid-state imaging device according to any one of claims 2 to 4,
Dividing the focus detection area into two areas at equal positions in the row direction of the pixels;
The first readout circuit reads out a signal output from each pixel in a row selected by the vertical scanning circuit for a column of the pixels including a pixel corresponding to one of the two regions,
The second readout circuit reads out a signal output from each pixel in a row selected by the vertical scanning circuit for a column of the pixels including a pixel corresponding to the other of the two regions,
The horizontal scanning circuit simultaneously selects two signals corresponding to two columns of the pixels respectively corresponding to the two regions, and outputs the selected signals from the first readout circuit and the second readout circuit, respectively. A solid-state imaging device. The solid-state imaging device according to claim 5,
In the photoelectric conversion unit, the focus detection pixels and imaging pixels that output signals for use in imaging are arranged in a predetermined arrangement pattern corresponding to the focus detection region,
The arrangement pattern is configured so that the arrangement of the focus detection pixels and the imaging pixels in each of the two regions is inverted,
The horizontal scanning circuit simultaneously selects two signals corresponding to two columns of the pixels in which the arrangement is inverted.

Images