JP2009088187A - Trench gate type transistor and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of a gate leak current and to reduce a gate capacitance in a trench gate type transistor. <P>SOLUTION: A trench 14 is formed on an N-type semiconductor layer 12. In the trench 14, thin silicon oxide films 15B are formed in a region to be a transistor activation region on the N-type semiconductor layer 12. On the region not to be the activation region, a silicon oxide film 15A thicker than the silicon oxide film 15B is formed. Furthermore, an extracting section 16S extending outward from the inside of the trench 14 forms a gate electrode 16 which is brought into contact with the silicon oxide film 15A. Thus, in the extracting section 16S of the gate electrode 16, since a long distance is secured between the gate electrode 16 and the corner section 12C of the N-type semiconductor layer 12, the occurrence of the gate leak current is prevented and the gate capacitance can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a trench gate type transistor and a manufacturing method thereof.

  The DMOS transistor is a double-diffused MOS field effect transistor, and is used as a power semiconductor element such as a power supply circuit and a driver circuit. A trench gate type transistor is known as a kind of DMOS transistor.

  In this trench gate type transistor, as shown in FIG. 14, a gate insulating film 115 is formed in a trench 114 formed in a semiconductor layer 112, and a gate electrode 116 is formed to cover the gate insulating film 115 in the trench 114. It is. In addition, a body layer and a source layer (not shown) are formed on the surface of the semiconductor layer 112 on the sidewall of the trench 114 by double diffusion in the vertical direction.

The trench gate type transistor is described in Patent Documents 1 and 2.
JP 2005-322949 A JP 2003-188379 A

  However, as shown in FIG. 14, a leak current (hereinafter referred to as a gate leak current) between the gate electrode 116 and the semiconductor layer 112 in a portion (hereinafter referred to as a lead portion) 116 </ b> S that leads the gate electrode 116 out of the trench 114. ) Occurred. The reason for this is that, according to the study by the present inventor, first, the thickness of the gate insulating film 115 is thin, and secondly, in the lead portion 116S, the corner portion 112C of the semiconductor layer 112 sandwiches the thin gate insulating film 115. This is because electric field concentration occurs in this portion since the gate electrode 116 is opposed to the gate electrode 116.

  The trench gate type transistor of the present invention includes a semiconductor layer, a gate insulating film formed in the trench formed in the semiconductor layer and extending on the semiconductor layer outside the trench, and on the gate insulating film. A gate layer formed near the surface of the semiconductor layer and in contact with the gate insulating film on a sidewall of the trench, the gate insulating film being a portion in contact with the body layer A first gate insulating film having a first film thickness, and a second gate film having a second film thickness greater than the first film thickness at a portion extending from the inside of the trench to the semiconductor layer outside the trench. And a gate insulating film.

  According to this configuration, the second gate insulating film (thick gate insulating film) having a second film thickness larger than the first film thickness in a portion extending from the inside of the trench to the semiconductor layer outside the trench. Since the distance between the gate electrode and the corner of the semiconductor layer is ensured long in the lead-out portion of the gate electrode, generation of gate leakage current is prevented and gate capacitance (gate electrode, insulating film, (Consisting of a semiconductor layer) can be reduced.

  Further, by forming a first gate insulating film (thin gate insulating film) having a first film thickness in a portion (activation region) in contact with the body layer, excellent transistor characteristics (low threshold, low on-resistance) ) Can be secured.

  The method of manufacturing a trench gate type transistor of the present invention includes a step of forming a trench in a semiconductor layer, and thermally oxidizing the semiconductor layer in which the trench is formed, thereby oxidizing the surface of the semiconductor layer including the inside of the trench. A step of forming a film; a step of selectively removing the oxide film in the activation region in the trench; and a step of selectively heating the semiconductor layer in which the trench is formed after the oxide film is selectively removed. By oxidizing, a first gate oxide film having a first film thickness is formed on the activated region in the trench, and thicker than the first film thickness in the non-activated region of the transistor. Forming a second gate oxide film having a second thickness; and forming the second gate oxide film in the trench through the first and second gate oxide films, and passing through the second gate oxide film. Tore To forming a gate electrode extending to the outside of the switch, forming a body layer in contact with the first gate oxide film on the sidewalls of the trench, characterized in that it comprises a.

  According to such a configuration, the first gate oxide film (thin gate oxide film) is formed in the activated region, and the second gate oxide film (thick gate oxide film) is formed in the non-activated region. And the same effect as described above can be obtained.

  According to the trench gate type transistor and the manufacturing method thereof of the present invention, it is possible to prevent the generation of gate leakage current and reduce the gate capacitance. In addition, excellent transistor characteristics (low threshold value, low on-resistance) can be ensured.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view illustrating a trench gate type transistor and a manufacturing method thereof according to an embodiment of the present invention. 2A to 11A are cross-sectional views taken along line AA in FIG. 1, and FIGS. 2B to 11B are taken along line BB in FIG. FIG. In the following description, the trench gate type transistor is simply referred to as a transistor.

  First, the schematic planar configuration of the transistor according to the present embodiment will be described with reference to FIG. Here, only main components will be described. In this transistor, an N + type semiconductor layer 11 and an N− type semiconductor layer 12 are formed on a P type semiconductor substrate 10, and a region where a body layer 19 is formed on the surface side of the N− type semiconductor layer 12. A plurality of trenches 14 having a short side and a long side are formed therethrough. A gate electrode 16 is formed in each trench 14 via a gate insulating film (not shown). Each gate electrode 16 is connected to one end of each trench 14 and extends outside the trench 14. The gate electrode 16 extending outside the trench 14 is connected to a wiring (not shown) through a contact hole H1 provided in an interlayer insulating film (not shown).

  It should be noted that another high voltage MOS transistor (not shown) may be formed on the same N − type semiconductor layer 12 adjacent to this transistor.

  The trench gate type transistor and the manufacturing method thereof according to the present embodiment will be explained below with reference to the drawings.

  As shown in FIG. 2, after doping the surface of a P-type semiconductor substrate 10 with an N-type impurity, the semiconductor layer is epitaxially grown to form an N + type semiconductor layer 11 and an N− type semiconductor layer 12. In the following description, it is assumed that the semiconductor substrate 10 is a silicon single crystal substrate and the N + type semiconductor layer 11 and the N− type semiconductor layer 12 are silicon single crystal semiconductor layers, but the present invention is not limited to this. Next, a silicon oxide film 13 is formed on the N − type semiconductor layer 12 by a CVD method or a thermal oxidation process. Further, a resist layer R1 having an opening M1 is formed on the silicon oxide film 13. The opening M1 has a plurality of rectangles having short sides and long sides.

Next, as shown in FIG. 3, the silicon oxide film 13 is etched using the resist layer R <b> 1 as a mask to form an opening 13 </ b> M in the silicon oxide film 13. After removing the resist layer R1, the N− type semiconductor layer 12 is etched using the silicon oxide film 13 as a hard mask, and a plurality of trenches 14 having short sides and long sides corresponding to the openings 13M are formed. Form. This etching is, for example, dry etching using an etching gas containing SF ₆ . Therefore, the corners 14C and 14D at the bottom of the trench 14 are rounded. Preferably, the depth of the trench 14 is about 1 μm, its long side is about 50 μm, and its short side is about 0.5 μm. The number of trenches 14 is preferably about 10. Thereafter, the silicon oxide film 13 is removed.

  Next, as shown in FIG. 4, a thermal oxidation process is performed on the N − type semiconductor layer 12 in the trench 14 to form a silicon oxide film 15A. Preferably, the thickness of the silicon oxide film 15A at this time is about 100 nm. The silicon oxide film 15 </ b> A is formed to be rounded at the portion reflecting the roundness of the corners 14 </ b> C and 14 </ b> D at the bottom of the trench 14.

  When another high voltage MOS transistor is formed on the same N− type semiconductor layer 12, the silicon oxide film 15A is formed simultaneously with the gate oxide film. The thickness of the silicon oxide film 15A varies depending on the breakdown voltage characteristics of the MOS transistor.

  Next, as shown in FIG. 5, a resist layer R2 having an opening M2 is formed on the silicon oxide film 15A. The opening M <b> 2 opens on a region of the N− type semiconductor layer 12 that becomes an activation region of the transistor. Here, the activation region of the transistor is a region where the body layer 19 is formed. Hereinafter, the activation region of the transistor is simply referred to as an activation region. In other words, the resist layer R <b> 2 extends from the N− type semiconductor layer 12 in a region that is not an activation region (deactivation region), that is, from the corner 14 </ b> C in the short side direction of the trench 14 to the outside of the trench 14. Exist.

  Next, as shown in FIG. 6, the silicon oxide film 15A is etched using the resist layer R2 as a mask. As a result, an opening 15M that exposes the region of the N − type semiconductor layer 12 that becomes the activation region is formed. Thereafter, the resist layer R2 is removed.

  Next, as shown in FIG. 7, by performing a thermal oxidation process on the N− type semiconductor layer 12 in the trench 14 and exposed at the opening 15 </ b> M of the silicon oxide film 15 </ b> A, A silicon oxide film 15B is formed.

  Thus, a thin silicon oxide film 15B (an example of the first gate insulating film of the present invention) is formed in a region that becomes an activation region of the N − type semiconductor layer 12. Preferably, the thickness of the silicon oxide film 15B is about 10 nm.

  On the other hand, a silicon oxide film 15A (an example of the second gate insulating film of the present invention) thicker than the silicon oxide film 15B is formed in a region that does not become an activated region (non-activated region). Preferably, the thickness of the silicon oxide film 15A is about 100 nm.

  Next, as shown in FIG. 8, a polysilicon layer 16P that covers the silicon oxide film 15A and the silicon oxide film 15B is formed, and impurities are doped therein. This impurity is preferably an N-type impurity.

  Thereafter, as shown in FIG. 9, a resist layer R3 is formed in a region on the polysilicon layer 16P and partially overlapping with the thick silicon oxide film 15A. Next, the polysilicon layer 16P is etched using the resist layer R3 as a mask, thereby forming the gate electrode 16 extending from each trench 14 onto the silicon oxide film 15A. The lead portion 16S of the gate electrode 16 extending from the inside of the trench 14 is in contact with the thick silicon oxide film 15A. The gate electrodes 16 are connected to each other on the silicon oxide film 15 </ b> A outside the trench 14. This etching is, for example, plasma etching. Thereafter, the resist layer R3 is removed.

  Next, as shown in FIG. 10, in the N − type semiconductor layer 12, a P type body layer 19 is formed by ion-implanting a P type impurity in the vertical direction around each trench 14. The body layer 19 is in contact with the thin silicon oxide film 15B. Further, the source layer 21 is formed by ion-implanting N-type impurities into the surface of the body layer 19 along the long side direction of each trench 14. Note that heat treatment is preferably performed to adjust the activation of the body layer 19 and the source layer 21 and the impurity distribution.

  Next, as shown in FIG. 11, an interlayer insulating film 24 that covers the silicon oxide films 15A and 15B and the gate electrode 16 is formed. On the interlayer insulating film 24, a wiring layer 25 connected to the gate electrode 16 through a contact hole H1 provided in the interlayer insulating film 24 is formed. On the interlayer insulating film 24, a source electrode 23 connected to the source layer 21 through the contact hole H2 provided in the silicon oxide film 15B and the interlayer insulating film 24 is formed.

  In the transistor thus completed, when a potential higher than the threshold is applied from the wiring layer 25 to the gate electrode 16, the surface of the body layer 19 on the side wall of the trench 17 is inverted to N-type to form a channel. As a result, a current can flow between the source electrode 23 and the N− type semiconductor layer 12 and the N + type semiconductor layer 11 that become the drain D.

  The silicon oxide film 15A in contact with the lead portion 16S of the gate electrode 16 functions as a thick gate insulating film, so that the gate electrode 16 and the corner portion 12C of the N− type semiconductor layer 12 in the lead portion 16S of the gate electrode 16 Therefore, the generation of the gate leakage current can be prevented and the gate capacitance (consisting of the gate electrode 16, the silicon oxide film 15A, and the N − type semiconductor layer 12) can be reduced.

  In the transistor activation region (region where the body layer 19 is formed), the thin silicon oxide film 15B is formed as a gate insulating film, so that excellent transistor characteristics (low threshold, low on-resistance) are obtained. be able to.

  As a modification of the present embodiment, a drain lead portion 26 and a drain electrode 27 may be formed as shown in FIG. In this case, before the interlayer insulating film 24 is formed, the opening 12H is formed in the N − type semiconductor layer 12, the insulating film 28 is formed in the opening 12H, and the drain drawing portion 26 is embedded. Thereafter, an interlayer insulating film 24 is formed, a through hole H3 penetrating the interlayer insulating film 24 is formed, and a drain electrode 27 connected to the drain lead portion 26 is formed in the through hole H3.

  As another modification of the present embodiment, the gate electrodes 16 are not connected to each other at the ends of the trenches 14 as shown in FIG. 1, but are separated for each trench 14 as shown in the plan view of FIG. And may be formed so as to be isolated. Other configurations are the same as those in FIG. Thereby, when the etching with respect to the polysilicon layer 16P is plasma etching, the area of the gate electrode 16 made of the polysilicon layer 16P is reduced, so that plasma damage to the gate electrode 16 can be suppressed as much as possible. Therefore, the reliability of the transistor can be improved.

  Needless to say, the present invention is not limited to the above-described embodiment, and modifications can be made without departing from the scope of the present invention. For example, although an N-channel transistor has been described, the present invention can also be applied to a P-channel transistor by changing the conductivity type of the source layer 21 and the body layer 19 to the opposite conductivity type. .

  The present invention can also be applied to a device having a buried gate electrode such as a trench gate type IGBT.

It is a top view explaining the trench gate type transistor by the embodiment of the present invention, and its manufacturing method. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is sectional drawing explaining the trench gate type transistor and its manufacturing method by embodiment of this invention. It is a top view explaining the trench gate type transistor by the embodiment of the present invention, and its manufacturing method. It is sectional drawing explaining the trench gate type transistor of a prior art example, and its manufacturing method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 N + type semiconductor layer 12 N- type semiconductor layer 12C, 14C, 14D, 112C Corner | angular part 13, 15A, 15B Silicon oxide film 14 Trench
16 Gate electrode 16P Polysilicon layer 16S, 116S Lead part 19 Body layer 21 Source layer 23 Source electrode 24 Interlayer insulating film 25 Wiring layer 26 Drain lead part 27 Drain electrode 28 Insulating film 115 Gate insulating film H1, H2 Contact hole H3 Through hole R1-R3 resist layer M1-M3, 13M, 15M opening

Claims (5)

A semiconductor layer; a gate insulating film formed in the trench formed in the semiconductor layer and extending on the semiconductor layer outside the trench; a gate electrode formed on the gate insulating film; and the semiconductor A body layer formed near the surface of the layer and in contact with the gate insulating film on the side wall of the trench, and
The gate insulating film includes a first gate insulating film having a first thickness at a portion in contact with the body layer, and a portion extending from the inside of the trench to the semiconductor layer outside the trench. And a second gate insulating film having a second film thickness greater than the thickness. 2. The trench gate transistor according to claim 1, wherein the second gate insulating film is rounded at a portion extending from the inside of the trench to the semiconductor layer outside the trench. 2. The trench gate type transistor according to claim 1, wherein the second gate insulating film is formed simultaneously with the gate insulating film of the high voltage MOS transistor formed on the surface of the semiconductor layer. Forming a trench in the semiconductor layer;
Forming a oxide film on the surface of the semiconductor layer including the inside of the trench by thermally oxidizing the semiconductor layer in which the trench is formed;
Selectively removing the oxide film in the activated region in the trench;
After the oxide film is selectively removed, a first gate having a first thickness is formed on the activated region in the trench by thermally oxidizing the semiconductor layer in which the trench is formed. Forming an oxide film and forming a second gate oxide film having a second film thickness larger than the first film thickness in the non-activated region;
Forming a gate electrode formed in the trench through the first and second gate oxide films and extending out of the trench through the second gate oxide film;
Forming a body layer on the sidewall of the trench in contact with the first gate oxide film, and manufacturing the trench gate type transistor. 5. The trench according to claim 4, wherein in the step of forming the oxide film, the oxide film is thermally oxidized so as to round at a portion extending from the inside of the trench to the semiconductor layer outside the trench. Manufacturing method of gate type transistor.

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