JP2009088177A - SI MOUNTING BOARD COMPOSED OF Si AND SEMICONDUCTOR MODULE USING THE SAME - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a Si board has high purity, namely, adopts so-called six-nine or eleven-nine purity while much Si debris is produced in the processes and it is not effectively recycled. <P>SOLUTION: Unlike a semiconductor device, the board adopting a Si interposer does not require so high purity. The Si board is desirable because it should be correspond to α of a Si chip. Herein, it adopts the interposer 10 for which Si debris is effectively recycled. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a mounting substrate with low Si purity.

    In recent years, with the widespread use of information terminals such as mobile phones and digital cameras, semiconductor devices mounted thereon are required to be thinned, miniaturized, and reduced in weight as well as integrated. This is generally called CSP (Chip Size Package) or SIP (System In Package), and these packages are two-dimensionally or three-dimensionally arranged with semiconductor chips having a thickness of 100 μm or less.

  That is, a thick wafer is formed as an IC or LSI using a normal semiconductor process, and then the semiconductor wafer is thinned to a desired thickness and diced to form a semiconductor chip.

  As shown in FIG. 2, the semiconductor wafer is also processed into a cylindrical ingot 2 by cutting the Si ingot 1 pulled up as a single crystal of Si. 3 is processed. For processing as a single wafer, for example, processing is performed with a saw wing 4 such as a saw. Naturally, in these processes, as described above, a large amount of Si scrap is generated because of polishing, grinding or sawing.

  For example, since the top and tail exist as large lumps, they are melted again and reused as Si ingots. Further, as shown in Japanese Patent No. 3316484, fine Si scraps can be collected as Si scraps, and are mixed with, for example, steel, bricks, etc., thereby improving the characteristics.

On the other hand, since the semiconductor chip used for CSP and SIP uses a thin semiconductor chip as mentioned before, a thin resin substrate has been adopted as an interposer. In order to approximate the thermal expansion coefficient α of this resin substrate with a mounting substrate such as a printed circuit board, a resin material and a filler to be mixed were selected, and measures were taken so that stress was not applied to the semiconductor chip as much as possible. .
Japanese Patent No. 3316484

  The above-mentioned Si scrap is manufactured using a large amount of electric power. However, in order to remelt the Si scrap and reuse it as a semiconductor substrate, the purity of Eleven Nine (99.99 ··%) is achieved. It must be done. In addition, to be used as a substrate for a solar cell, the purity must be 6% (99.99%).

  In order to achieve these purities, impurities such as B, P or As must be realized by an inexpensive method, and there has been a problem that the method has not yet been established.

  Further, when the above-described purity Si substrate is employed as a mounting substrate for a Si semiconductor chip, there has been a problem that the substrate is broken due to stress during mounting.

The present invention has been made in view of the aforementioned problems,
First, the problem is solved by making the Si purity of the mounting substrate 99% or less.

  Second, the mounting substrate made of Si contains Si scraps generated by polishing, grinding, or sawing, and P or N type impurities, impurities made of electrode material, or polishing, grinding, or sawing processed members. The problem is solved by including an impurity composed of a constituent material.

  Thirdly, the mounting substrate made of Si includes at least one of B, P, As, Al, Cu or Fe to solve the problem.

  Fourthly, the problem is solved by making the Si purity more rigid than the Si substrate exceeding 99%.

  Fifth, the problem is solved by forming the mounting substrate made of Si from polycrystal.

  Sixth, the problem is solved by increasing the roughness of the back side of the Si substrate rather than the surface of the Si substrate.

  Seventh, the surface of Si is provided with a plurality of surface electrodes through an insulating layer, and the back surface of Si is provided with a back surface electrode of a single-layer wiring.

  Eighth, the mounting substrate made of Si is solved by being made of a sintered body containing Si scraps generated by polishing, grinding or sawing.

  Ninth, the problem can be solved by setting the average particle size of Si in the sintered body to 1 μm or less.

  Tenth, the problem is solved by including a metal oxide as a sintering accelerator in the grain boundary of the sintered body.

  Eleventh, this is solved by adopting a complex oxide of manganese oxide and titanium oxide as the metal oxide.

  Twelfth, the through via provided from the front side to the back side of the mounting substrate made of Si is solved by being formed by punching or die processing on the green sheet before firing.

  Thirteenth, the problem is solved by mounting a semiconductor chip made of Si on a mounting board made of Si.

  14thly, it solves by mounting the mounting substrate which consists of Si provided with the semiconductor chip which consists of Si on the mounting substrate which consists of resin.

  Unlike a semiconductor chip such as an LSI made of Si, a mounting substrate made of Si does not require Si purity. Further, since the hardness is increased to some extent by mixing impurities, the flatness can be maintained as compared with the mounting substrate made of resin. Moreover, since the thermal expansion coefficients α that cause stress substantially coincide, even a thin semiconductor chip can be mounted with high reliability.

In addition, Si scrap generated from polishing / grinding of ingots or polishing / grinding of wafer back-grinding, dicing, etc. has a high purity of 93% to 97%,
Since it only needs to be melted into an ingot and sliced, the process can be simplified, the power can be reduced, the cost can be reduced, and a highly reliable mounting board can be realized.

  Further, the mounting substrate is made of single crystal or polycrystal. In particular, if polycrystalline, there is no cleaving property and cracking of the mounting substrate can be suppressed.

  Finally, if the sintered body is made of Si scrap, not only the above-described cleavage property is suppressed, but also the production method can be simplified. That is, since it can be easily made as a green sheet, punching or die processing can be performed, so that the process can be simplified and the power can be reduced, thereby reducing the cost.

  Specifically, the silicon powder can be refined for firing at a low temperature (up to 1000 degrees). For example, the finished product can have an average particle size of Si after sintering of 1 μm or less, and can suppress chipping during processing and improve strength.

  Furthermore, since a composite oxide of manganese oxide and titanium oxide is blended as a sintering accelerator, the resulting product contains Mn and Ti oxides as impurities in Si, and oxides exist at the grain boundaries. Thus, it is possible to improve the insulation of the Si mounting substrate.

  First of all, definitions are provided to simplify and distinguish sentences. That is, the mounting substrate made of Si, which is the point of the present invention, is called an interposer in the present invention. A semiconductor chip made of Si mounted on the interposer includes a discrete type, an IC, an LSI, a system LSI, and the like, and is simply referred to as a chip.

  Further, the interposer on which the chip is mounted is mounted on a mounting board set in an electronic device, for example, a printed board, a ceramic board, a metal board, or the like, and these are collectively referred to as a mounting board.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 4.

  FIG. 1A shows a cross-sectional view of the interposer 10. As a manufacturing method, as shown in FIG. 1B, the wafer 11 is manufactured and finally separated along a dicing line.

  Generally, this wafer is a single crystal having a purity as high as eleven nines, and has a cleavage property. As a matter of course, an IC and an LSI are fabricated by a normal semiconductor process on the thick wafer 11, and this is back-ground, for example, the thickness is reduced to 100 μm to 50 μm, and then dicing is performed. Naturally, various forces are applied depending on the thinness of the chip and the stress at the time of mounting, and chipping occurs.

  For example, in FIGS. 5 and 6, the chip 13 and the laminated chip 14 correspond to this. That is, the chip 13 has bumps 15 such as solder, Au or Cu formed on the surface, and is mounted on the interposer 16. If the interposer 16 is made of resin, the chip 13 may crack due to the difference between the thermal expansion coefficient α1 of the resin and the thermal expansion coefficient α2 of the chip. The laminated chip 14 has a through electrode 17 formed from the front surface to the back surface of the chip. In the laminated chip 14, bumps 18 electrically connected to the through electrodes 17 are formed on the back surface of the chip 14. The multilayer chip 14 is employed in, for example, a memory, and the number of multilayer chips increases with the memory capacity. Again, if the interposer 16 is made of a resin, the chip 13 may crack due to the difference between the thermal expansion coefficient α1 of the resin and the thermal expansion coefficient α2 of the chip.

  For example, α1 in the resin xy direction is 11-12 × 10 −6 / ° C., 25-30 × 10 −6 / ° C. in the z direction, and α2 of Si is 4.0 × 10 −6 / ° C. It is very different.

  Therefore, by using the Si interposer 16 instead of the resinous interposer, the α of the chips 13 and 14 and the interposer 16 can be matched, and chipping, cracking, and the like can be prevented.

  However, the interposer 16 is naturally made of Si like the chips 13 and 14. Moreover, the interposer 16 is mounted on a mounting board 19 such as a printed board mounted on the set. The interposer 16 and the mounting substrate 19 are substantially different in α between Si and resin, and this time, corner chipping on the side of the interposer 16 (a phenomenon substantially similar to chipping), cracks, and the like occur.

  The present invention prevents this chipping and cracking.

In other words, since it is hardly required to make a semiconductor element which is an active element, the purity of eleven nine and six nine is not required for the Si substrate itself.
In short, the purity of the active element and the passive element composed of the diffusion region is required to control the characteristic and to require stability of the characteristic.

  On the other hand, the present invention has focused on the fact that Si of low purity is employed and impurities are introduced, whereby the hardness of the Si substrate is increased and the cleavage property is decreased at the same time. For example, the Si purity is satisfied even at 99% or less.

  As described in the conventional example, it is possible to secure, for example, Si powder with low purity. For example, when drainage containing Si waste generated by back grinding and dicing is stored in one tank, the components are as follows.

  There may be 13 types of impurities other than Si: Si: 94.8%, P: 63 ppm, B: 7 ppm, Al: 13 ppm, Cu: 25 ppm, and so on. This Si may be remelted as it is, or this Si waste may be mixed with high purity Si and remelted. In other words, the wafer is made into an ingot and used as an interposer.

  Further, in the process of producing eleven nine and six nine ingots, the Si purity may be taken out at a stage of 90% to 99%. That is, when used as an interposer, it is not necessary to have eleven nine or six nine purity.

  In addition, in the case of a polycrystalline structure, unlike a single crystal, cleavage can be suppressed. In this case, Si powder and fine particles may be sintered. In other words, fine single crystals are different in composition but are integrated in a grain boundary. As a result, chipping and the like during processing can be suppressed, and improvement in strength can be realized.

  For example, it is necessary to suppress the conversion of all Si fine particles into a silicon oxide film at the stage of sintering. That is, even if a silicon oxide film is present in the sintered body, it is necessary that the Si ratio is 50% or more and the weight ratio is large. In other words, since α with the chip is matched, if there is no Si as much as possible, it will not approach the α of the chip.

  for that reason. As will be described with reference to FIG. 9, it is necessary to have a reducing atmosphere. That is, the graph shown in FIG. 10 shows the particle size distribution of cutting waste generated during dicing of the Si wafer. As can be seen from the figure, it is distributed in the range of approximately 0.1 μm to 200 μm. (Note that the particle size distribution measuring apparatus cannot detect particles smaller than 0.1 μm because particles smaller than 0.1 μm cannot be detected. Actually, particles smaller than this are included. This is because, when such very fine particles are sintered, in an oxidizing atmosphere, most of the Si is not converted and a silicon oxide film is converted.

  Now, the interposer 10 will be described with reference to FIG. 1A. First, there is a substrate 20 made of Si. The substrate 20 is a low purity substrate having a purity of about 90 to 99% or about 80 to 99%. This can be done by removing the Si scrap generated in the process of FIG. 2 as it is or by mixing it with virgin Si to make an ingot, and in the process of FIG.

  Then, it demonstrates using FIG. FIG. 2A illustrates a process in which the top and tail of the Si ingot 1 are cut with a jig such as a saw, and the remaining portion is processed into a cylindrical ingot 2 with a grinding jig. At this time, Si waste is generated.

  In FIG. 2B, the cylindrical ingot 2 is sawed, for example, cut with a saw, and processed into a wafer. Also at this time, Si waste is generated. Since this Si scrap becomes a wafer or a substrate for a semiconductor or a solar cell, it is a Si scrap for eleven nine or six nine, in which a predetermined amount of impurities are put, and high purity. Further, although not explained in the drawings, Si scrap generated by back grinding, dicing, etc. of a semiconductor wafer is also an object.

  These debris is melted into an ingot in a reducing atmosphere as shown in FIG. 2C.

  Next, a high-purity Si ingot and the ingot of the present invention will be described with reference to FIG. FIG. 11 is a flow for manufacturing a high-purity Si ingot. First, silica, which is an oxide, is prepared and reductively decomposed using wood chips, coal, etc. to produce metal grade silicon (purity 98%). This metal grade silicon is converted to high purity gas, that is, trichlorosilane using hydrochloric acid, and the gasified one is deposited and melted to produce single crystal silicon. Although high purity is obtained by this flow, the present invention may utilize single crystal or polycrystalline silicon by taking out metal grade silicon before being gasified and deposited. Furthermore, Si scraps may be mixed and melted at the stage of this metal grade silicon.

  If the polishing / grinding scraps shown in FIG. 2 are used, the material can be recycled, so that the cost can be reduced. If metal grade silicon is used, there is no need for gasification, and the cost can be reduced.

  Subsequently, the ingot is processed again into a wafer 11 in FIGS. 2A and 2B, and this wafer 11 is provided with each conductive material and conductive pattern insulated by a normal semiconductor process. Is cut along the dicing line to become an interposer.

  FIG. 1A illustrates the interposer 10. Here, the front electrode 22 and the back electrode 23 are electrically connected by the through electrode 21. The through electrode is filled with conductive polysilicon or by a method such as Cu plating. The through electrode 21 needs to be insulated from the substrate 20, and an insulating film is provided in the through hole 24. Specifically, the insulating film 25 may be deposited by thermal oxidation or by CVD or the like. Here, in the case of thermal oxidation, there is a possibility that impurities 26 present in the substrate 20 may be taken in. Therefore, an insulating film such as a silicon oxide film needs to be separately deposited on the thermal oxide film 25 by CVD. Insulating films 27 and 28 such as a silicon oxide film are also provided on the front and back of the substrate 20.

  For the surface electrode 22, a single-layer metal or a multi-layer metal wiring is selected depending on the number of terminals of the mounted chip. In the drawing, the electrode is shown as a structure in which two layers are laminated, but wiring is also formed integrally with the electrode. One end of the wiring may be integrated with the electrode, and the other end may be integrated with an external connection pad. That is, the pad on the substrate 20 side connected to the pad on the chip may be directly above the through electrode 21 or may be a pad for external connection located via the wiring. Naturally, in the case of a multilayer metal, an interlayer insulating film 29 is formed in order to perform an insulating process.

  Further, considering solder connection, the front and back conductive patterns are provided with a solder resist, and portions where electrical connection means such as solder are provided are opened.

  As described above, although the interposer is formed, since the substrate 20 itself has a purity of 80-99% and contains impurities, there are advantages in that cleavage is suppressed, hardness is increased, and further, the cost is low. In addition, since the α of this interposer is substantially the same as α of Si, the reliability of the mounted chip is also improved.

  FIG. 3 is substantially the same as FIG. 1, and the difference is that the through electrode 21A and the back electrode 23A are formed by plating from the back surface. The rest is the same as FIG.

  That is, the insulating layer 27 on the substrate 20, the opening of the insulating layer 27 where the substrate is exposed, the first conductive pattern 22 provided in the opening, and the second conductive pattern provided via the interlayer insulating film 29. After forming, the through-hole 24 is formed from the back surface.

  After the through hole 24 is formed, an insulating film 25 is formed on the front surface and back surface of the hole, and the back surface of the first layer electrode 22 is exposed. The This conductive film is formed by a film forming technique such as plating or CVD, and is formed only on the surface, and a space is provided in the hole. This conductive film becomes a through electrode and a back electrode. Further, a solder resist SR having an opening at a portion where the solder is formed is provided.

  In this embodiment, the thickness of the substrate can be adjusted by back grinding before the through-hole is opened, and naturally the depth of the hole can be reduced, so that the film formation time can be shortened.

  FIG. 4 describes the back surface of the substrate 20. For example, as shown in FIG. 2B, after slicing into a wafer, the front and back surfaces are generally mirror-polished in a semiconductor process. However, considering that it is not necessary to form a fine pattern as that of a semiconductor and that the back surface of the interposer is mounted on a printed circuit board, the back surface may be formed rougher than the front surface of the substrate. The front surface is polished and the back surface is not formed at all or is slightly rough polished to finish. In this case, adhesion with the film on the back surface is improved, and film peeling due to stress with the mounting substrate can be prevented.

  5 and 6 show an example when the interposer 16 shown in FIGS. 1 and 3 is mounted on the mounting board 19.

  FIG. 5 shows a view in which a chip 13 mounted face-down on an interposer 16 and a laminated chip 14 electrically connected by a through electrode 17 are provided. This is different from FIG. 6 in that the sealing resin 30 is not provided.

  On the other hand, in FIG. 6, the interposer 16 shown in FIG. 5 is sealed with the resin 30 including the chips 13 and 14.

  In both cases, impurities are mixed in Si and the purity is not as high as Eleven Nine and Six Nine. Since this is simply used as a wiring board and α does not differ greatly from the chip, it is adopted and effective in terms of cost and environment.

  7 and 8, the cavity 40 is formed in the interposer 10, the chip 41 is mounted face up there, and the electrodes extend from the front surface to the back surface of the interposer.

  As described above, the interposer 10 uses a substrate mixed with impurities, and a cavity 40 is provided at the center thereof. The back surface and front surface of the substrate and the inner wall of the cavity are all insulated with an insulating film, and the chip 41 is fixed in the cavity 40 with an adhesive. The thickness of the chip is slightly smaller than the depth of the cavity, and the entire surface is covered with an insulating resin or the like in order to make the interposer surface and the concave portion of the chip surface the same surface. The surface of the insulating resin 42 becomes substantially flat due to the fluidity of the insulating resin 42. Further, when the fluidity is low and the flatness is poor, the surface is flattened by performing a flattening process.

  Further, the insulating resin 42 is opened at the portion of the electrode on the chip 41, and extends from the chip 41 side to the surface electrode 43 corresponding to the through electrode 24. The front electrode 43 is electrically connected to the back electrode 23 through the through electrode 24.

  FIG. 8 shows a through electrode structure having the same structure as that described with reference to FIG.

  Next, a method for molding and sintering Si powder generated by polishing and grinding will be described with reference to FIG.

  First, a powder made of Si is prepared. Although it is 7 μm or less in the drawing, a particle size distribution as shown in FIG. 10 may be used.

  In any case, this is because the powder is pulverized and mixed in the next step. In this pulverization / mixing step, a cylindrical pot 50 capable of storing powder is prepared and pulverized by a ball mill 51 contained therein. The entire pot 50 is rotated and pulverized by rolling of the ball mill. As shown in FIG. 10, when the size of the powder is large, a desired particle size distribution can be realized by increasing the pulverization time. Although it is described as 1 micrometer or less beside the figure of a pot, it is not this limitation.

  Subsequently, the binder is put in the pot 50 and kneaded. As shown in the figure, a binder 53 is attached around the Si powder and is slurried. This binder is mainly composed of adhesive glue and is made of an organic material such as acrylic resin and / or butyral. In this, a composite oxide (metal oxide) such as manganese oxide and titanium oxide is blended as a sintering accelerator.

  Therefore, as shown in the figure, the binder covers the periphery of the Si powder. Then, the molding process begins.

  Here, it can be formed into a cylindrical shape or a quadrangular prism shape, and if it is sintered, the pasty substance made of an organic substance is vaporized as carbon dioxide gas, around the Si powder, that is, at the grain boundary, the metal oxide Since an object exists and is sintered, the insulation can be improved.

  Moreover, since Si is a fine powder, Si may be converted into silicon oxide. Therefore, if sintering is performed in a non-oxidizing atmosphere, for example, a nitrogen atmosphere, a hydrogen atmosphere, or a mixed atmosphere of both, oxidation of Si can be suppressed.

  Basically, the finished sintered body preferably has an Si content ratio of 50% or more of the total weight.

  Also, as with ceramics, since it is like a green sheet when molded, the vias, that is, the through holes in FIG. 1 and the cavities in FIG. 7, can be easily processed by pressing them with a punch or a mold. Can do. Of course, since it shrinks at the time of sintering, there is some difficulty in dimensional accuracy. However, dimensional accuracy can also be obtained by considering the shrinkage rate.

  If this sintered body is utilized as an interposer, it has the following merits in addition to substantially matching α. For example, by etching the front surface and / or the back surface, etching can be performed along the interface of the Si powder, that is, the grain boundary, and irregularities can be formed on the surface. Therefore, even when an organic or inorganic insulating film is formed, adhesion can be improved. For example, an insulating resin is remarkable.

  The through hole may be drilled with a drill or the like after being sintered. Further, the through electrode, the front surface electrode, the back surface electrode, the insulating layer, and the like have the structure shown in FIGS. 1 and 7 and will not be described in detail.

  As described above, an interposer having a Si sintered body having a purity of Si of 50% or more, and a single crystal or polycrystal having a Si purity of 90 to 99% can be realized at a low cost with almost the same α. Therefore, even if a chip is placed, stress can be suppressed and deterioration can be prevented.

  Moreover, impurities that determine the conductivity type of the diffusion region, such as B, P, or As, are mixed in Si scrap generated in the semiconductor polishing / grinding process. Therefore, a P-type or N-type region is rarely generated in a single crystal or polycrystal substrate.

  In consideration of the formation of a parasitic capacitance and a parasitic element by forming a wiring or the like on the conductive region, the substrate may be fixed to a predetermined potential such as VCC or GND.

  This interposer is mainly used for chip mounting, but in addition, a thin-film solar cell may be coated, or a sensor such as a SAW filter or a crystal resonator may be provided.

It is a figure explaining the mounting substrate of this invention. It is a figure explaining the generation | occurrence | production process of Si waste. It is a figure explaining the mounting substrate of this invention. It is a figure explaining the board | substrate back surface of this invention. It is a figure explaining the application example of the mounting board | substrate of this invention. It is a figure explaining the application example of the mounting substrate of this invention. It is a figure explaining the mounting substrate of this invention. It is a figure explaining the mounting substrate of this invention. It is a figure explaining the sintering method of Si powder. It is a figure explaining the particle size distribution of Si powder. It is a figure explaining the manufacturing method of Si ingot.

Explanation of symbols

13: Chip 14: Multilayer chip 15: Bump 16: Interposer 17: Through electrode 19: Mounting substrate 20: Substrate 21: Through electrode 22: Front electrode 23: Back electrode 24: Through hole 25: Insulating film 26: Impurity

Claims (17)

A mounting substrate made of Si for mounting a semiconductor chip made of Si,
At least one surface electrode corresponding to the pad electrode provided on the semiconductor chip is provided on the surface of the substrate, and at least one back surface electrically connected to the surface electrode is provided on the back surface of the substrate. Electrodes are provided,
A mounting substrate made of Si, characterized in that the Si purity of the substrate is 99% or less. The substrate made of Si includes a melt of Si scrap generated by polishing, grinding, or sawing, and is a P or N-type impurity, an impurity made of an electrode material, or a constituent material of a processing member for polishing, grinding, or sawing The mounting substrate made of Si according to claim 1, wherein an impurity made of The mounting substrate made of Si according to claim 1, wherein the substrate made of Si contains at least one of B, P, As, Al, Cu, or Fe. The mounting substrate made of Si according to claim 1, 2 or 3, which has a hardness higher than that of Si having a purity exceeding 99%. The mounting substrate made of Si according to claim 1, claim 2 or claim 3 made of polycrystal. The mounting substrate made of Si according to claim 1, 2, or 3, wherein the roughness of the back side of the substrate is larger than that of the front side of the substrate. 7. The front surface of the substrate is provided with a plurality of surface electrodes or surface wirings via an insulating layer, and at least a single-layer back electrode or at least a single-layer back surface wiring is provided on the back of the substrate. Mounting substrate made of Si. The mounting substrate made of Si according to claim 1, wherein the mounting substrate made of Si is a sintered body formed by sintering Si scrap generated by polishing, grinding, or sawing. The mounting substrate made of Si according to claim 8, wherein an average particle diameter of Si in the sintered body is 1 μm or less. The mounting substrate made of Si according to claim 8 or 9, wherein the grain boundary of the sintered body contains a metal oxide as a sintering accelerator. The mounting substrate made of Si according to claim 10, wherein the metal oxide is a complex oxide of manganese oxide and titanium oxide. The through via provided from the front side to the back side of the substrate is formed of Si according to any one of claims 8 to 11 formed by punching or die processing when the green sheet is fired. Mounting board. The semiconductor module according to claim 1, wherein a semiconductor chip made of Si is mounted on the mounting board made of Si. The semiconductor module according to claim 1, wherein the mounting substrate made of Si provided with the semiconductor chip made of Si is mounted on a mounting substrate made of resin. The mounting substrate made of Si according to claim 1, wherein a P-type or N-type diffusion region is formed on the mounting substrate made of Si. The P-type or N-type impurity is diffused in the mounting substrate made of Si, and is fixed to a desired voltage in order to suppress parasitic capacitance with the front surface electrode or the front surface wiring, or the back surface electrode or the back surface wiring. A mounting substrate made of Si according to claim 7. The semiconductor module according to claim 7, wherein a thin-film solar cell is formed on the mounting substrate made of Si.

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