JP2009042030A - Test method and test apparatus for semiconductor integrated circuit device - Google Patents

Abstract

A semiconductor integrated circuit device including a power supply pad, a GND pad, and an output pad and having a function of outputting a predetermined constant voltage from the output pad is provided with a circuit for accurately transmitting the internal voltage from the semiconductor integrated circuit device. Even if not, the semiconductor integrated circuit device under test is tested with high accuracy.
A power supply unit 11 and a power pad terminal 13 for supplying a voltage to a power pad 13 of an IC chip 7, a GND pad terminal 17 for connecting a GND pad 3 of the IC chip 7 to a GND 15, The output pad terminal 19 that is in contact with the output pad 5 of the IC chip 7, the comparators 21a and 21b for comparing the voltage of the output pad terminal 19 and the standard voltage, and the standard voltage generation for generating the standard voltage Circuits 23a and 23b are provided. The standard voltage generation circuits 23 a and 23 b generate standard voltages with reference to the voltage of the GND pad 3.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a resistance element and a manufacturing method thereof.

In recent years, semiconductor integrated circuit devices equipped with a voltage regulator (hereinafter abbreviated as VR) have become highly accurate, and recently, products that require an accuracy of 10 mV (millivolt) or less are not uncommon.
For example, when a VR is tested in a wafer state, a contact jig usually called a probe card is used. The test device and the VR chip to be tested are connected by contacting a contact probe provided on the probe card to the pad of the VR chip to be tested, and an electrical signal is sent from the test apparatus to the VR chip to be tested.

  In recent semiconductor integrated circuits, functions are compounded, and products in which a plurality of VRs are mounted on the same chip or functions other than VR are formed on the same chip are increasing. In a semiconductor integrated circuit, current consumption is generated by an internal operation. However, as the number of functions formed on the same chip increases, the current consumption generally tends to increase.

  The GND pad of the VR chip to be tested is connected to the GND of the test apparatus via the contact probe. However, since a contact resistance is generated between the pad surface of the VR chip to be tested and the contact probe, a voltage drop is caused by the current flowing through the GND. As a result, the GND voltage inside the VR chip under test becomes a value higher than 0 V with respect to the GND voltage (0 V) of the test apparatus.

  In a normal test, a voltage is applied to the semiconductor integrated circuit device under test using a test device called a tester. Since all the voltages at this time are based on the GND voltage (0 V) of the test apparatus, a potential difference occurs with the GND voltage inside the VR chip to be tested, thereby causing a problem that measurement accuracy is lowered.

  Similarly, in a unit test (also called a final test) performed after being sealed in a package, the VR chip to be tested is connected to an IC socket necessary for connecting an electrical signal between the VR chip to be tested and the test apparatus. Since contact resistance is generated at the connection point between the terminal and the terminal of the IC socket, there is a problem that a potential difference is generated between the GND voltage of the test apparatus and the GND voltage inside the VR chip to be tested, resulting in a decrease in measurement accuracy.

  Since the contact resistance changes depending on the contact state, the contact resistance changes even if the VR chip under test is the same every time contact is made, and it is difficult to estimate the GND voltage of the VR chip under test. Note that when the VR is actually mounted on a product and used, the probe card and IC socket that cause the contact resistance are not necessary, so this contact resistance is a problem only in the test.

  As a conventional technology that solves the problems caused by the potential difference between the GND voltage of the test equipment and the GND voltage inside the VR chip under test, the voltage is accurately measured by a special circuit provided inside the chip to accurately read the voltage inside the chip from the outside. There is a semiconductor integrated circuit device including a driving circuit for transmitting (see, for example, Patent Document 1).

JP 11-66890 A

When testing a semiconductor integrated circuit device having a voltage generation circuit such as a voltage regulator, the GND voltage of the test device and the GND voltage inside the semiconductor integrated circuit device under test are determined by the contact resistance at the GND pad of the semiconductor integrated circuit device to be tested. Therefore, there is a problem that a potential difference occurs and the measurement accuracy decreases. As a result, there is a problem of reducing the yield of non-defective products.
In addition, when a circuit that accurately transmits the internal voltage is provided as in the semiconductor integrated circuit device disclosed in Patent Document 1, there is a problem in that the chip area increases and the manufacturing cost of the semiconductor integrated circuit device increases. was there.

  The present invention provides a circuit that includes a power supply pad, a GND pad, and an output pad, and the semiconductor integrated circuit device accurately transmits an internal voltage to a semiconductor integrated circuit device having a function of outputting a predetermined constant voltage from the output pad. An object of the present invention is to provide a test method and a test apparatus that can test a semiconductor integrated circuit device under test with high accuracy even if it is not provided.

  A test method for a semiconductor integrated circuit device according to the present invention is a test method for a semiconductor integrated circuit device comprising a power supply pad, a GND pad, and an output pad, and having a function of outputting a predetermined constant voltage from the output pad. A comparator that supplies a voltage to the power supply pad of the test semiconductor integrated circuit device, and compares the voltage output from the output pad with the standard voltage while the GND pad is connected to the GND and the semiconductor integrated circuit device is driven. And a standard voltage generation circuit for generating the standard voltage, the standard voltage generation circuit generates the standard voltage with reference to the GND pad voltage, and the semiconductor integrated circuit under test based on the output of the comparator The pass / fail of the circuit device is determined.

  In the test method of the present invention, the semiconductor integrated circuit device under test includes a second GND pad that has the same voltage as the GND pad and is provided for the purpose of detecting the voltage of the GND pad. An example in which the standard voltage is generated by the standard voltage generation circuit based on the voltage of the second GND pad can be given.

  Further, a DA conversion circuit may be used as the standard voltage generation circuit, and a voltage standard code for causing the DA conversion circuit to generate the standard voltage may be recorded in a storage device in advance.

  Further, a High-side comparator and a Low-side comparator are used as the comparator, and a High-side standard voltage generation circuit for supplying a High-side standard voltage to the High-side comparator as the standard voltage generation circuit and the Low-side comparison. A low-side standard voltage generation circuit for supplying a low-side standard voltage to the comparator, and the pass / fail of the semiconductor integrated circuit device under test is determined based on the outputs of the high-side comparator and the low-side comparator. Good.

  A test apparatus for a semiconductor integrated circuit device according to the present invention includes a power supply pad, a GND pad, and an output pad, and a test apparatus for testing a semiconductor integrated circuit device having a function of outputting a predetermined constant voltage from the output pad. A power supply unit and a power supply pad terminal for supplying a voltage to a power supply pad of the semiconductor integrated circuit device under test; a GND pad terminal for connecting the GND pad of the semiconductor integrated circuit device under test to the GND; An output pad terminal in contact with the output pad of the semiconductor integrated circuit device under test; a comparator for comparing the voltage of the output pad terminal with a standard voltage; and a standard voltage generation for generating the standard voltage The standard voltage generation circuit generates the standard voltage with reference to the voltage of the GND pad.

  In the test apparatus according to the present invention, a semiconductor integrated circuit device to be tested is one having the same voltage as the GND pad and having a second GND pad provided for the purpose of detecting the voltage of the GND pad. A second GND pad terminal that is in contact with the second GND pad may be further provided, and the standard voltage generation circuit may generate the standard voltage based on the voltage of the second GND pad.

  Further, a DA conversion circuit may be provided as the standard voltage generation circuit, and a storage device for previously recording a voltage standard code for causing the DA conversion circuit to generate the standard voltage may be further provided. .

  The comparator includes a high-side comparator and a low-side comparator, and the high-side standard voltage generation circuit for supplying the high-side standard voltage to the high-side comparator as the standard voltage generation circuit and the low-side comparison. A low-side standard voltage generation circuit for supplying a low-side standard voltage to the comparator, and a comprehensive judgment circuit for judging pass / fail of the semiconductor integrated circuit device under test based on the outputs of the high-side comparator and the low-side comparator Further, it may be provided.

According to the test method of a semiconductor integrated circuit device of the present invention, a standard voltage generation circuit for supplying a standard voltage to a comparator that compares a voltage output from an output pad with a standard voltage, and the GND pad of the semiconductor integrated circuit device under test The standard voltage is generated based on the voltage of.
In the test apparatus for a semiconductor integrated circuit device of the present invention, the power supply unit for supplying a voltage to the power supply pad of the semiconductor integrated circuit device under test and the terminal for the power supply pad, and the GND pad of the semiconductor integrated circuit device under test are connected to the GND. A GND pad terminal for connection to the output pad, an output pad terminal in contact with the output pad of the semiconductor integrated circuit device under test, a comparator for comparing the voltage of the output pad terminal with the standard voltage, and the standard voltage The standard voltage generation circuit is configured to generate the standard voltage with reference to the voltage of the GND pad.
In the test method and test apparatus according to the present invention, even if the GND voltage inside the semiconductor integrated circuit device under test rises due to the contact resistance at the GND pad of the semiconductor integrated circuit device under test, the standard voltage generating circuit is increased by that amount. Therefore, even if the semiconductor integrated circuit device does not have a circuit that accurately transmits the internal voltage, the semiconductor integrated circuit device under test can be tested with high accuracy.
Furthermore, the conventional test method and test apparatus require a voltage measurement unit for measuring the voltage output from the output pad of the semiconductor integrated circuit device during the test, but the test method and test apparatus of the present invention are compared. Since the pass / fail of the semiconductor integrated circuit device under test can be determined based on the output of the device, it is not necessary to provide a voltage measuring unit.

In the test method of the present invention, the semiconductor integrated circuit device under test includes a second GND pad that is provided for the purpose of detecting the voltage of the GND pad, which is the same voltage as the GND pad, and generates a standard voltage. The standard voltage may be generated by the circuit with reference to the voltage of the second GND pad.
In the test apparatus of the present invention, a semiconductor integrated circuit device under test having the same voltage as that of the GND pad and having the second GND pad provided for the purpose of detecting the voltage of the GND pad is used. The standard voltage generation circuit may further generate a standard voltage with reference to the voltage of the second GND pad.
Since the second GND pad is not connected to the GND of the test apparatus, no current flows through the second GND pad and no voltage effect occurs. As a result, it is possible to generate a standard voltage based on the GND level of the semiconductor integrated circuit device under test, ignoring the contact resistance generated at the second GND pad.
Even when the standard voltage is generated with reference to the voltage of the GND pad, no current flows between the GND pad and the standard voltage generation circuit. In addition, the method of supplying the GND pad voltage to the standard voltage generation circuit is to provide a standard voltage generation circuit terminal separately from the GND pad terminal, and bring the GND pad terminal and the standard voltage generation circuit terminal into contact with the GND pad. May be.

In the test method of the present invention, a DA conversion circuit may be used as the standard voltage generation circuit, and a voltage standard code for causing the DA conversion circuit to generate a standard voltage may be recorded in the storage device in advance.
The test apparatus of the present invention includes a DA conversion circuit as a standard voltage generation circuit, and further includes a storage device for recording in advance a voltage standard code for causing the DA conversion circuit to generate a standard voltage. Also good.
This makes it possible to easily change the standard voltage supplied to the comparator from the DA converter circuit as the standard voltage generation circuit.

In the test method of the present invention, a high-side comparator and a low-side comparator are used as comparators, and a high-side standard voltage generator for supplying a high-side standard voltage to a high-side comparator as a standard voltage generator and a low-side A low-side standard voltage generation circuit for supplying a low-side standard voltage to the comparator may be used, and pass / fail of the semiconductor integrated circuit device under test may be determined based on the outputs of the high-side comparator and the low-side comparator. Good.
In the test apparatus according to the present invention, a high side comparator and a low side comparator are provided as comparators, and a high side standard voltage generation circuit and a low side for supplying a high side standard voltage to the high side comparator as a standard voltage generation circuit. A general determination circuit that includes a low-side standard voltage generation circuit for supplying a low-side standard voltage to the comparator, and determines pass / fail of the semiconductor integrated circuit device under test based on the outputs of the high-side comparator and the low-side comparator. Further, it may be provided.
This facilitates the determination of the pass / fail of the semiconductor integrated circuit device under test.

FIG. 1 is a circuit diagram showing an embodiment of a test apparatus. An embodiment of the test apparatus will be described with reference to FIG.
This test apparatus is a test apparatus for testing an IC chip 7 that includes a power supply pad 1, a GND pad 3, and an output pad 5 and has a function of outputting a predetermined constant voltage from the output pad 5. The IC chip 7 also includes a second GND pad 9 that is provided for the purpose of detecting the voltage of the GND pad 3 that is the same voltage as the GND pad 3.

  The test apparatus includes a power supply unit 11 and a power supply pad terminal 13 for supplying a voltage to the power supply pad 1 of the IC chip 7, a GND pad terminal 17 for connecting the GND pad 3 of the IC chip 7 to the GND 15, An output pad terminal 19 that is in contact with the output pad 5 of the IC chip 7; comparators 21a and 21b for comparing the voltage (Vout) of the output pad terminal 19 with a high-side standard voltage or a low-side standard voltage; DA converters (standard voltage generation circuits) 23a and 23b for generating a high-side standard voltage or a low-side standard voltage are provided.

  The output of the high-side standard voltage DA converter 23a is connected to, for example, the non-inverting input terminal (+) of the high-side comparator 21a, and the output of the low-side standard voltage DA converter 23b is connected to, for example, the inverting input terminal (− )It is connected to the. The output pad terminal 19 is connected to, for example, the inverting input terminal (−) of the High side comparator 21a and, for example, the non-inverting input terminal (+) of the Low side comparator 21b.

In addition, a high-side voltage generation circuit 25a for supplying power to the high-side standard voltage DA converter 23a and a low-side voltage generation circuit 25b for supplying power to the low-side standard voltage DA converter 23b are also provided.
Furthermore, the second GND pad 9 is also provided with a second GND pad terminal 27 for connecting the GND of the DA converters 23a and 23b and the voltage generation circuits 25a and 25b.

  During the test of the IC chip 7, a contact resistance 29 is generated between the power pad 1 and the power pad terminal 13, a contact resistance 31 is generated between the GND pad 3 and the GND pad terminal 17, and the output pad 5 and the output pad A contact resistance (not shown) is generated between the terminals 19, and a contact resistance 33 is generated between the second GND pad 9 and the second GND pad terminal 27.

The test apparatus also includes an AND circuit 35 to which the outputs of the comparators 21a and 21b are input. The output of the AND circuit 35 is connected to the expected value determination unit 37.
The output of the high-side standard voltage memory 39a for recording the high-side standard voltage value digital code for determining the high-side standard voltage, which is the output of the high-side standard voltage DA converter 23a, and the output of the low-side standard voltage DA converter 23b. A Low-side standard voltage memory 39b for recording a Low-side standard voltage value digital code for determining a certain Low-side standard voltage is also provided. The standard voltage memories 39a and 39b are formed by nonvolatile memories. The high-side standard voltage memory 39a stores a digital code generated by the high-side pattern generation unit 41a. A digital code generated by the low-side pattern generation unit 41b is recorded in the low-side standard voltage memory 39b.

For example, when the DA converters 23a and 23b are of 12 bits and the reference voltage generated by the voltage generation circuits 25a and 25b is 3V, 3.0 / 4096 = 0.73V per 1 bit, so the standard voltage memory 39a , 39b outputs 556h (hexa signal), the outputs of the DA converters 23a, 23b are 1V. If the output of the standard voltage memories 39a and 39b is 800h, the outputs of the DA converters 23a and 23b are 1.5V.
FIG. 2 shows an example of tester pattern generation on the High side. In FIG. 2, the high-side standard voltage memory 39a is not shown.

  Further, when the number of channels of the high-side pattern generation unit 41a is small, as shown in FIG. 3, it is possible to generate a 12-bit digital code necessary for one channel by using a serial / parallel converter 43a. is there. From the channel 1, 1,0, 1, 1, 0, 1,..., 12 data are input to the serial / parallel converter 43a and assigned to D0 to D11 of the DA converter 23a for parallel output. This can be achieved.

  Further, when the voltage standard memories 39a and 39b are, for example, 10 bits and the necessary memory bits are 7 bits, the channels of the pattern generation units 41a and 41b are connected to A0 to A6 as shown in FIG. By connecting A7 to A9 to GND, A7 to A9 = 0V, and unnecessary tester resources can be reduced.

  During the test, the high-side comparator 21a compares the high-side standard voltage with the output voltage of the IC chip 7, and outputs “1” (Pass) if the output voltage of the IC chip 7 is equal to or less than the high-side standard voltage value. If the output voltage of the IC chip 7 is higher than the high-side standard voltage, “0” (Fail) is output. The low-side comparator 21b compares the low-side standard voltage with the output voltage of the IC chip 7, and outputs “1” (Pass) if the output voltage of the IC chip 7 is equal to or higher than the low-side standard voltage value. If the output voltage of the IC chip 7 is smaller than the low-side standard voltage, “0” (Fail) is output. The AND circuit 35 outputs a comprehensive determination result “1” (Pass) when both the outputs of the comparators 21 a and 21 b are “1”, and either or both of the outputs of the comparators 21 a and 21 b are “0”. Sometimes the comprehensive determination result “0” (Fail) is output and sent to the expected value determination unit 37.

  In this test apparatus, the DA converters 23a and 23b generate standard voltages to be input to the comparators 21a and 21b with reference to the voltages of the GND pad 3 and the second GND pad 9. For example, when the internal GND voltage of the IC chip 7 is 10 mV due to the contact resistance 31, the GND voltages of the DA converters 23a and 23b and the voltage generation circuits 25a and 25b are also 10 mV. At this time, the output voltage of the voltage generation circuits 25a and 25b is a voltage higher by 10 mV than the set value, and the standard voltage generated by the DA converters 23a and 23b is also a voltage higher by 10 mV than the set value. Further, since the internal GND voltage of the IC chip 7 is 10 mV, the voltage output from the output pad 5 of the IC chip 7 is also a voltage shifted by +10 mV.

  As described above, even if the GND voltage in the IC chip 7 rises due to the contact resistance 31 in the GND pad 3 of the IC chip 7, the standard voltage is raised by the DA converters 23a and 23b by the rise. Therefore, even if the IC chip 7 does not include a circuit that accurately transmits the internal voltage, the IC chip 7 can be tested with high accuracy.

  FIG. 5 is a circuit diagram showing another embodiment of the test apparatus. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

  In this test apparatus, a high-side VR 45a is provided as a voltage generator for supplying a reference voltage to the high-side standard voltage DA converter 23a, and a low-side VR 45b is provided as a voltage generator for supplying a reference voltage to the low-side standard voltage DA converter 23b. ing. The GNDs of the VRs 45 a and 45 b are connected to the second GND pad terminal 27.

  Further, a voltage generation unit 47 for supplying power to the VRs 45a and 45b is provided. For example, when the output voltage of the VRs 45a and 45b is set to 3.0V, the voltage supplied by the voltage generation unit 47 may be set to 3.5V.

  Also in this test apparatus, as in the embodiment described with reference to FIG. 1, when the internal GND voltage of the IC chip 7 increases due to the contact resistance 31, the DA converters 23a, 23b and VR45a are increased by the increase. , 45b GND voltage also rises, so that the IC chip 7 can be tested with high accuracy.

  As mentioned above, although the Example of this invention was described, this invention is not limited to these, A various change is possible within the range of this invention described in the claim.

  For example, in the above embodiment, the IC chip 7 which is the semiconductor integrated circuit device under test includes the second GND pad 9 provided for the purpose of detecting the voltage of the GND pad 3 which is the same voltage as the GND pad 3. However, the semiconductor integrated circuit device under test is not limited to this, and may not include the second GND pad 9. In this case, the second GND pad terminal 27 may be used as a standard voltage generation circuit terminal, and the GND pad terminal and the standard voltage generation circuit terminal may be brought into contact with the GND pad.

It is a circuit diagram which shows one Example of a test apparatus. It is a figure which shows the example of the tester pattern production | generation by the side of the High in the Example. It is a figure which shows the other example of the tester pattern production | generation of the High side in the Example. It is a figure which shows the further another example of the tester pattern generation by the High side in the Example. It is a circuit diagram which shows the other Example of a test apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply pad 3 GND pad 5 Output pad 7 IC chip (semiconductor integrated circuit device)
9 Second GND pad 11 Power supply unit 13 Power supply pad terminal 15 GND
17 GND pad terminal 19 Output pad terminal 21a High side comparator 21b Low side comparator 23a High side standard voltage DA converter (standard voltage generation circuit)
23b Low side standard voltage DA converter (standard voltage generation circuit)
27 Second GND pad terminals 29, 31, 33 Contact resistance 35 AND circuit (overall judgment circuit)
39a, 39b Voltage standard memory (storage device)

Claims (8)

In a test method of a semiconductor integrated circuit device comprising a power supply pad, a GND pad and an output pad, and having a function of outputting a predetermined constant voltage from the output pad.
Comparison in which a voltage is supplied to the power supply pad of the semiconductor integrated circuit device under test, and the voltage output from the output pad is compared with the standard voltage when the GND pad is connected to GND and the semiconductor integrated circuit device is driven And a standard voltage generation circuit for generating the standard voltage,
The standard voltage generation circuit generates the standard voltage with reference to the voltage of the GND pad,
A test method for a semiconductor integrated circuit device, wherein pass / fail of the semiconductor integrated circuit device under test is determined based on an output of the comparator. The semiconductor integrated circuit device under test includes a second GND pad provided for the purpose of detecting the voltage of the GND pad, which is the same voltage as the GND pad,
The test method according to claim 1, wherein the standard voltage is generated by the standard voltage generation circuit with reference to the voltage of the second GND pad.   The test method according to claim 1 or 2, wherein a DA conversion circuit is used as the standard voltage generation circuit, and a voltage standard code for causing the DA conversion circuit to generate the standard voltage is recorded in a storage device in advance. As the comparator, a high-side comparator and a low-side comparator are used,
As the standard voltage generation circuit, a high side standard voltage generation circuit for supplying a high side standard voltage to the high side comparator and a low side standard voltage generation circuit for supplying a low side standard voltage to the low side comparator are provided. Use
The test method according to claim 1, wherein pass / fail of the semiconductor integrated circuit device under test is determined based on outputs of the high-side comparator and the low-side comparator. In a test apparatus for testing a semiconductor integrated circuit device having a power pad, a GND pad, and an output pad, and having a function of outputting a predetermined constant voltage from the output pad,
A power supply unit and a power supply pad terminal for supplying a voltage to the power supply pad of the semiconductor integrated circuit device under test;
A GND pad terminal for connecting the GND pad of the semiconductor integrated circuit device under test to the GND;
An output pad terminal that is in contact with the output pad of the semiconductor integrated circuit device under test;
A comparator for comparing the voltage of the output pad terminal with a standard voltage;
A standard voltage generation circuit for generating the standard voltage;
The test apparatus for a semiconductor integrated circuit device, wherein the standard voltage generation circuit generates the standard voltage with reference to a voltage of the GND pad. As the semiconductor integrated circuit device under test, a semiconductor integrated circuit device having the same voltage as the GND pad and having a second GND pad provided for the purpose of detecting the voltage of the GND pad is used.
A second GND pad terminal that is in contact with the second GND pad;
The test apparatus according to claim 5, wherein the standard voltage generation circuit generates the standard voltage with reference to a voltage of the second GND pad. A DA conversion circuit is provided as the standard voltage generation circuit,
The test apparatus according to claim 5 or 6, further comprising a storage device for recording in advance a voltage standard code for causing the DA converter circuit to generate the standard voltage. A high side comparator and a low side comparator are provided as the comparators,
As the standard voltage generation circuit, a high side standard voltage generation circuit for supplying a high side standard voltage to the high side comparator and a low side standard voltage generation circuit for supplying a low side standard voltage to the low side comparator are provided. Prepared,
8. The test apparatus according to claim 5, further comprising a comprehensive determination circuit that determines pass / fail of the semiconductor integrated circuit device under test based on outputs of the high-side comparator and the low-side comparator.

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