JP2008306030A - Mark design device and position detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an error in setting an artificial parameter of a person in charge when designing a mark for position detection, and to prevent a decrease in yield and an operation rate due to an artificial error.
In a mark design apparatus for designing a mark formed on a substrate and detected by a position detection apparatus, means for editing parameters including the type of mark, the width and number of lines constituting the mark, and the parameters Means for forming an image of the mark determined by the above, and display means for displaying the element for editing the parameter and the image of the formed mark on a single screen.
[Selection] Figure 1

Description

  The present invention relates to a mark design apparatus for setting a configuration of a mark formed on a substrate of an element and detected by a position detection device in a manufacturing process of a semiconductor element, a liquid crystal element, or the like.

  Conventionally, when a plurality of patterns are aligned in a manufacturing process of a semiconductor element or a liquid crystal element, the pattern is positioned using an alignment mark. For example, in the field of semiconductor elements, alignment marks are used for alignment between a silicon substrate and an exposure mask (original). In the field of liquid crystal elements, alignment marks have been used in processes such as alignment of color filters and transparent conductive films and alignment of color filter substrates and counter substrates.

In addition to alignment, marks for error measurement are used in overlay misalignment inspection and the like. This is because the mark detection accuracy and measurement accuracy vary depending on the mark shape and line width. As described above, a person in charge of each manufacturing process of a semiconductor or liquid crystal manufacturer needs to select a mark shape or a line width in accordance with each process in the manufacturing process of the semiconductor element or the liquid crystal element. In order to efficiently perform the selection of the mark, there is a technique in which a simulation regarding mark design is performed in advance and an optimum mark is selected from existing marks (Patent Document 1). At this time, it was necessary to manually input parameters when creating or tuning a mark pattern independently. For this reason, the person in charge of the manufacturing process inputs the mark design related parameters on the mark design editing screen prepared by the exposure apparatus manufacturer or the like.
JP 2004-0777550 A

  However, exposure apparatus manufacturers tend to increase the parameters that can be set so that the person in charge of the manufacturing process can perform the fine tuning necessary for finer alignment. In addition, exposure apparatus manufacturers tend to complicate alignment marks in order to increase detection accuracy and measurement accuracy, which also increases the parameters set by the person in charge of the manufacturing process.

Such an increase in parameters increases the probability that the person in charge will make an artificial parameter setting error, causing a decrease in yield, and a decrease in the operation rate of the exposure system due to an abnormal stop of the measurement process for detecting misalignment. It becomes a factor of.
An object of the present invention is to solve the problems in the above-described conventional example.

  In order to solve the above-described problems, the present invention provides a mark design apparatus for designing a mark formed on a substrate and detected by a position detection apparatus, and editing means for editing parameters for determining the configuration of the mark An image forming means for forming an image of the mark determined by the parameter, and a display means for displaying the element for editing the parameter and the image of the formed mark on one screen on a GUI. A design apparatus, an alignment apparatus having the apparatus, and an exposure apparatus are provided.

  According to the present invention, since there is a display means for displaying the parameters as an editing element and a mark image on a single screen, artificial mark design parameter setting errors can be reduced. This reduces manufacturing defects due to design parameter setting errors, increases the operating rate of the apparatus, and reduces costs.

  In a preferred embodiment of the present invention, the present invention is applied for detecting misalignment between an original plate and a substrate in an exposure apparatus that exposes a pattern formed on the original plate and a pattern formed on the substrate in an overlapping manner. . That is, marks detected by a position detection device that measures a plurality of marks formed on the substrate with a detection optical system and calculates a displacement amount of the entire substrate and a displacement amount of a pattern formed on the substrate are detected. It becomes a device that can be designed. The position detection apparatus includes an editing unit that edits a parameter that determines the configuration of the mark, and an image forming unit that forms an image of the mark determined by the parameter. Further, there is provided display means for displaying the element for editing the parameter and the image of the formed mark on a single screen.

  Here, the original is a mask, a reticle, or the like, and the substrate is a semiconductor wafer, a liquid crystal panel, or a glass substrate for a color filter. The parameters that determine the mark configuration are, for example, the type of the mark and the width and number of lines forming the mark.

  In the present embodiment, the display means highlights on the display means the influence of the parameter edited by the editing means on the image of the mark. Further, the editing means can edit the corresponding parameter by directly manipulating the image on the mark image on the display means.

  In the present embodiment, the parameter constraint may be displayed on the display means. Furthermore, when the mark is imported, the image of the mark may be displayed as a thumbnail on the display means.

  FIG. 8 is a perspective view showing the appearance of a semiconductor exposure apparatus according to an embodiment of the present invention. This semiconductor exposure apparatus has the same hardware configuration as a general semiconductor exposure apparatus.

  The semiconductor exposure apparatus of FIG. 8 includes a temperature control chamber 801 that controls the environmental temperature of the apparatus main body, and an EWS main body 806 that is disposed inside the apparatus and has a CPU that controls the apparatus main body. Also provided is an EWS display 802 that displays predetermined information in the apparatus, and a monitor TV 805 that displays image information obtained via the imaging means in the apparatus main body. Furthermore, an operation panel 803 for performing predetermined input to the apparatus and a console unit including an EWS keyboard 804 and the like are provided. In the figure, 807 is an ON-OFF switch, 808 is an emergency stop switch, 809 is various switches, a mouse, etc. 810 is a LAN communication cable. Reference numeral 811 denotes an exhaust duct for generating heat from the console function, and 812 denotes an exhaust device for the chamber.

  The semiconductor exposure apparatus main body is installed inside the chamber 801. The EWS display 802 is a thin flat type such as EL, plasma, liquid crystal, etc., is housed in the front surface of the chamber 801, and is connected to the EWS main body 806 by a LAN cable 810. An operation panel 803, a keyboard 804, a monitor TV 805, and the like are also installed on the front surface of the chamber 801 so that the same console operation can be performed from the front surface of the chamber 801.

  FIG. 9 shows the internal structure of the apparatus of FIG. In the drawing, a stepper which is a step-and-repeat type exposure apparatus is shown as the semiconductor exposure apparatus 901. The semiconductor exposure apparatus may be another type of exposure apparatus such as a scanner which is a step-and-scan type exposure apparatus.

  In the figure, reference numeral 902 denotes a reticle and 903 denotes a wafer. When the light beam emitted from the light source device 904 illuminates the reticle 902 through the illumination optical system 905, the pattern on the reticle 902 can be transferred to the photosensitive layer on the wafer 903 by the projection lens 906. The reticle 902 is supported by a reticle stage 907 for holding and moving the reticle 902. The wafer 903 is exposed while being vacuum-sucked by the wafer chuck 991. The wafer chuck 991 can be moved in each axial direction by a wafer stage 909.

  Above the reticle 902, a reticle optical system 981 for detecting the amount of positional deviation of the reticle is arranged. An off-axis microscope 982 is disposed adjacent to the projection lens 906 above the wafer stage 909. The main function of the off-axis microscope 982 is to detect the relative position between the internal reference mark and the alignment mark on the wafer 903. Further, a reticle library 920 and a wafer carrier elevator 930 which are peripheral devices are disposed adjacent to these stepper bodies. Necessary reticles and wafers are transferred to the stepper main body by the reticle transfer device 921 and the wafer transfer device 931.

  The chamber 801 mainly includes an air conditioner room 910 that adjusts the temperature of air, a filter box 913 that filters fine foreign matters to form a uniform flow of clean air, and a booth 914 that shuts off the apparatus environment from the outside. . In the chamber 801, the air whose temperature is adjusted by the cooler 915 and the reheat heater 916 in the air conditioner room 910 is supplied into the booth 914 by the blower 917 through the air filter g. The air supplied to the booth 914 is again taken into the air conditioner room 910 from the return port ra and circulates in the chamber 801. Normally, this chamber 801 is not strictly a complete circulation system. That is, in order to keep the inside of the booth 914 at a positive pressure at all times, the air outside the booth 914 that is about 10% of the circulating air amount is introduced from the outside air inlet oa provided in the air conditioner room 910 via the blower. In this way, the chamber 801 makes it possible to keep the ambient temperature in which the apparatus is placed constant and keep the air clean.

  The light source device 904 is provided with an intake port sa and an exhaust port ea in preparation for cooling of the ultra-high pressure mercury lamp and generation of toxic gas at the time of laser abnormality. A part of the air in the booth 914 is forcibly exhausted to the factory equipment via the light source device 904 and through a dedicated exhaust fan provided in the air conditioner room 910. In addition, a chemical adsorption filter cf for removing chemical substances in the air is connected to the outside air introduction port oa and the return port ra of the air conditioner room 910, respectively.

  FIG. 10 is a block diagram showing an electric circuit configuration of the apparatus of FIG. In the figure, reference numeral 1021 denotes a main body CPU built in the EWS main body 806 that controls the entire apparatus, and is composed of a central processing unit such as a microcomputer or a minicomputer. 1022 is a wafer stage driving device, 1023 is an alignment detection system (detection optical system) such as the off-axis microscope 982, 1024 is a reticle stage driving device, and 1025 is an illumination system such as the light source device 904. Reference numeral 1026 denotes a shutter driving device, 1027 denotes a focus detection system (detection optical system), and 1028 denotes a Z driving device. Each of these devices and systems is controlled by the main body CPU 1021.

  Reference numeral 1029 denotes a transfer system such as the reticle transfer device 921 and the wafer transfer device 931. Reference numeral 1030 denotes a console unit having the display 802, the keyboard 804, and the like, and is for giving various commands and parameters relating to the operation of the exposure apparatus to the main body CPU 1021. That is, information is exchanged with an operator. Reference numeral 1031 is a console CPU, and 1032 is an external memory for storing parameters and the like.

The wafer alignment in the semiconductor exposure apparatus having the configuration shown in FIGS. 8 to 10 will be described with reference to FIGS. This wafer alignment is also performed in the same manner as a conventional semiconductor exposure apparatus.
When the wafer 903 is supplied to the semiconductor exposure apparatus 901, first, mechanical pre-alignment is performed in step S01. This is mechanical alignment performed in a mechanical alignment apparatus (not shown) using the outer periphery of the wafer and an orientation flat (orientation flat) or notch provided on the outer periphery of the wafer. FIG. 12 shows an example in which a notch N is provided on the outer periphery of the wafer. The rough position of the wafer 903 is determined by this mechanical pre-alignment. This mechanical alignment accuracy is about 20 μm.

  Next, in step S02, the wafer 903 is mounted on the wafer chuck 991 by the wafer transfer device 931 and supplied to the wafer stage 909. In step S03, pre-alignment is performed. In pre-alignment, detection is performed by setting the magnification of the off-axis microscope 982 to a low magnification under the control of the alignment detection system 1023. Thus, the left and right pre-alignment marks (PAL, PAR) shown in FIG. 12 are detected, the position of the pre-alignment mark is obtained, and the center of the wafer 903 is obtained. The alignment accuracy at this time is about 4 μm.

  Next, global alignment is performed in step S04, and the position of the wafer 903 and the position of the exposure shot are obtained accurately. In the global alignment, the off-axis microscope 982 is set to a high magnification. In this way, a plurality of global alignment marks (FX1 to FX4, FY1 to FY4) on the wafer 903 shown in FIG. 12 are measured at a high magnification, and the deviation of the wafer in the X and Y directions, the rotational component, and the magnification of the shot arrangement Find the ingredients. The accuracy of global alignment is an accuracy of an error of 50 nm or less in today's 256Mbit memory manufacturing machine. When the global alignment is completed, exposure is started in step S05.

  FIG. 1 is a diagram showing a screen for simultaneously displaying mark parameter editing means and mark image display in the apparatus of FIG. 8 according to the mark designing apparatus of the present invention. The screen in FIG. 1 is displayed when the user sets a mark design (mark design). Further, this screen includes a window title display area 110, a parameter input area 120, a mark image display unit 130, and a toolbar 140.

  In FIG. 1, reference numeral 121 denotes a parameter group switching tab for grouping parameters and switching the groups. Reference numeral 122 denotes a parameter group display unit that displays the name of the parameter group, 123 denotes a parameter name display unit, and 124 denotes a parameter value input unit for editing the parameter value. Reference numeral 131 denotes a mark image displaying a mark image corresponding to the parameter. 141 is a save button for saving the edited parameter, 142 is a redo button for the previous editing, 143 is a button for opening and opening a new parameter, and 144 is an end button for finishing editing of the parameter.

  FIG. 2 is a diagram showing an example of a mark design pattern used in the apparatus of FIG. These mark patterns are used in the fine alignment step S04 in FIG. A cross pattern as shown in FIG. 2 (a), a bar shape as shown in FIG. 2 (b), a pattern in which the inside of the rectangle is crushed or sawed, and a bar shape as shown in FIG. A pattern that makes it sticky or sawed. In addition, there are various mark patterns for each process and device used, such as those with a square shape, a diffraction grating, or a Fresnel zone plate.

  FIG. 3 is a flowchart showing processing when mark design editing is executed. The operation at the time of mark design editing will be described with reference to FIGS. When the mark design setting editor is executed on the upper-level operation screen displayed on the display 802, the console CPU 1031 reads an existing mark design or creates a new one using the input unit of the console unit 1030 in step S301.

  Next, in step S302, the screen shown in FIG. 1 is displayed on the display. At this time, a mark image 131 corresponding to the parameter is displayed on the mark image display unit 130. Next, in step S303, the parameter group to be edited is switched by the parameter group switching tab 121 by the input unit of the console unit 1030. Next, in step S304, the parameter to be edited is selected by the input means of the console unit 1030.

  Next, in step S305, the parameter value input unit 124 is edited by the input means of the console unit 1030. As a result, if the parameter value satisfies the constraint condition in step S306, the mark image 131 is updated according to the edited parameter in step S307.

  At this time, in step S308, the operator can confirm that the mark image has the intended shape by confirming the updated mark image 131. If the intended shape is not obtained, the process can be returned to step S305 by the editing redo button 142 or the like, and the editing can be redone. In step S309, when editing is completed, the edited result is saved. In step S310, if the end button 144 is instructed, the mark design setting editor is ended and the screen returns to the upper operation screen. In this way, the parameters can be edited while confirming the display of the mark image.

  As commands for parameter editing, redo, repeat, parameter copy and paste, parameter clear, parameter name and parameter value search, replacement, and the like may be prepared.

  FIG. 4 shows how the effect of editing by the mark parameter editing unit is displayed on the mark image display unit on the screen of FIG. Reference numeral 421 denotes display means for indicating a parameter currently selected for editing, and reference numeral 431 denotes display means for displaying an image on a mark image corresponding to the selected parameter.

  When a parameter to be edited is selected in step S304, the selected parameter is highlighted by being surrounded by a thick frame by the display means 421. Further, the image on the mark image 131 corresponding to the selected parameter is highlighted by being surrounded by a thick frame by the display means 431. In this way, by highlighting the parameter currently being edited on the mark image, the visibility of the parameter editing portion can be improved, contributing to the suppression of the occurrence of human error and the improvement of operability. it can. In addition, as a method for highlighting the above-described differences, not only the above-described method of enclosing with a thick frame, but also numerical values and the like may be displayed with different display colors and fonts. Further, as the correspondence between the parameter and the mark image, the display unit 421 and the display unit 431 may be connected by a line, or the display colors may be aligned.

  The screen of FIG. 5 shows a state where the image is directly manipulated on the mark image 131 and the parameters are edited. 5A is a diagram showing the entire mark design setting editor, FIG. 5B is an enlarged view of the editing portion 503 of the mark image 131 before parameter editing, and FIG. It is the figure which expanded the edit part 503 of the mark image 131. In FIG. 5, 501 is a mouse pointer, 502 is a locus for moving the mouse pointer, and 503 is an editing portion of the mark image 131. Reference numeral 521 denotes a parameter corresponding to the image to be operated, 531 is an image that can be operated on the mark image, and 532 is an auxiliary image representing parameter information and dimensions.

When editing parameters,
(1) In step S304 of FIG. 3, an image 531 that can be operated on the mark image 131 is selected. Then, the corresponding parameter 521 can be selected.
(2) Next, in step S305, the mouse pointer 501 is set to the operable image 531 and the mouse button is kept pressed, and the mouse device is moved along the broken line 502. Then, the parameter value corresponding to the image 531 is edited according to the moving distance of the broken line 502.
(3) Thereafter, in step S306, if the edited parameter value satisfies the constraint condition, the mark image of 531 and / or the parameter value displayed in 521 and / or 532 are changed.

  In this way, by directly manipulating the image on the mark image and editing the parameters, it is possible to increase the recognizability of the parameter editing operation, and to contribute to the suppression of the occurrence of human error and the improvement of operability. . Note that the above-described image operation method for parameter editing is not limited to single parameter editing, and parameters may be grouped and a plurality of parameters may be edited by one operation.

  The screen of FIG. 6 shows a state in which parameter constraint conditions are displayed on the screen by the parameter editing unit and / or the mark image display unit. In the figure, 621 is a character string representing a parameter constraint condition, and 631 is an image representing a parameter constraint condition.

  In step S303 (FIG. 3), the parameter group to be edited is switched by the parameter group switching tab 121. Then, the character string 621 representing the parameter constraint condition and / or the image 631 representing the parameter constraint condition are displayed in the parameter input area 120 and / or the mark image display unit 130. In step S305, the parameter value input unit 124 is edited or the image is directly manipulated on the mark image 131 to edit the parameter. In this case, if the edited parameter value does not satisfy the constraint conditions in step S306, an error is displayed in step S311, and then the process returns to step S305, where editing can be performed again. As a result, editing can be performed while checking the constraint conditions of the parameters. In addition, it is possible to prevent input of values that do not satisfy the constraint conditions during editing. The timing for displaying the above-described constraint conditions may be displayed not only at the time of parameter group selection S303 described above, but also at the time of mark reading S301 or parameter selection S303.

  The screen in FIG. 7 shows a state in which the mark image is displayed as a thumbnail when the mark is saved and read. This screen includes a title display area 710, a mark parameter display area 720, a mark list display area 730, and a tool bar 740. 721 is a mark parameter, 731 is a reduced mark image display, 732 is a mark name, 741 is an open button, 742 is a cancel button, and 743 is a mark name display section for a selected mark.

  When the open button 143 is selected in step S301 in FIG. 3, the screen in FIG. 6 is displayed. At this time, readable mark information is displayed in the mark list display area 730 of FIG. 7 as a mark image reduction display 721, a mark name 722, and a mark parameter 723. Thus, the mark can be opened by selecting the mark to be opened and pressing the open button 731. In step S309, the storage destination mark can be selected by the same operation. At this time, when overwriting an existing mark, a message for calling attention is displayed. As a result, unintentional overwriting of a mark can be prevented.

The alignment mark and the alignment mark editing means of the present invention are not limited to the fine alignment process of the semiconductor exposure apparatus, but can be applied to the pre-alignment process.
Needless to say, the alignment mark and the alignment mark editing means of the present invention can be used not only for semiconductor exposure but also for manufacturing liquid crystal elements and TFT substrates.

[Example of device manufacturing method]
Next, an embodiment of a device manufacturing method using the above-described exposure apparatus will be described with reference to FIGS. FIG. 13 is a flowchart for explaining how to fabricate devices (ie, semiconductor chips such as IC and LSI, LCDs, CCDs, and the like). Here, a semiconductor chip manufacturing method will be described as an example.
In step 1 (circuit design), a semiconductor device circuit is designed. In step 2 (mask production), a mask (also referred to as an original plate or a reticle) is produced based on the designed circuit pattern. In step 3 (wafer manufacture), a wafer (also referred to as a substrate) is manufactured using a material such as silicon. Step 4 (wafer process) is called a pre-process, and an actual circuit is formed on the wafer by using the mask and the wafer by the above-described exposure apparatus using the lithography technique. Step 5 (assembly) is referred to as a post-process, and is a process for forming a semiconductor chip using the wafer produced in step 4, and an assembly process such as an assembly process (dicing, bonding), a packaging process (chip encapsulation), or the like. including. In step 6 (inspection), the semiconductor device manufactured in step 5 undergoes inspections such as an operation confirmation test and a durability test. Through these steps, a semiconductor device is completed and shipped (step 7).

  FIG. 14 is a detailed flowchart of the wafer process in Step 4. In step 11 (oxidation), the surface of the wafer is oxidized. In step 12 (CVD), an insulating film is formed on the surface of the wafer. In step 13 (electrode formation), an electrode is formed on the wafer by vapor deposition. In step 14 (ion implantation), ions are implanted into the wafer. In step 15 (resist process), a photosensitive agent is applied to the wafer. Step 16 (exposure) uses the exposure apparatus to expose a circuit pattern on the mask onto the wafer. In step 17 (development), the exposed wafer is developed. In step 18 (etching), portions other than the developed resist image are removed. In step 19 (resist stripping), the resist that has become unnecessary after the etching is removed. By repeatedly performing these steps, multiple circuit patterns are formed on the wafer.

It is a figure which shows the initial screen which displays simultaneously the mark parameter edit means and the means to display the mark image decided by the parameter based on one Example of this invention. It is a figure which shows the example of the mark design pattern based on one Example of this invention. It is a flowchart which shows the process at the time of performing the mark design edit based on one Example of this invention. It is a figure which shows the screen which displays on the mark image display means the influence of the edit of the mark parameter edit means based on one Example of this invention. It is a figure which shows the screen which operates the image directly on the mark image and edits the parameter based on one Example of this invention. It is a figure which shows the screen which displays the constraint conditions of a parameter on a screen based on one Example of this invention. It is a figure which shows the screen which displays the thumbnail image of the mark image at the time of the preservation | save and reading of the mark based on one Example of this invention. It is a perspective view which shows the external appearance of the semiconductor exposure apparatus which concerns on one Example of this invention. It is a figure which shows the internal structure of the apparatus of FIG. It is a block diagram which shows the electric circuit structure of the apparatus of FIG. It is a flowchart explaining the alignment process sequence in the apparatus of FIG. It is a figure which shows the alignment mark in a common wafer. It is a flowchart for demonstrating manufacture of the device using an exposure apparatus. 14 is a detailed flowchart of a wafer process in the flowchart shown in FIG. 13.

Explanation of symbols

  110: Window title display area, 120: Parameter input area, 121: Parameter group switching tab, 122: Parameter group display section, 123: Parameter name display section, 124: Parameter value input section, 130: Mark image display section, 131: Mark image, 140: Toolbar, 141: Save button, 142: Redo button for editing, 143: Open button, 144: End button, 421: Display means indicating selected parameter, 431: Corresponding to selected parameter Display means for displaying an image on the mark image to be performed, 501: mouse pointer, 502: trajectory for moving the mouse pointer, 531: operable image on the mark image, 532: auxiliary image representing parameter information and dimensions, 621: Parameter Character string representing constraint condition, 631: Image representing parameter constraint condition, 710: Title display area, 720: Mark parameter display area, 721: Mark parameter, 730: Mark list display area, 731: Mark image reduced display, 732 : Mark name, 741: Open button, 742: Cancel button, 743: Mark name display part of selected mark.

Claims (8)

A mark design device for designing a mark formed on a substrate and detected by a position detection device,
An editing means for editing parameters for determining the configuration of the mark;
Image forming means for forming an image of the mark determined by the parameters;
Display means for displaying the element for editing the parameter and the image of the formed mark on a single screen;
A mark design apparatus comprising:   2. The mark design apparatus according to claim 1, wherein an influence of the parameter edited by the editing unit on the image of the mark is displayed on the display unit in an emphasized manner.   3. The mark design apparatus according to claim 1, wherein the editing means includes means for editing a corresponding parameter by directly manipulating an image on the mark image on the display means.   4. The mark designing apparatus according to claim 1, wherein the editing unit displays the parameter constraint condition on the display unit.   5. The mark design apparatus according to claim 1, wherein the editing unit displays the image of the mark on the display unit as a thumbnail when the mark is imported.   6. A position detection system comprising: the mark design device according to claim 1; and a detection optical system that detects the mark on the substrate on which the mark set by the design device is formed. apparatus.   A position detection device according to claim 6 is provided, the substrate is aligned with the original based on the result of position detection by the position detection device, and the pattern formed on the original is placed on the pattern formed on the substrate. An exposure apparatus, wherein the exposure is performed by superimposing on the exposure apparatus.   A device manufacturing method comprising: exposing a substrate using the exposure apparatus according to claim 6; and developing the exposed substrate.

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