JP2008305881A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a semiconductor device capable of improving a breakdown voltage in an off state without increasing an on-resistance and a parasitic capacitance as much as possible.
A semiconductor device of the present invention includes a P-type semiconductor substrate including a P-type semiconductor substrate, an N ⁺ type drain buried layer formed in a predetermined region, and the N ⁺ type drain buried layer. The N ⁻ type epitaxial layer 102 formed above, the N ⁺ type drain extraction region 104 penetrating therethrough and connected to the N ⁺ type drain buried layer 103, and the P formed on the surface of the N ⁻ type epitaxial layer 102 -type base region 105, and a ^{N +} -type source region 106 formed in the P-type base region 105 surface, N ^- -type epitaxial layer 102 surface, N ^- type epitaxial layer 102 and the same conductivity type as in the N ^- type epitaxial An N ⁻⁻ type low concentration region 11 having an impurity concentration lower than that of the layer 102 is provided along the outer periphery of the P type base region 105.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a DMOS (Double Diffused Metal Oxide Semiconductor) transistor.

  An example of a semiconductor device having a conventional DMOS transistor is shown in FIG.

  6A is a plan view of the main part of the MOS cell region, and FIG. 6B is a cross-sectional perspective view taken along line XX of FIG. 6A.

In FIG. 6, 100 is a conventional semiconductor device, 101 is a P-type silicon substrate, 102 is an N ⁻ type epitaxial layer, 103 is an N ⁺ type drain buried layer, 104 is an N ⁺ type drain extraction region, and 105 is a P type base region. , 106 is an N ⁺ type source region, 108 is a gate electrode, 108a is a gate oxide film, 109 is a source electrode, 110 is a drain electrode, 114 is a field oxide film, D is a drain cell, S is a source cell, and H is lateral. Current, V is a longitudinal current.

  As shown in FIG. 6A, the cell region of the conventional semiconductor device 100 is formed in such a manner that the drains D and the source cells S are formed in a lattice shape, and the source cells S are arranged so as to surround the drain cells D. ing.

As shown in FIG. 6B, an N ⁺ type drain buried layer 103 is formed in a predetermined region of the P type silicon substrate 101, and the N ⁻ type epitaxial layer 102 is formed on the P type silicon substrate 101 including the N ⁺ type drain buried layer 103. Is formed.

A P-type base region 105 is formed on the surface of the N ⁻ -type epitaxial layer 102, and an N ⁺ -type source region 106 is formed on the surface of the P-type base region 105.

The N ⁻ type epitaxial layer 102 is formed with an N ⁺ type drain extraction region 104 that penetrates the N ⁻ type epitaxial layer 102 and connects to the N ⁺ type drain buried layer 103.

A field oxide film 114 is formed in a predetermined region on the surface of the N ⁻ type epitaxial layer 102, and a gate electrode 108 is formed in a predetermined region on the P-type base region 105 through a gate oxide film 108 a. Has been.

Further, a source electrode 109 connected to the N ⁺ -type source region 106 is formed, and a drain electrode 110 connected to the source electrode 109 is formed on the N ⁺ -type drain extraction region 104.

  Next, the operation of the semiconductor device 100 will be described with reference to FIG. 6B in the case where a positive voltage is applied to the drain and a negative voltage is applied to the source.

  When a predetermined voltage is applied to the gate electrode 108, the surface of the P-type base region 105 opposed to the gate electrode 108 is inverted to form a channel, and the drain / source is conducted and turned on.

  At this time, two current paths are formed: a horizontal current path and a vertical current path.

The current path in the horizontal direction flows from the drain electrode 110 through the N ⁺ type drain extraction region 104 to the N ⁻ type epitaxial layer 102 in the horizontal direction, and flows into the N ⁺ type source region 106 through the channel. It is. (Indicated by arrow H in the figure)

On the other hand, the vertical current path flows from the drain electrode 110 through the N ⁺ -type drain extraction region 104 and the N ⁺ -type drain buried layer 103 to the N ⁻ -type epitaxial layer 102 in the vertical direction and through the channel, ^This is a current path flowing into the ⁺ type source region 106. (Indicated by arrow V in the figure)

Japanese Patent Laid-Open No. 2001-298183 FIG. 31 and FIG.

  The semiconductor device 100 as described above is required to reduce the on-resistance and to improve the breakdown voltage in the off state.

The on-resistance depended mainly on the impurity concentration of the N ⁻ -type epitaxial layer 102, and the off-breakdown voltage depended on the width of the depletion layer formed at the PN junction formed by the P-type base region 105 and the N ⁻ -type epitaxial layer 102.

  The breakdown voltage in the off state will be described in detail with reference to FIG.

  FIG. 7 is a cross-sectional perspective view and an enlarged cross-sectional view of a main part in which the electrode portion of the semiconductor device 100 is removed, and shows a state where a positive voltage is applied to the drain and a negative voltage is applied to the source in the off state.

As shown in FIG. 7, since a reverse bias is applied to the PN junction formed by the P-type base region 105 and the N ⁻ -type epitaxial layer 102, a depletion layer K1 (shown by a dot region in the figure) is formed. spread.

  However, the depletion layer K1 has a problem that its width decreases near the PN junction near the surface, causing electric field concentration and lowering the withstand voltage.

  The reason why the width of the depletion layer K1 decreases near the PN junction near the surface is that there is actually a fixed charge in the oxide film caused by the manufacturing process in the oxide film, and the oxide film-silicon interface is at the so-called interface state. This is presumably because trapped charges exist, which makes it difficult for the depletion layer to extend.

  For this reason, in order to improve the breakdown voltage, it is necessary to widen the width of the depletion layer K1 near the surface.

In Patent Document 1, in addition to the configuration of FIG. 6, as shown in FIG. 8A, P-type diffusion is formed on the surface of the N ⁻ -type epitaxial layer 102 between the P-type base region 105 and the drain electrode 110. A configuration in which the area 107 is provided is described.

  Further, as shown in FIG. 8B, a configuration is described in which a plurality of P-type diffusion regions 107a are discretely arranged so that adjacent depletion layers are connected to each other.

However, when such P type diffusion regions 107 and 107a are provided, a PN junction is formed between the N ⁻ type epitaxial layer 102 and a depletion layer K3 (indicated by a dot region in the figure) is generated. The path area of the current flowing in the lateral direction is narrowed by the layer K3, or the current path length is increased to bypass the depletion layer.

  As a result, the on-resistance is greatly increased and unnecessary parasitic capacitance is generated.

  An object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage in the off state without increasing the on-resistance and the parasitic capacitance as much as possible.

The semiconductor device of the present invention is
A semiconductor substrate;
A first conductivity type drain buried layer formed in a predetermined region of the semiconductor substrate;
An epitaxial layer of a first conductivity type formed on a semiconductor substrate including a drain buried layer;
A drain extraction region of a first conductivity type penetrating the epitaxial layer and connected to the drain buried layer;
A base region of a second conductivity type formed in a predetermined region on the surface of the epitaxial layer;
In a semiconductor device comprising a first conductivity type source region formed in a predetermined region of the base region surface,
A semiconductor device characterized in that a low concentration region having the same conductivity type as the epitaxial layer and having an impurity concentration lower than that of the epitaxial layer is provided on the surface of the epitaxial layer along the outer periphery of the base region.

  According to the semiconductor device of the present invention, the breakdown voltage in the off state can be improved without increasing the on-resistance and the parasitic capacitance as much as possible.

  An object of the present invention is to provide a semiconductor device capable of improving a breakdown voltage in an off state without increasing an on-resistance and a parasitic capacitance as much as possible. This is realized by providing a low concentration region with a lower impurity concentration along the outer periphery of the base region and increasing the width of the depletion layer near the surface.

  An example of a semiconductor device provided with the DMOS transistor of the present invention is shown in FIG.

  FIG. 1A is a plan view of a principal part of a MOS cell region, and FIG. 1B is a cross-sectional perspective view taken along line XX of FIG. The same parts as those in FIGS.

In FIG. 1, 10 is a semiconductor device of the present invention, 11 is an N ⁻⁻ type low concentration region, 101 is a P type silicon substrate, 102 is an N ⁻ type epitaxial layer, 103 is an N ⁺ type drain buried layer, and 104 is N ^+. Type drain extraction region, 105 is a P type base region, 106 is an N ⁺ type source region, 108 is a gate electrode, 108a is a gate oxide film, 109 is a source electrode, 110 is a drain electrode, 114 is a field oxide film, D is a drain A cell, S is a source cell, H is a horizontal current, and V is a vertical current.

  In the cell region of the semiconductor device 10 of the present invention, as shown in FIG. 1A, the drain D and the source cell S are formed in a lattice shape, and the source cell S is arranged so as to surround the drain cell D. It has become.

Further, as shown in FIG. 1B, an N ⁺ type drain buried layer 103 is formed in a predetermined region of the P type silicon substrate 101, and an N ⁻ type epitaxial layer 102 is formed on the P type silicon substrate 101 including the N ⁺ type drain buried layer 103. Is formed.

A P-type base region 105 is formed on the surface of the N ⁻ -type epitaxial layer 102, and an N ⁺ -type source region 106 is formed on the surface of the P-type base region 105.

The N ⁻ type epitaxial layer 102 is formed with an N ⁺ type drain extraction region 104 that penetrates the N ⁻ type epitaxial layer 102 and connects to the N ⁺ type drain buried layer 103.

A field oxide film 114 is formed in a predetermined region on the surface of the N ⁻ type epitaxial layer 102, and a gate electrode 108 is formed in a predetermined region on the P-type base region 105 through a gate oxide film 108 a. Has been.

Further, a source electrode 109 connected to the N ⁺ -type source region 106 is formed, and a drain electrode 110 connected to the source electrode 109 is formed on the N ⁺ -type drain extraction region 104.

The N ⁻ type low concentration region 11 having the same conductivity type as the N ⁻ type epitaxial layer 102 and having a lower impurity concentration than the N ⁻ type epitaxial layer 102 is formed on the surface of the N ⁻ type epitaxial layer 102. It is provided along the outer periphery.

That is, the N ⁻⁻ type low concentration region 11 is formed so as to surround the P type base region 105 in a plan view.

Further, the depth of the N ⁻⁻ type low concentration region 11 is formed to be shallower than the depth of the P type base region 105.

Further, the width of the N ⁻⁻ type low concentration region 11 is formed to be smaller than ½ of the distance between the P type base region 105 and the N ⁺ type drain extraction region 104.

  Next, the operation of the semiconductor device 10 will be described with reference to FIG. 1B when a positive voltage is applied to the drain and a negative voltage is applied to the source.

  When a predetermined voltage is applied to the gate electrode 108, the surface of the P-type base region 105 opposed to the gate electrode 108 is inverted to form a channel, and the drain / source is conducted and turned on.

  At this time, two current paths are formed: a horizontal current path and a vertical current path.

The current path in the horizontal direction flows from the drain electrode 110 through the N ⁺ type drain extraction region 104 to the N ⁻ type epitaxial layer 102 in the horizontal direction, and flows into the N ⁺ type source region 106 through the channel. It is. (Indicated by arrow H in the figure)

On the other hand, the vertical current path flows from the drain electrode 110 through the N ⁺ -type drain extraction region 104 and the N ⁺ -type drain buried layer 103 to the N ⁻ -type epitaxial layer 102 in the vertical direction and through the channel, ^This is a current path flowing into the ⁺ type source region 106. (Indicated by arrow V in the figure)

  Next, the breakdown voltage in the off state will be described in detail with reference to FIG.

  FIG. 2 is a cross-sectional perspective view and an enlarged cross-sectional view of the main part from which the electrode portion of the semiconductor device 10 is removed, and shows a state where a positive voltage is applied to the drain and a negative voltage is applied to the source in the off state.

As shown in FIG. 2, since a reverse bias is applied to the PN junction formed by the P-type base region 105 and the N ⁻ -type epitaxial layer 102, a depletion layer K2 (shown by a dot region in the figure) is formed. spread.

Here, the depletion layer K2 is, N ^- due to the presence of type low concentration region ^{11, N - - N} lower impurity concentration than -type epitaxial layer 102 to the depletion layer K1 when not provided type low concentration region 11 In comparison, the shape is pushed outward near the surface, the width of the depletion layer is increased, and the breakdown voltage is improved.

Since the N ⁻⁻ type low concentration region 11 has the same conductivity type as that of the N ⁻ type epitaxial layer 102, no PN junction portion is formed and no depletion layer is formed between the two.

  For this reason, the path area of the lateral current is not narrowed by the depletion layer, and the current path length is not increased due to detouring of the depletion layer, greatly increasing the on-resistance and generating unnecessary parasitic capacitance. There is nothing.

Further, the depth of the N ⁻⁻ type low concentration region 11 is formed to be shallower than the depth of the P type base region 105, or the width of the N ⁻⁻ type low concentration region 11 is set to the P type base region 105 and the N ⁺ type drain extraction region. By forming the distance to be smaller than ½ of the distance to 104, an increase in on-resistance can be suppressed.

  Next, an example of a method for manufacturing the semiconductor device 10 as described above will be described with reference to FIGS.

  3 to 5 are cross-sectional views of the main part of the device at the completion of each manufacturing process.

First, as shown in FIG. 3A, antimony, which is an N-type impurity, is ion-implanted into a predetermined region of a P-type silicon substrate 101 to perform heat treatment, and an N ⁻ -type epitaxial layer 102 is formed by an epitaxial growth method. An N ⁺ type drain buried layer 103 is formed.

Next, as shown in FIG. 3 (b), by photolithography to form a resist mask having a predetermined pattern (not shown), and it masks boron is implanted a P-type impurity, N ^- -type epitaxial The N ⁻⁻ type low concentration region 11 is formed by canceling out the N type impurities in the layer 102.

  Next, as shown in FIG. 4C, a field oxide film 114 is formed in a predetermined region.

  Thereafter, as shown in FIG. 4D, a gate oxide film 108a and a gate electrode 108 are formed, a resist mask (not shown) having a predetermined pattern is formed, and boron, which is a P-type impurity, is implanted to form a P-type impurity. A base layer 105 is formed.

Next, as shown in FIG. 5E, a resist mask (not shown) having a predetermined pattern is formed, arsenic as an N-type impurity is implanted, and an N ⁺ -type source region 106 is formed on the surface of the P-type base layer 105. Form.

  Thereafter, as shown in FIG. 5F, a source electrode 109 and a drain electrode 110 are formed.

  In the above example, the drain cell D and the source cell S are arranged in a lattice pattern, and the source cell S is disposed so as to surround the drain cell D. However, the present invention is not limited to this.

  Further, the thick field oxide film 114 is formed between the source / drain, but a configuration without the field oxide film 114 may be used.

  That is, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

  The present invention can be applied to a semiconductor device capable of improving the breakdown voltage in the off state without increasing the on-resistance and parasitic capacitance as much as possible.

The principal part top view and principal part cross-section perspective view of the cell area | region of the semiconductor device of this invention The cross-sectional perspective view and principal part expanded sectional view which removed the electrode part of the semiconductor device of this invention Sectional drawing of the principal part of the device for each manufacturing process completion of the semiconductor device of the present invention Sectional drawing of the principal part of the device for each manufacturing process completion of the semiconductor device of the present invention Sectional drawing of the principal part of the device for each manufacturing process completion of the semiconductor device of the present invention Plan view and cross-sectional perspective view of the main part of a cell region of a conventional semiconductor device Cross-sectional perspective view and main-part cross-sectional perspective view of the conventional semiconductor device with the electrode portion removed Cross-sectional perspective view of the main part of another conventional semiconductor device

Explanation of symbols

10 semiconductor device of the present invention 11 N ^- -type low concentration region 100 conventional semiconductor device 101 P-type silicon substrate 102 N ^- -type epitaxial layer 103 N ⁺ -type drain buried layer 104 N ⁺ -type drain extraction region 105 P-type base region 106 N ⁺ -type source region 107, 107a P-type diffusion region 108 Gate electrode 108a Gate oxide film 109 Source electrode 110 Drain electrode 114 Field oxide film D Drain cell H Lateral current K1, K2, K3 Depletion layer S Source cell V Vertical current

Claims (4)

A semiconductor substrate;
A drain buried layer of a first conductivity type formed in a predetermined region of the semiconductor substrate;
An epitaxial layer of a first conductivity type formed on the semiconductor substrate including the drain buried layer;
A drain extraction region of a first conductivity type penetrating the epitaxial layer and connected to the drain buried layer;
A base region of a second conductivity type formed in a predetermined region on the surface of the epitaxial layer;
In a semiconductor device comprising a source region of a first conductivity type formed in a predetermined region on the surface of the base region,
A semiconductor device characterized in that a low concentration region having the same conductivity type as the epitaxial layer and having an impurity concentration lower than that of the epitaxial layer is provided along the outer periphery of the base region on the surface of the epitaxial layer.   2. The semiconductor device according to claim 1, wherein the low concentration region is provided so as to circumscribe the base region.   The semiconductor device according to claim 1, wherein a depth of the low concentration region is formed shallower than a depth of the base region.   4. The semiconductor device according to claim 1, wherein a width of the low concentration region is smaller than a half of a distance between the base region and the drain extraction region.

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