CN106057905A - Trench gate field effect transistor and manufacturing method - Google Patents

Abstract

The invention discloses a trench gate field effect transistor, and the field effect transistor comprises a drift region and a body region. A trench passes through the body region to enter the drift region. A gate medium layer and a polysilicon gate are formed in the trench. A reverse doped layer is formed at a part, at the bottom of the trench, of the drift region, and is formed by the overlapping of a second conductive type foreign matter and a first conductive type foreign matter. The second conductive type foreign matter is formed through vertical ion implantation after the forming of the trench and before the forming of the gate medium layer and the polysilicon gate, and the reverse doped layer is enabled to be located at the bottom of the trench in a self-aligned manner. The reverse doped layer is used for reducing the electric field intensity of the part, located at the bottom of the trench, of the drift region, and can increase the breakdown voltage of a device under the conditions that the doping density of the drift region is not reduced and the thickness of the drift region is not increased. The invention also discloses a manufacturing method for the trench gate field effect transistor. The trench gate field effect transistor can increase the breakdown voltage of the device, and does not sacrifice other performances of the device.

Description

Trench gate field effect transistor and manufacturing method

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench gate field effect transistor. The invention also relates to a manufacturing method of the trench gate field effect transistor.

Background technique

Compared with planar field effect transistors, trench gate field effect transistors have the advantages of high device density and high driving current. As shown in Figure 1, it is a schematic structural diagram of an existing trench gate field effect transistor; taking an N-type device as an example, the existing trench gate field effect transistor includes:

An N-type drift region 101 and a P-type body region 102, the body region 102 is located on the surface of the drift region 101; the drift region 101 is formed on the surface of the semiconductor substrate.

A trench, the trench passes through the body region 102 and enters into the drift region 101 .

A gate dielectric layer 103 is formed on the inner surface of the trench, and the trench is filled with a polysilicon gate 104; the surface of the body region 102 covered by the polysilicon gate 104 is used to form a channel.

A source region 105 composed of an N-type heavily doped region is formed on the surface of the body region 102 .

An N-type heavily doped drain region 106 is formed on the back of the drift region 101 , and the drain region 106 can be formed by thinning the back of the semiconductor substrate and performing back implantation.

The source and the gate formed by patterning the front metal layer, the gate is connected to the polysilicon gate 104 through the contact hole, the source region 105 and the body region 102 are connected to the polysilicon gate 104 through the contact hole at the top source.

The back metal layer, the back metal layer is in contact with the drain region 106 and serves as the drain.

In the existing structure, the drift region 101 at the bottom of the trench is the most concentrated region of electric lines in the entire drift region 101 , and it is also the place where breakdown is most likely to occur.

Due to the lower breakdown voltage of the drift region 101 at the bottom of the trench, the device has to use a lower doping concentration of the drift region 101 and a thicker drift region 101 to achieve the target breakdown voltage of the device. But this will sacrifice performance such as device on-resistance.

Contents of the invention

The technical problem to be solved by the present invention is to provide a trench gate field effect transistor, which can increase the breakdown voltage of the device without sacrificing other performances of the device. Therefore, the present invention also provides a manufacturing method of the trench gate field effect transistor.

In order to solve the above technical problems, the present invention provides a trench gate field effect transistor comprising:

A drift region of the first conductivity type and a body region of the second conductivity type, the body region is located on the surface of the drift region; the drift region is formed on the surface of the semiconductor substrate.

A trench passes through the body region and into the drift region.

A gate dielectric layer is formed on the inner surface of the trench, and the trench is filled with a polysilicon gate; the surface of the body region covered by the side of the polysilicon gate is used to form a channel.

A counter-doped layer is formed in the drift region at the bottom of the trench, and the counter-doped layer is formed by overlapping impurities of the second conductivity type and impurities of the first conductivity type in the drift region, the second Conductive impurity is formed by vertical ion implantation after the trench is formed and before the gate dielectric layer and the polysilicon gate are formed in the trench and makes the anti-doping layer self-aligned in the trench The bottom of the trench, the anti-doping layer is used to reduce the electric field intensity of the drift region at the bottom of the trench, and can improve the device without reducing the doping concentration of the drift region and increasing the thickness of the drift region. the breakdown voltage.

A further improvement is that the concentration of impurities of the second conductivity type is less than or equal to the concentration of impurities of the first conductivity type in the drift region, the net doping type of the counter-doping layer is the first conductivity type and the counter-doping layer The doping concentration of the first conductivity type of the impurity layer is lower than the doping concentration of the first conductivity type of the drift region.

Alternatively, the concentration of impurities of the second conductivity type is greater than the concentration of impurities of the first conductivity type in the drift region, the net doping type of the counter-doped layer is the second conductivity type, and the counter-doped layer and the adjacent A PN junction is formed between the drift regions.

A further improvement is that the counter-doped layer is in contact with the bottom surface of the trench and extends upward, and the upwardly extending portion of the counter-doped layer is in contact with the side surface of the trench.

Alternatively, the counter-doped layer is located at the bottom of and not in contact with the bottom surface of the trench.

A further improvement is that a source region composed of a heavily doped region of the first conductivity type is formed on the surface of the body region; a heavily doped drain region of the first conductivity type is formed on the back of the drift region.

A further improvement is to also include:

A source and a gate formed by patterning the front metal layer, the gate is connected to the polysilicon gate through a contact hole, and the source region and the body region are connected to the source through the contact hole at the top .

a back metal layer, the back metal layer is in contact with the drain region and serves as a drain.

A further improvement is that the semiconductor substrate is a silicon substrate.

A further improvement is that the gate dielectric layer is an oxide layer.

A further improvement is that the trench gate field effect transistor is an N-type device, the first conductivity type is N type, and the second conductivity type is P type; or, the trench gate field effect transistor is a P type device, the first The first conductivity type is P type, and the second conductivity type is N type.

In order to solve the above-mentioned technical problems, the manufacturing method of the trench gate field effect transistor provided by the present invention comprises the following steps:

Step 1, forming a drift region of the first conductivity type on the surface of the semiconductor substrate.

Step 2, forming a hard mask layer on the surface of the semiconductor substrate where the drift region is formed.

Step 3: Define the formation area of the trench by photolithography, remove the hard mask layer in the formation area of the trench, and keep the hard mask layer outside the formation area of the trench.

Step 4, using the hard mask layer as a mask to etch the semiconductor substrate to form the trench, the trench is located in the drift region and the depth of the trench is greater than that formed subsequently The depth of the body area.

Step 5, using the hard mask layer as a mask to perform vertical ion implantation of the second conductivity type, the vertical ion implantation self-alignedly implants impurities of the second conductivity type in the drift region at the bottom of the trench , an anti-doping layer is formed by overlapping the impurities of the second conductivity type and the impurities of the first conductivity type in the drift region, and the anti-doping layer is used to reduce the electric field intensity of the drift region at the bottom of the trench, and can be used in The breakdown voltage of the device is improved without reducing the doping concentration of the drift region and increasing the thickness of the drift region.

Step 6, removing the hard mask layer.

Step 7, forming a gate dielectric layer on the inner surface of the trench, and filling the trench with a polysilicon gate;

Step 8, forming a body region of the second conductivity type on the surface of the drift region; the surface of the body region covered by the side surface of the polysilicon gate is used to form a channel.

A further improvement is that the concentration of impurities of the second conductivity type is less than or equal to the concentration of impurities of the first conductivity type in the drift region, the net doping type of the counter-doping layer is the first conductivity type and the counter-doping layer The doping concentration of the first conductivity type of the impurity layer is lower than the doping concentration of the first conductivity type of the drift region.

Alternatively, the concentration of impurities of the second conductivity type is greater than the concentration of impurities of the first conductivity type in the drift region, the net doping type of the counter-doped layer is the second conductivity type, and the counter-doped layer and the adjacent A PN junction is formed between the drift regions.

A further improvement is that the counter-doped layer is in contact with the bottom surface of the trench and extends upward, and the upwardly extending portion of the counter-doped layer is in contact with the side surface of the trench.

Alternatively, the counter-doped layer is located at the bottom of and not in contact with the bottom surface of the trench.

A further improvement is to also include the steps:

Step 9, forming a source region composed of a heavily doped region of the first conductivity type on the surface of the body region.

Step 10: Thinning the back of the semiconductor substrate and performing back ion implantation to form a heavily doped drain region of the first conductivity type on the back of the drift region.

A further improvement is to also include:

After step nine and before step ten, the following front processes are also included:

Form an interlayer film on the front surface of the semiconductor substrate, form a contact hole through the interlayer film, form a front metal layer and form a source electrode and a gate electrode, and the gate electrode passes through the contact hole and the polysilicon gate connection, the source region and the body region are connected to the source through the contact hole at the top.

After step ten, the following backside processes are also included:

A back metal layer is formed, the back metal layer is in contact with the drain region and serves as a drain.

A further improvement is that in step seven, a thermal oxidation process is used to form the gate dielectric layer on the inner surface of the trench.

A further improvement is that the hard mask layer is formed by stacking silicon oxide and silicon nitride.

In the present invention, by forming a counter-doped layer in the drift region at the bottom of the trench, the impurities of the second conductivity type in the counter-doped layer can reduce the net impurities of the first conductivity type in the counter-doped layer or directly convert them into the second conductivity type The structure of the net impurities can reduce the electric field intensity of the drift region at the bottom of the trench, thereby increasing the breakdown voltage of the device.

In addition, the second conductivity type impurity of the anti-doping layer of the present invention is formed by vertical ion implantation before the gate dielectric layer and the polysilicon gate are formed through the trench formation, and the anti-doping layer and the trench have a self-aligned relationship, so The anti-doping layer can be accurately positioned at the bottom of the trench, so that it will not affect the doping of the drift region in other regions, so the present invention can be achieved without changing the process conditions of the drift region, such as doping concentration and thickness. The breakdown voltage of the device is improved; and because the invention improves the breakdown voltage of the device without changing the process conditions of the drift region, other properties of the device such as on-resistance can be maintained.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

FIG. 1 is a schematic structural view of an existing trench gate field effect transistor;

2 is a schematic structural view of a trench gate field effect transistor according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a trench gate field effect transistor according to Embodiment 2 of the present invention;

FIG. 4 is a schematic diagram of a device structure in a manufacturing method of a trench gate field effect transistor according to an embodiment of the present invention.

detailed description

As shown in Figure 2, it is a schematic structural diagram of a trench gate field effect transistor according to an embodiment of the present invention; a trench gate field effect transistor according to an embodiment of the present invention includes:

A drift region 1 of the first conductivity type and a body region 2 of the second conductivity type, the body region 2 is located on the surface of the drift region 1; the drift region 1 is formed on the surface of the semiconductor substrate. Preferably, the semiconductor substrate is a silicon substrate.

A trench passes through the body region 2 and enters the drift region 1 .

A gate dielectric layer 3 is formed on the inner surface of the trench, and the trench is filled with a polysilicon gate 4; the surface of the body region 2 covered by the side of the polysilicon gate 4 is used to form a channel. Preferably, the gate dielectric layer 3 is an oxide layer.

An anti-doping layer 7a is formed in the drift region 1 at the bottom of the trench, and the anti-doping layer 7a is formed by overlapping the impurities of the second conductivity type and the impurities of the first conductivity type in the drift region 1, The impurity of the second conductivity type is formed by vertical ion implantation after the trench is formed and before the gate dielectric layer 3 and the polysilicon gate 4 are formed in the trench and makes the anti-doped layer 7a Self-alignment is located at the bottom of the trench, and the anti-doping layer 7a is used to reduce the electric field intensity of the drift region 1 at the bottom of the trench, without reducing the doping concentration of the drift region 1 and increasing the The breakdown voltage of the device is improved under the condition of the thickness of the drift region 1 mentioned above.

In Embodiment 1 of the present invention, the concentration of impurities of the second conductivity type is greater than the concentration of impurities of the first conductivity type in the drift region 1, and the net doping type of the counter-doped layer 7a is the second conductivity type, so A PN junction is formed between the counter-doped layer 7a and the adjacent drift region 1 . In other embodiments, it can also be: the concentration of impurities of the second conductivity type is less than or equal to the concentration of impurities of the first conductivity type in the drift region 1, and the net doping type of the counter-doped layer 7a is the first conductivity type and the doping concentration of the first conductivity type of the counter-doped layer 7 a is lower than the doping concentration of the first conductivity type of the drift region 1 .

The anti-doping layer 7a is in contact with the bottom surface of the trench and extends upward, and the upwardly extending portion of the anti-doping layer 7a is in contact with the side surface of the trench. It can be known from FIG. 2 that the PN junction formed between the anti-doped layer 7 a and the drift region 1 is in a ring structure and surrounds the bottom of the trench.

A source region 5 composed of a heavily doped region of the first conductivity type is formed on the surface of the body region 2 ; and a drain region 6 of the first conductivity type heavily doped is formed on the back of the drift region 1 .

Also includes:

The source and the gate are formed by patterning the front metal layer, the gate is connected to the polysilicon gate 4 through a contact hole, and the source region 5 and the body region 2 are connected to the polysilicon gate 4 through the contact hole at the top. source.

The back metal layer, the back metal layer is in contact with the drain region 6 and serves as the drain.

In Embodiment 1 of the present invention, the trench gate field effect transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; the impurity of the second conductivity type in the counter-doped layer 7a can For boron, indium etc. In other embodiments, it can also be: the trench gate field effect transistor is a P-type device, the first conductivity type is P-type, the second conductivity type is N-type, and the second conductivity type of the counter-doped layer 7a Type impurities can be arsenic, phosphorus, antimony, etc.

As shown in FIG. 3 , it is a schematic structural diagram of the trench gate field effect transistor of the second embodiment of the present invention; the difference between the trench gate field effect transistor of the second embodiment of the present invention and the trench gate field effect transistor of the first embodiment of the present invention is that , the counter-doped layer 7b in Embodiment 2 of the present invention is located at the bottom of the bottom surface of the trench and does not contact it.

As shown in FIG. 4 , it is a schematic view of the device structure in a method for manufacturing a trench 203 gate field effect transistor according to an embodiment of the present invention. The method for manufacturing a trench 203 gate field effect transistor according to an embodiment of the present invention includes the following steps:

Step 1, forming a drift region 1 of the first conductivity type on the surface of the semiconductor substrate.

Step 2, forming a hard mask layer on the surface of the semiconductor substrate where the drift region 1 is formed. Preferably, the hard mask layer is formed by stacking silicon oxide 201 and silicon nitride 202 .

Step 3, define the formation area of the trench 203 by photolithography, remove the hard mask layer in the formation area of the trench 203, and keep the hard mask layer outside the formation area of the trench 203 .

Step 4, using the hard mask layer as a mask to etch the semiconductor substrate to form the trench 203, the trench 203 is located in the drift region 1 and the depth of the trench 203 is greater than the depth of the subsequently formed body region 2 .

Step 5, using the hard mask layer as a mask to perform vertical ion implantation of the second conductivity type, the vertical ion implantation self-aligned implantation of the second conductivity type in the drift region 1 at the bottom of the trench 203 Type impurity 204. After annealing the second conductivity type impurity 204, an anti-doped layer 7a is formed by overlapping the second conductivity type impurity 204 and the first conductivity type impurity in the drift region 1 as shown in FIG. The anti-doping layer 7a is used to reduce the electric field intensity of the drift region 1 at the bottom of the trench 203, and can improve the device performance without reducing the doping concentration of the drift region 1 and increasing the thickness of the drift region 1. breakdown voltage.

In the method of Embodiment 1 of the present invention, the concentration of the impurity of the second conductivity type 204 is greater than the concentration of the impurity of the first conductivity type in the drift region 1, and the net doping type of the counter-doped layer 7a is the second conductivity type , a PN junction is formed between the counter-doped layer 7a and the adjacent drift region 1 . In other embodiments, the method can also be: the concentration of the impurity of the second conductivity type 204 is less than or equal to the concentration of the impurity of the first conductivity type in the drift region 1, and the net doping type of the counter-doped layer 7a is the second One conductivity type and the first conductivity type doping concentration of the counter-doped layer 7 a is lower than the first conductivity type doping concentration of the drift region 1 .

As shown in FIG. 2 , the counter-doped layer 7 a is in contact with the bottom surface of the trench 203 and extends upward, and the upwardly extending portion of the counter-doped layer 7 a is in contact with the side surface of the trench 203 . In other embodiments, the method can also be: as shown in FIG. 3 , the anti-doping layer 7 b is located at the bottom of the bottom surface of the trench 203 without contacting it.

Step 6, removing the hard mask layer.

Step 7, as shown in FIG. 2 , forming a gate dielectric layer 3 on the inner surface of the trench 203 , and filling the trench 203 with a polysilicon gate 4 . Preferably, the gate dielectric layer 3 is formed on the inner surface of the trench 203 by a thermal oxidation process.

Step 8. As shown in FIG. 2 , a body region 2 of the second conductivity type is formed on the surface of the drift region 1 ; the surface of the body region 2 covered by the side of the polysilicon gate 4 is used to form a channel.

As shown in Figure 2, the steps are also included:

Step 9, forming a source region 5 composed of a heavily doped region of the first conductivity type on the surface of the body region 2 .

Form an interlayer film on the front surface of the semiconductor substrate, form a contact hole through the interlayer film, form a front metal layer and form a source electrode and a gate electrode, and the gate electrode passes through the contact hole and the polysilicon gate 4, the source region 5 and the body region 2 are connected to the source through the contact hole at the top.

Step 10: Thinning the back of the semiconductor substrate and performing back ion implantation to form a heavily doped drain region 6 of the first conductivity type on the back of the drift region 1 .

A back metal layer is formed, the back metal layer is in contact with the drain region 6 and serves as a drain.

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (17)

1. A trench gate field effect transistor, characterized in that, comprising: A drift region of the first conductivity type and a body region of the second conductivity type, the body region is located on the surface of the drift region; the drift region is formed on the surface of the semiconductor substrate; a trench passing through the body region and into the drift region; A gate dielectric layer is formed on the inner surface of the trench, and the trench is filled with a polysilicon gate; the surface of the body region covered by the side of the polysilicon gate is used to form a channel; A counter-doped layer is formed in the drift region at the bottom of the trench, and the counter-doped layer is formed by overlapping impurities of the second conductivity type and impurities of the first conductivity type in the drift region, the second Conductive impurity is formed by vertical ion implantation after the trench is formed and before the gate dielectric layer and the polysilicon gate are formed in the trench and makes the anti-doping layer self-aligned in the trench The bottom of the trench, the anti-doping layer is used to reduce the electric field intensity of the drift region at the bottom of the trench, and can improve the device without reducing the doping concentration of the drift region and increasing the thickness of the drift region. the breakdown voltage. 2. Trench gate field effect transistor as claimed in claim 1, is characterized in that: The concentration of impurities of the second conductivity type is less than or equal to the concentration of impurities of the first conductivity type in the drift region, the net doping type of the counter-doped layer is the first conductivity type and the first conductivity type of the counter-doped layer is the doping concentration of the conductivity type is lower than the doping concentration of the first conductivity type in the drift region; Alternatively, the concentration of impurities of the second conductivity type is greater than the concentration of impurities of the first conductivity type in the drift region, the net doping type of the counter-doped layer is the second conductivity type, and the counter-doped layer and the adjacent A PN junction is formed between the drift regions. 3. The Trench Gate Field Effect Transistor according to claim 2, characterized in that: the anti-doped layer is in contact with the bottom surface of the trench and extends upward, and the upwardly extending part of the anti-doped layer is in contact with the sides of the trench are in contact; Alternatively, the counter-doped layer is located at the bottom of and not in contact with the bottom surface of the trench. 4. The trench gate field effect transistor according to claim 1, characterized in that: a source region composed of a heavily doped region of the first conductivity type is formed on the surface of the body region; A heavily doped drain region of the first conductivity type is formed on the back of the drift region. 5. The Trench Gate Field Effect Transistor as claimed in claim 4, further comprising: A source and a gate formed by patterning the front metal layer, the gate is connected to the polysilicon gate through a contact hole, and the source region and the body region are connected to the source through the contact hole at the top ; a back metal layer, the back metal layer is in contact with the drain region and serves as a drain. 6. The trench gate field effect transistor according to claim 1, wherein the semiconductor substrate is a silicon substrate. 7. The trench gate field effect transistor according to claim 1, wherein the gate dielectric layer is an oxide layer. 8. The Trench Gate Field Effect Transistor according to any one of claims 1-7, wherein the Trench Gate Field Effect Transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is N-type. The conductivity type is P-type; or, the Trench Gate Field Effect Transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. 9. A method for manufacturing a trench gate field effect transistor, comprising the steps of: Step 1, forming a drift region of the first conductivity type on the surface of the semiconductor substrate; Step 2, forming a hard mask layer on the surface of the semiconductor substrate where the drift region is formed; Step 3, defining the formation area of the trench by photolithography, removing the hard mask layer in the formation area of the trench, and retaining the hard mask layer outside the formation area of the trench; Step 4, using the hard mask layer as a mask to etch the semiconductor substrate to form the trench, the trench is located in the drift region and the depth of the trench is greater than that formed subsequently the depth of the body region; Step 5, using the hard mask layer as a mask to perform vertical ion implantation of the second conductivity type, the vertical ion implantation self-alignedly implants impurities of the second conductivity type in the drift region at the bottom of the trench , an anti-doping layer is formed by overlapping the impurities of the second conductivity type and the impurities of the first conductivity type in the drift region, and the anti-doping layer is used to reduce the electric field intensity of the drift region at the bottom of the trench, and can be used in improving the breakdown voltage of the device without reducing the doping concentration of the drift region and increasing the thickness of the drift region; Step 6, removing the hard mask layer; Step 7, forming a gate dielectric layer on the inner surface of the trench, and filling the trench with a polysilicon gate; Step 8, forming a body region of the second conductivity type on the surface of the drift region; the surface of the body region covered by the side surface of the polysilicon gate is used to form a channel. 10. The manufacturing method of Trench Gate Field Effect Transistor as claimed in claim 9, is characterized in that: The concentration of impurities of the second conductivity type is less than or equal to the concentration of impurities of the first conductivity type in the drift region, the net doping type of the counter-doped layer is the first conductivity type and the first conductivity type of the counter-doped layer is the doping concentration of the conductivity type is lower than the doping concentration of the first conductivity type in the drift region; Alternatively, the concentration of impurities of the second conductivity type is greater than the concentration of impurities of the first conductivity type in the drift region, the net doping type of the counter-doped layer is the second conductivity type, and the counter-doped layer and the adjacent A PN junction is formed between the drift regions. 11. The manufacturing method of trench gate field effect transistor as claimed in claim 9, characterized in that: the anti-doped layer is in contact with the bottom surface of the trench and extends upward, and the upward of the anti-doped layer the extension part is in contact with the side of the groove; Alternatively, the counter-doped layer is located at the bottom of and not in contact with the bottom surface of the trench. 12. The manufacturing method of trench gate field effect transistor as claimed in claim 9, is characterized in that, also comprises the step: Step 9, forming a source region composed of a heavily doped region of the first conductivity type on the surface of the body region; Step 10: Thinning the back of the semiconductor substrate and performing back ion implantation to form a heavily doped drain region of the first conductivity type on the back of the drift region. 13. The method for manufacturing a Trench Gate Field Effect Transistor as claimed in claim 12, further comprising: After step nine and before step ten, the following front processes are also included: An interlayer film is formed on the front side of the semiconductor substrate, a contact hole passing through the interlayer film is formed, a front metal layer is formed and a source and a gate are formed, and the gate passes through the contact hole and the polysilicon gate connection, the source region and the body region are connected to the source through the contact hole at the top; After step ten, the following backside process is also included: A back metal layer is formed, the back metal layer is in contact with the drain region and serves as a drain. 14. The method for manufacturing a trench gate field effect transistor according to claim 9, wherein the semiconductor substrate is a silicon substrate. 15 . The method for manufacturing a trench gate field effect transistor according to claim 9 , wherein in step seven, a thermal oxidation process is used to form the gate dielectric layer on the inner surface of the trench. 16. The method for manufacturing a trench gate field effect transistor according to claim 9, wherein the hard mask layer is formed by stacking silicon oxide and silicon nitride. 17. The manufacturing method of the Trench Gate Field Effect Transistor according to any one of claims 0-16, characterized in that: the Trench Gate Field Effect Transistor is an N-type device, and the first conductivity type is N-type , the second conductivity type is P-type; or, the Trench Gate Field Effect Transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.