CN1316573C - Method for producing semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, which comprises the following working procedures: forming first insulation films (9), (10) above a semiconductor substrate 1; forming capacitors Q having lower electrodes (11a), dielectric films (13a) and upper electrodes (14c) on the first insulation films (9), (10); forming second insulation films (15), (15a), (16) which cover the capacitors Q; after the second insulation films (15), (15a), (16) are formed, forming a stress control insulation film (30) at the back of the semiconductor substrate 1.

Description

Manufacturing method of semiconductor device

technical field

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a capacitor.

Background technique

Flash memory (Flash Memory) and ferroelectric memory (FeRAM) are known as nonvolatile memories capable of storing information even when power is turned off.

The flash memory has a floating gate provided in a gate insulating film of an insulated gate type electric field effect transistor (IGFET), and stores information by storing charges that become stored information in the floating gate. Both writing and erasing of information require a channel current to flow through the gate insulating film, so a relatively high voltage is required.

FeRAM has a ferroelectric capacitor that uses the hysteresis characteristics of a ferroelectric to store information. In a ferroelectric capacitor, the ferroelectric film formed between the upper electrode and the lower electrode is polarized according to the voltage applied between the upper electrode and the lower electrode, and spontaneously polarized when the polarity of the applied voltage is reversed polarity is also reversed. Information can be read by detecting the polarity and magnitude of the spontaneous polarization.

Compared with flash memory, FeRAM has the advantage that it can operate at a low voltage and can perform high-speed writing while saving power.

As described in Document 1 (Japanese Patent Laid-Open No. 2001-60669), the memory cell of FeRAM has: a MOS transistor formed on a silicon substrate; a first interlayer insulating film formed on the silicon substrate and the MOS transistor; The ferroelectric capacitor on the first interlayer insulating film; the second interlayer insulating film formed on the ferroelectric capacitor and the first interlayer insulating film; the via buried on the first and second interlayer insulating films A conductive insert connected to the MOS transistor in the hole; a first wiring pattern that connects the conductive insert to the upper electrode of the ferroelectric capacitor; a third layer formed on the first wiring pattern and the second interlayer insulating film an interlayer insulating film; and a second wiring pattern formed on the third interlayer insulating film.

However, when the first wiring pattern is formed of aluminum, the tensile stress of the first wiring pattern deteriorates the residual polarization characteristics of the ferroelectric capacitor. In order to improve it, Document 2 (Japanese Patent Laid-Open No. 2001-36025) provides a technical solution to heat the aluminum film at a temperature exceeding the Curie point of the ferroelectric film constituting the ferroelectric capacitor. After relaxing the tensile stress, the aluminum film is used for patterning to form a wiring pattern.

In addition, Document 3 (Japanese Patent Application Laid-Open No. 11-330390 ) proposes a technique in which an interlayer insulating film is formed so as to have a tensile stress with respect to a ferroelectric capacitance.

Moreover, document 4 (Japanese Patent Laid-Open Publication No. 6-188249) also provides a method of forming a SiN film on the back surface of a substrate before forming a capacitor, and the SiN film has a The composition and film thickness of the SiN film on the surface are the same to suppress warping of the substrate.

According to Document 1, the interlayer insulating film covering the ferroelectric capacitor enhances the compressive stress and provides a force in the direction in which the capacitor itself expands. Therefore, when a plurality of interlayer insulating films are formed superimposed on the ferroelectric capacitor, the contraction force of the ferroelectric capacitor increases every time the film is formed, deteriorating the ferroelectric capacitor.

According to Document 2, since the interlayer insulating film still exists in the gap between the first wiring patterns, there is a possibility that the compressive stress of the interlayer insulating film degrades the ferroelectric capacitance regardless of the stress of the first wiring pattern question.

According to Document 3, there arises an additional problem that since the interlayer insulating film having tensile stress contains much moisture, the ferroelectric capacity is deteriorated due to moisture.

In the method of Document 4, according to investigations by the inventors of the present application, it has been found that uniform stress adjustment is difficult because the stress applied to capacitors within a wafer varies widely.

disclosure of invention

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of maintaining or improving the characteristics of a capacitor covered with an interlayer insulating film favorably and uniformly.

The above-mentioned problem is solved by a manufacturing method of a semiconductor device, which is characterized in that it has: a step of forming a first insulating film above a semiconductor substrate; , a process of capacitance between the dielectric film and the upper electrode; a process of forming a second insulating film covering the capacitance; and a process of forming a stress control insulating film on the back surface of the semiconductor substrate after forming the second insulating film.

According to the present invention, after the second insulating film covering the capacitor is formed, the stress control insulating film is formed on the back surface of the substrate. For example, the stress control insulating film is formed so as to have the same compressive stress or the same tensile stress as the second insulating film. In this way, while the stress generated by the second insulating film is relaxed, uniform stress adjustment can be performed, and as a result, favorable and uniform capacitance characteristics can be maintained or improved. According to experiments by the inventors of the present application, when the invention of the present application is applied to a method of manufacturing FeRAM having a ferroelectric capacitive insulating film, it is possible to improve switching charge characteristics and variations thereof.

Furthermore, since the stress on the entire wafer can be reduced, it is possible to prevent so-called edge degradation, which occurs significantly in a planar structure FeRAM. Terminal degradation is a phenomenon in which capacitance characteristics tend to deteriorate due to stress concentration on the side of the dielectric film of the capacitor at the terminal on the lower electrode common to a plurality of capacitors. This phenomenon occurs when an insulating film made of TEOS as a raw material is formed on the capacitor.

In the present invention, in particular, the same compressive stress can be imparted to the second insulating film and the stress control insulating film. In this case, it is preferable to cover the capacitor with a high-quality insulating film with a low moisture content.

The stress control insulating film formed on the back surface of the semiconductor substrate can be removed when unnecessary. In this case, the stress control insulating film may be removed after the step of forming wiring on the second insulating film for connecting the upper electrode of the capacitor through the via hole penetrating the second insulating film. This is because the high-temperature annealing process was performed to improve the film quality of the dielectric film of the capacitor through the via hole formed on the second insulating film above the upper electrode of the capacitor by etching, but the annealing process was completed after the annealing was completed. Thereafter, heat treatment at a higher temperature is not performed, and after the wiring is formed on the second insulating film, there is little change in the temporarily adjusted stress even if the stress control insulating film is removed.

A brief description of the drawings

FIG. 1 is a cross-sectional view (Part 1) showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

2(a) and 2(b) are cross-sectional views (Part 2) showing the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

3(a) and 3(b) are cross-sectional views (Part 3) showing the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

4(a) and 4(b) are cross-sectional views (Part 4) showing the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

5(a) and 5(b) are cross-sectional views (Part 5) showing the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

6(a) and 6(b) are cross-sectional views (Part 6) showing the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

7(a) and 7(b) are cross-sectional views (part 7) showing the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

8(a) and 8(b) are cross-sectional views (8) showing the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

9(a) and 9(b) are cross-sectional views (9) showing the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

Fig. 10 is a cross-sectional view (10) showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

Fig. 11 is a cross-sectional view (11) showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

12 is a plan view showing the arrangement relationship among capacitors, transistors, wiring, and conductive pads formed by the method of manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 13 is a graph showing the switching charge distribution of the capacitance of the FeRAM produced by the method of manufacturing the semiconductor device according to the embodiment of the present invention.

The best way to practice the invention

Hereinafter, embodiments of the present invention will be described based on the drawings.

1 to 11 are cross-sectional views showing the manufacturing steps of a planar FeRAM according to an embodiment of the present invention.

The process of forming the structure shown in FIG. 1 will be described.

First, as shown in FIG. 1 , an element isolation insulating film 2 is formed on the surface of an n-type or p-type silicon (semiconductor) substrate 1 by the LOCOS (Local Oxidation of Silicon: local oxidation of silicon) method. As the element isolation insulating film 2, in addition to the structure formed by the LOCOS method, an STI (Shallow Trench Isolation: Shallow Trench Isolation) structure may be used.

After forming such an element isolation insulating film 2, p-type impurities and n-type impurities are selectively introduced into predetermined active regions (transistor formation regions) in the memory cell region A and peripheral circuit region B of the silicon substrate 1 to form p-type impurities. well 3a and n-well 3b. Furthermore, in order to form a CMOS in the peripheral circuit region B, not only the n well 3b but also a p well (not shown) is formed.

Thereafter, the surface of the active region of the silicon substrate 1 is thermally oxidized to form a silicon oxide film constituting a gate insulating film.

Next, a film of amorphous silicon or polysilicon is formed on the entire upper surface of the silicon substrate 1, and then impurity ions are implanted to lower the resistance of the silicon film. Thereafter, the silicon film is patterned into a predetermined shape by photolithography, and gate electrodes 5a, 5b, 5c and wiring 5d are formed.

In memory cell region A, two gate electrodes 5a, 5b are arranged at approximately parallel intervals on one p-well 3a, and extend in the vertical direction of the paper of the drawing. These gate electrodes 5a, 5b form a part of word line WL.

Then, in the memory cell region A, n-type impurities are ion-implanted into the p-well 3a on both sides of the gate electrodes 5a, 5b to form three n-type impurity diffusion regions constituting the source/drain of the p-channel MOS transistor. 6a. At the same time, an n-type impurity diffusion region is also formed in a p well (not shown) in the peripheral circuit region B. As shown in FIG.

Next, in the peripheral circuit region B, p-type impurities are ion-implanted on both sides of the gate electrode 5c in the n-well 3b to form the p-type impurity diffusion region 6b constituting the source/drain of the p-channel MOS transistor.

Then, after an insulating film is formed on the entire surface of the silicon substrate 1 , the insulating film is etched to remain as sidewall insulating films 7 only on both sides of the gate electrodes 5 a to 5 c . As the insulating film, silicon oxide (SiO ₂ ) is formed, for example, by a CVD (Chemical Vapor Deposition: chemical vapor deposition) method.

Then, using gate electrodes 5a to 5c and sidewall insulating film 7 as a mask, n-type impurity ions are implanted again in p well 3a to make n-type impurity diffusion region 6a have an LDD structure, and by The p-type impurity ions are implanted again, so that the p-type impurity diffusion region 6b also has an LDD structure.

Furthermore, the distinction between n-type impurities and p-type impurities can be performed using a resist pattern.

As described above, in the memory cell region A, an n-type MOSFET is constituted by the p well 3a, the gate electrodes 5a, 5b, and the n-type impurity diffusion region 6a on both sides thereof, and in the peripheral circuit region B, an n-type MOSFET is formed by the n-well 3b, the gate electrode 5c, and the p-type impurity diffusion region 6b on both sides thereof constitute a p-type MOSFET.

Then, after forming a high-melting-point metal film, such as a Ti or Co film, on the entire surface, the high-melting-point metal film is heated to form high-melting-point metal films on the surfaces of the n-type impurity diffusion region 6a and the p-type impurity diffusion region 6b, respectively. Metal silicide layers 8a, 8b. After that, the unreacted refractory metal film is removed by wet etching.

Then, a silicon oxynitride (SiON) film with a thickness of about 200 nm is formed as a coating film 9 on the entire surface of the silicon substrate 1 by plasma CVD. Then, silicon dioxide (SiO ₂ ) is grown to a thickness of approximately 1.0 micron on the coating film 9 as a first interlayer insulating film by plasma CVD using TEOS gas. The insulating film formed by the plasma CVD method using TEOS gas is also referred to as a PE-TEOS film below.

Then, the upper surface of the first interlayer insulating film 10 is polished and planarized by a chemical mechanical polishing (CMP: Chemical Mechanical Polishing) method.

Next, the process of forming the structure shown in FIG. 2( a ) will be described.

First, the surface of the planarized first interlayer insulating film 10 is improved with plasma of ammonia (NH ₃ ) gas. Also, the surface of the insulating film is treated with plasma of NH ₃ gas for improvement, which is hereinafter referred to as NH ₃ plasma treatment.

As the conditions of the _NH3 plasma treatment in this process, for example, it can be set as follows: the flow rate of _NH3 gas introduced into the chamber is 350 sccm, the pressure in the chamber is 1 Torr, the substrate temperature is 400°C, and the 13.56MHz gas supplied to the substrate is The power of the high-frequency power supply is 100W, the power of the 350KHz high-frequency power supply supplied to the plasma generation area is 55W, the distance between the electrode and the first interlayer insulating film is 350mils, and the plasma irradiation time is 60 seconds.

Thereafter, as shown in FIG. 2( b ), an intermediate layer (self-alignment layer) 11 made of a substance having self-alignment property is formed on the first interlayer insulating film 10 . The intermediate layer can be formed, for example, by the following steps.

First, a titanium (Ti) film with a thickness of 20 nm is formed on the first interlayer insulating film 10 by DC sputtering, and then the Ti film is oxidized by RTA (rapid thermal annealing) to form titanium oxide ( TiO _x ) film, this TiO _x film is used as the intermediate layer 11.

The oxidation conditions of the Ti film can be set as follows: for example, the substrate temperature is 700° C., the oxidation time is 60 seconds, and the oxygen (O ₂ ) and argon (Ar) in the oxidation environment are 1% and 99%, respectively. Furthermore, a Ti film that has not been oxidized may be used as it is as the intermediate layer 11 .

The intermediate layer 11 is an element to improve the orientation strength of the first conductive film formed later, and also has a function of blocking the diffusion of Pb in the PZT-based ferroelectric film further formed on the first conductive film to the lower layer. In addition, the intermediate layer 11 also has a function of improving the sealability between the first conductive film 12 and the first interlayer insulating film 10 to be formed later.

The self-aligning material constituting the intermediate layer 11 may be, in addition to Ti, aluminum (Al), silicon (Si), copper (Cu), tantalum (Ta), tantalum nitride (TaN), iridium (Ir ), iridium oxide (IrO _x ), platinum (Pt), etc. In the following embodiments, the intermediate layer can be selected from these materials.

Next, the steps of forming the structure shown in FIG. 3( a ) will be described.

First, on the intermediate layer 11, a Pt film having a thickness of 175 nm was formed as the first conductive film 12 by sputtering. As film-forming conditions of the Pt film, Ar gas pressure of 0.6 Pa, DC power of 1 kW, and substrate temperature of 100° C. can be set. The target is platinum.

Furthermore, as the first conductive film 12, a film of iridium, ruthenium, ruthenium oxide, strontium ruthenium oxide (SrRuO ₃ ) or the like may be formed. In this embodiment and the following embodiments, the first conductive film is made of a substance having self-alignment.

Then, a PZT (PLZT (lead lanthanum zirconate titanate) in which lanthanum (La) is added to (Pb(Zrl-xTix)O ₃ ) is formed on the first conductive film 12 with a thickness of 100 to 300 nm, such as 240 nm, by sputtering. : lead lanthanum zirconate titanate; (Pb _1-3x/2 La _x )(Zr _1-y Ti _y )O3)) film, which is used as the ferroelectric film 13 . Furthermore, calcium (Ca) and strontium (Sr) may be added to the PLZT film.

Next, the silicon substrate 1 was placed in an oxygen atmosphere, and the PLZT film was crystallized by RTA. As the crystallization conditions, for example, the substrate temperature is 585°C, the processing time is 20 seconds, the heating rate is 125°C/sec, and the ratios of _O2 and Ar introduced into the oxygen atmosphere are 2.5% and 97.5%. .

As a method for forming the ferroelectric film 13, in addition to the above-mentioned sputtering method, there are spin method, sol-gel transition method, MOD (Metal Organic Deposition: Metal Organic Deposition) method, MOCVD (Metal Organic Chemical Vapor Deposition) method, etc. )Law. In addition, as the material of the ferroelectric film 13, other than PLZT, PZT, SrBi ₂ (Tax _{Nb 1-x} ) ₂ O ₉ (where 0<x≦1), Bi ₄ Ti ₂ O ₁₂ and the like may be used. Furthermore, when forming a DRAM, it is only necessary to replace the ferroelectric material with a high dielectric material such as (BaSr)TiO ₃ (BST) or strontium titanate (STO).

Then, as shown in FIG. 3( b ), the second conductive film 14 is formed on the ferroelectric film 13 . The second conductive film 14 can be formed by the following two steps.

First, an iridium oxide ( _IrOx ) film with a thickness of 20 to 75 nm, for example, 50 nm, is formed on the ferroelectric film 13 as the lower conductive layer 14a of the second conductive film 14 by sputtering. Thereafter, crystallization of the ferroelectric film 13 and annealing of the lower conductive layer 14a are performed by RTA in an oxygen atmosphere. As the conditions of RTA, it can be set that the substrate temperature is 725°C, the processing time is 1 minute, and the ratios of _O2 and Ar introduced into the oxygen atmosphere are 1% and 99%, respectively.

Then, an iridium oxide ( _IrOx ) film with a thickness of 100 to 300 nm, eg, 200 nm, is formed as the upper conductive layer 14b of the second conductive film 14 on the lower conductive layer 14a by sputtering.

In addition, as the upper conductive layer 14b of the second conductive film 14, a platinum film or a strontium ruthenium oxide (SRO) film may be formed by sputtering.

Next, the steps of forming the structure shown in Fig. 4(a) will be described.

First, after forming a resist pattern (not shown) in the planar shape of the upper electrode on the second conductive film 14, the second conductive film 14 is etched using the resist pattern as a mask, and the remaining second conductive film 14 is etched. 2. The pattern of the conductive film 14 is used as the upper electrode 14c of the capacitor.

Then, after removing the resist pattern, the ferroelectric film 13 was annealed in an oxygen atmosphere at 650° C. for 60 minutes. This annealing treatment is performed at the time of sputtering of the upper conductive layer 14b of the second conductive film 14 and at the time of etching of the second conductive film 14 in order to restore damage to the ferroelectric film 13 .

Then, in the state where a resist pattern (not shown) is formed on the capacitor upper electrode 14c and its surroundings in the memory cell region A, the ferroelectric 13 is etched, so that the ferroelectric remaining under the upper electrode 14c can be removed. The film 13 is used as a ferroelectric film 13a of a capacitor.

Then, the ferroelectric film 13 is annealed in a nitrogen and oxygen atmosphere with the resist pattern (not shown) removed. For example, this annealing is performed to remove moisture and the like absorbed by the ferroelectric film 13 and the films below it.

Then, as shown in Figure 4(b), on the upper electrode 14c, the ferroelectric film 13a and the first conductive film 12, an Al ₂ O ₃ film with a thickness of 50 nm is formed at room temperature by sputtering as the first sealant. Layer 15. The first sealing layer 15 is formed to protect the easily reducible dielectric film 13 from hydrogen, and is formed to prevent hydrogen from entering its interior.

As the first sealing layer 15, a PZT film, a PLZT film, or a titanium oxide film may be formed. The Al ₂ O ₃ film, PZT film, PLZT film, or titanium oxide film as the sealing layer may be formed by MOCVD, or a laminated film formed by two methods such as sputtering and MOCVD. When the first sealing layer 15 is a laminated film, it is preferable to form an Al ₂ O ₃ film by a sputtering method in advance in consideration of deterioration in capacitance.

Thereafter, the first sealing layer 15 is heat-treated under the condition of 550° C. in an oxygen atmosphere for 60 minutes to improve its film quality.

Then, a resist (not shown) is applied on the first sealing layer 15, exposed and developed, and the planar shape of the lower electrode remains on and around the upper electrode 14c and the dielectric film 13a. Then, using the resist film as a mask, the first sealing layer 15, the first conductive film 12, and the intermediate layer 11 are etched, and the remaining pattern of the first conductive film 12 is used as the lower electrode 11a of the capacitor. Furthermore, the intermediate layer 11 also constitutes the lower electrode 11a. The etching of the sealing layer 15, the first conductive film 12, and the intermediate layer 11 can be performed by dry etching using halogen elements such as chlorine and bromine.

After removing the resist, the upper electrode 14c, the dielectric film 13a, and the like are annealed at 350° C. for 30 minutes in an oxygen atmosphere. The purpose of this is to prevent the detachment of the film formed in the subsequent process.

In this way, as shown in FIG. 5(a), on the first interlayer insulating film 10, a lower electrode 11a (first conductive film 12/intermediate layer 11), a dielectric film 13a, and an upper electrode 14c (second conductive film) are formed. ) constitutes the capacitor Q.

Next, formation of the structure shown in FIG. 5(b) will be described.

First, a 20 nm-thick Al ₂ O ₃ film is formed as the second sealing layer 15a to cover the capacitor Q and the first interlayer insulating film 10 by sputtering. A material other than the material used for the first sealing layer 15 can be used as the second sealing layer 15a. Then, the ferroelectric film 13a is annealed at 650° C. for 60 minutes in an oxygen atmosphere to recover from damage.

Next, on the sealing layer 15a, a SiO ₂ film having a film thickness of 1500 nm was formed as the second interlayer insulating film 16 by the CVD method. For the growth of the second interlayer insulating film 16, silane (SiH ₄ ) and polysilane compounds (Si ₂ F ₆ , Si ₃ F ₈ , Si ₂ F ₃ Cl, etc.) and SiF ₄ can be used as film-forming gases. Use TEOS. The CVD method as the film forming method can be plasma excitation (ECR method: Electron cyclotron Resonance (electron cyclotron resonance method), ICP method: Inductively Coupled Plasma (inductively coupled plasma), HDP: High Density Plasma (high density plasma), EMS: Electron Magneto-Sonic (electron magneto-acoustic)), thermal excitation, and laser excitation methods. An example of film formation conditions of the second interlayer insulating film 16 by the plasma CVD method is shown below.

TEOS gas flow: 460sccm

He (TEOS carrier gas) flow rate: 480sccm

_O2 flow: 700sccm

Pressure: 9.0Torr

Frequency of high frequency power supply: 13.56MHz

High frequency power supply power: 400W

Film forming temperature: 390°C

Then, as shown in FIG. 6(a), under the same film-forming method and conditions as the film-forming method and conditions of the second interlayer insulating film 16, SiO ₂ with a film thickness of 1500 nm is formed on the back surface of the silicon substrate 1. The stress control insulating film 30 is composed of a film.

Thereafter, as shown in FIG. 6(b), the upper surface of the second interlayer insulating film 16 is planarized by CMP. The surface of the second interlayer insulating film 16 is planarized until the thickness becomes 400 nm from the upper surface of the upper electrode 14c. Moisture in the slurry used for planarization by the CMP method and in the cleaning solution used in subsequent cleaning adheres to or is absorbed on the surface of the second interlayer insulating film 16. to its interior.

Therefore, the second interlayer insulating film 16 is heated at a temperature of 390° C. in a vacuum chamber (not shown), and moisture on the surface and inside thereof is discharged to the outside. After such dehydration treatment, the second interlayer insulating film 16 is heated and exposed to N ₂ O plasma to dehydrate and improve the film quality. In this way, deterioration of capacitance due to heating and water in subsequent processes is prevented. Such dehydration treatment and plasma treatment may also be performed in the same chamber (not shown). In the chamber, a supporting electrode carrying the silicon substrate 1 and an opposing electrode facing it are arranged, and the opposing electrode is in a state capable of being connected to a high-frequency power source. Then, with N ₂ O gas introduced into the chamber, a high-frequency voltage was applied to the counter electrode to generate N ₂ O plasma between the electrodes to perform N ₂ O plasma treatment of the insulating film. According to this N ₂ O plasma treatment, nitrogen is contained in at least the surface of the insulating film. Such a method can also be employed in the following steps. When performing plasma treatment following the dehydration treatment, it is preferable to use N ₂ O plasma, but it is also possible to use NO plasma, N ₂ plasma, etc., and the same applies to the steps described later. Furthermore, the substrate temperature for the dehydration treatment is substantially the same as the substrate temperature for the plasma treatment.

Then, as shown in FIG. 7(a), the first interlayer insulating film 10, the second sealing layer 15a, the second interlayer insulating film 16, and the The cover film 9 is etched to form contact holes 16a to 16c on the upper surface of the impurity diffusion layer 6a in the memory cell region A, and contact holes 16d and 16e are formed on the upper surface of the impurity diffusion layer 6b in the peripheral circuit region B. A contact hole 16f is formed on the wiring 5d on the element isolation insulating layer 2 .

The second interlayer insulating film 16 , the second sealing layer 15 , the first interlayer insulating film 10 , and the cover film 9 are etched using a CF-based gas, for example, a mixed gas in which CF ₄ and Ar are added to CHF ₃ .

Then, as shown in FIG. 7(b), in order to perform the above-mentioned treatment on the upper surface of the second interlayer insulating film 16 and the inner surfaces of the contact holes 16a to 16f, after performing RF (high frequency) etching, sputtering is used on them. A 20-nm-thick titanium (Ti) film and a 50-nm-thick titanium nitride (TiN) film were successively formed by irradiation, and these films were used as the gel layer 17 . Then, a tungsten (W) film 18 is formed on the upper surface of the gel layer 17 by a CVD method using a mixed gas of tungsten hexafluoride (WF ₆ ), argon, and hydrogen. Furthermore, silane (SiH ₄ ) gas is also used at the initial stage of growth of the tungsten film 18 . Tungsten film 18 has a thickness to completely bury contact holes 16 a to 16 f , for example, 500 nm on the uppermost surface of gel layer 17 .

Then, as shown in FIG. 8(a), the tungsten film 18 and the gel layer 17 on the upper surface of the second interlayer insulating film 16 are removed by CMP, leaving only the contact holes 16a to 16f. In this way, the respective tungsten films 18 and gel layers 17 in the contact holes 16a to 16f are used as conductive plugs 17a to 17f.

Afterwards, in order to remove the moisture adhering to the surface of the second interlayer insulating film 16 or penetrating into the inside of the second interlayer insulating film 16 during the cleaning process after the formation of the contact holes 16a to 16f, the cleaning process after the CMP, etc., the , heat the second interlayer insulating film at a temperature of 390° C. in a vacuum chamber to remove moisture to the outside. After such dehydration treatment, the second interlayer insulating film 16 is heated and exposed to N ₂ O plasma to perform annealing treatment for improving film quality, for example, for 2 minutes.

Then, as shown in FIG. 8(b), SiON is formed with a thickness of about 100 nm on the second interlayer insulating film 16 and the conductive plugs 17a to 17f as a tungsten oxidation prevention film 19 by plasma CVD.

Next, as shown in FIG. 9(a), using a resist pattern (not shown) as a mask, the second interlayer insulating film 16 and the sealing layers 15, 15a on the upper electrode 14c are etched to form vias. Hole 16g. At the same time, a via hole is also formed on the lower electrode 11a exposed from the upper electrode 14c in the extending direction of the word line WL. In addition, although the through hole in the lower electrode 11 a is not shown in FIG. 9( a ), it is indicated by reference numeral 20 g in FIG. 12 .

The etching is carried out by using a CF gas, such as a mixed gas of CHF ₃ with CF ₄ and Ar added. After that, the resist pattern is removed.

Thereafter, in the state shown in FIG. 9( a ), an annealing treatment is performed at 550° C. for 60 minutes in an oxygen atmosphere to improve the film quality of the dielectric film 13 a through the through hole 16 g. In this case, since the conductive inserts 17a to 17f made of easily oxidizable tungsten are covered with the oxidation preventing film 19, oxidation does not occur.

Next, as shown in FIG. 9(b), the oxidation prevention film 19 on the second interlayer insulating film 16 and the conductive plugs 17a to 17f is etched by etching to expose the conductive plugs 17a to 17f. In this case, the upper ends of the conductive plugs 17 a to 17 f are exposed from the second interlayer insulating film 16 .

Then, with the conductive plugs 17a to 17f and the upper electrode 14c exposed, their surfaces are etched by about 10 nm (in terms of SiO ₂ ) by RF etching to expose a clean surface.

Thereafter, a conductive film of a four-layer structure containing aluminum is formed on the second interlayer insulating film 16 and the conductive plugs 17a to 17f by sputtering. The conductive film is, in descending order, a titanium nitride film with a film thickness of 150 nm, an aluminum film containing copper (0.5%) with a film thickness of 550 nm, a titanium film with a film thickness of 5 nm, and a titanium nitride film with a film thickness of 150 nm.

Next, as shown in FIG. 10 , the conductive film is patterned by photolithography to form first to fifth wirings 20 a , 20 c , 20 d to 20 f and conductive pads 20 b. And at the same time, wiring connected to the lower electrode 11a is also formed in the through hole 20g.

In the memory cell region A, the first wiring 20a is connected to the upper electrode 14c on one side of the p well 3a through the via hole 16g, and is connected to the conductive plug 17a on the p well 3a closest to the upper electrode 14c. The second wiring 20c is connected to the upper electrode 14a on the other side of the p-well 3a through the via hole 16g, and is connected to the conductive plug 17c on the p-well 3a closest to the upper electrode 14c. The conductive pad 20b is formed in an island shape on the upper surface of the conductive pad 17b formed on the upper surface at the center of the p-well 3a. The third to fifth wiring lines 20d to 20f are connected to the conductive plugs 17d to 17f in the peripheral circuit area.

The planar arrangement relationship of the wirings 20 a and 20 c , the conductive pad 20 b , capacitors, and transistors formed in this step is shown in FIG. 12 . FIG. 10 corresponds to a sectional view taken along line I-I in FIG. 12 . As shown in FIG. 12 , the dielectric film 13a also extends continuously in a strip shape on the lower electrode 11a extending in a continuous strip shape, and a plurality of upper electrodes 14c are formed at intervals on one dielectric film 13a. Components denoted by other reference numerals are the same as components denoted by the same reference numerals in FIGS. 1 to 10 .

Next, steps for forming the structure shown in FIG. 11 will be described.

First, after forming the third interlayer insulating film 21 on the upper surfaces of the first to fifth wirings 20a, 20c, 20d to 20f and the conductive pad 20b, the upper surface of the third interlayer insulating film 21 is flattened by CMP. change.

Next, via holes (via holes) 22a and 22b are formed in the third interlayer insulating film 21 using a mask (not shown). The via holes 22a and 22b are formed on the conductive pad 20b on the p-well 3a of the memory cell region A, on the upper surface of the wiring 20e in the peripheral circuit region B, and at other positions.

Furthermore, in the via holes 22a, 22b, vias 23a, 23b made of a TiN layer and a W layer are formed. These vias 23a, 23b are formed as follows: After forming a TiN layer and a W layer in the via holes 22a, 22b and on the third interlayer insulating film 21 by sputtering and CVD, the third interlayer insulating film is removed from the third interlayer insulating film by CMP. The TiN layer and the W layer are removed on layer 21, so that vias 23a, 23b remain in via holes 22a, 22b.

Next, after forming the second-layer wiring lines 24a to 24e on the third interlayer insulating film 21, a fourth interlayer insulating film 25 is formed on the third interlayer insulating film 21 and the second-layer wiring lines 24a to 24e. . Further, after the fourth interlayer insulating film 25 is planarized, a conductive pattern 26 made of aluminum is formed on the fourth interlayer insulating film 25 . Thereafter, a first cover insulating film 27 made of silicon oxide and a second cover insulating film 28 made of silicon nitride are sequentially formed on the fourth interlayer insulating film 25 and the conductive pattern 26 .

After that, a protective film (not shown) is formed on the surface with resin or the like. Furthermore, when it is necessary to adjust the thickness of the substrate, after forming the protective film, the back surface of the substrate is shaved off by a back grinding process. As above, the basic structure of FeRAM is formed.

In addition, the stress control insulating film 30 may be left as it is and chipped, or after the process of forming the wiring 20a and the like and the conductive pad 20b in FIG. In any step, they can be removed by post-grinding treatment or the like. Even in the case of removing the stress control insulating film 30, since the annealing for improving the film quality of the dielectric film of the capacitor is completed, there is no heat treatment process at a higher temperature in the subsequent process, and if the wiring After the formation of 20a and the like, there is basically no step of applying a large stress in the subsequent steps, so the stress on the substrate can be kept small.

The characteristics of the capacitor Q formed by the above implementation form are improved compared with the prior art.

Therefore, the results of investigation on the characteristics of the capacitor Q formed in the above embodiment will be described in detail below. In addition, the interlayer insulating film and the stress control insulating film described below are silicon oxide films in principle. Depending on circumstances, other types of insulating films such as silicon nitride films, silicon oxynitride films, aluminum oxide films, etc. may be used.

First, the FeRAM of this embodiment in which the second interlayer insulating film 16 and the stress control insulating film 30 are formed in the order of the front surface (S)→the rear surface (R) by the above steps is prepared. Furthermore, as a comparative sample, a FeRAM in which an interlayer insulating film was formed only on the surface (S) was prepared, and a thin interlayer insulating film was formed in the order of the surface (S) → rear surface (R) → surface (S), and a thick FeRAM was prepared. FeRAM in which a stress control insulating film and a thick interlayer insulating film are formed, and FeRAM in which a stress control insulating film and an interlayer insulating film are formed in this order from the rear surface (R) to the surface (S).

The film-forming method and film-forming conditions of the interlayer insulating film and the stress control insulating film of the comparative sample are the same as the film-forming method and film-forming conditions of the second interlayer insulating film 16 and the stress control insulating film 30 of the present embodiment. . However, in the sample of surface (S)→back surface (R)→surface (S), although two layers of a thin interlayer insulating film and a thick interlayer insulating film are formed on the surface, the gap between the two layers is The film thickness of the insulating film was the same as that of the interlayer insulating film of one layer in the other samples.

FIG. 13 is a graph showing the results of investigating the distribution of the switching charge (Qsw) of the capacitor Q for each of the aforementioned FeRAMs. In FIG. 13 , the vertical axis represents the cumulative generation rate (%), and the horizontal axis represents the switching charge (Qsw) (µC/cm ² ) expressed on a linear scale.

In the figure, the symbol ○ indicates the characteristics of FeRAM in which an interlayer insulating film is formed only on the surface (S), and the symbol □ indicates that the interlayer insulating film and the The characteristics of the FeRAM of this embodiment of the stress control insulating film, the symbol △ indicates that the interlayer insulating film, the stress control insulating film, and the interlayer insulating film are formed in the order of the surface (S) → the rear surface (R) → the surface (S). The characteristics of FeRAM, the symbol ◇, indicates the characteristics of FeRAM in which a stress control insulating film and an interlayer insulating film are formed in the order of rear surface (R)→surface (S).

According to FIG. 13 , in the case of FeRAM (□ mark) of this embodiment formed in the order of surface (S)→rear face (R), compared with the case of FeRAM (circle mark) formed only on the surface , while improving the switching charge (Qsw) characteristics of 1 μC/cm ² or above, the deviation was improved from 13% to 9.97%.

In the case of FeRAM formed in the order of rear surface (R)→surface (S) (◊ symbol), the distribution of switching charge (Qsw) increased toward the lower direction, and the deviation was 36%, which was worse.

As described above, according to the manufacturing method of the semiconductor device of this embodiment, after forming the second interlayer insulating film 16 covering the capacitance, since the stress control insulating film 30 is formed on the back surface of the silicon substrate 1, it is possible to relax the stress of the second interlayer insulating film 16. Uniform adjustment of the stress can be performed simultaneously with the stress of the interlayer insulating film 16 . As a result, the characteristics of capacitance including switching charges can be maintained favorably and uniformly, or the characteristics can be improved.

Furthermore, since the stress on the entire wafer is reduced, it is possible to prevent the phenomenon of so-called edge degradation, which is conspicuous in the planar structure FeRAM. Terminal deterioration is a phenomenon in which capacitance characteristics are easily degraded due to stress concentration on the side of the dielectric film of the capacitor at the terminal on the lower electrode 11a common to a plurality of capacitors. This phenomenon occurs when an insulating film made of TEOS as a raw material is formed on the capacitor.

Moreover, since it is only necessary to apply the same type of stress as the stress of the second interlayer insulating film 16 to the stress control insulating film 30, it is not necessary to adjust the film stress so that it becomes opposite to each other due to the moisture content in the film. stress, and for example, a high-quality insulating film having compressive stress can be used as the second interlayer insulating film 16 and the stress control insulating film 30, and the moisture content is small.

Above, although the present invention has been described in detail using specific embodiments, the present invention is not limited by the examples specifically shown in the above-mentioned embodiments, and the above-mentioned embodiments are described within the scope not departing from the gist of the present invention. Modifications are included within the scope of the present invention.

For example, in the above-mentioned embodiment, although it has been described about FeRAM with a planar structure characterized by the connection between the lower electrode 11a of the capacitor Q obtained from the upper part of the capacitor Q and the transistor under the lower electrode 11a, it may also be It is applicable to the FeRAM of the stack structure characterized by obtaining the connection directly under the lower electrode 11a of the capacitor through the conductive plug directly to the transistor under the lower electrode 11a.

In addition, the film-forming method and film-forming conditions of the second interlayer insulating film 16 and the stress control insulating film 30 can also be appropriately selected in consideration of the laminate structure, materials used, and other factors.

In the above embodiment, since the stress of the second interlayer insulating film 16 directly above the capacitor has the greatest influence, it is mainly to offset the stress at the second interlayer insulating film 16 directly above the capacitor, so that the stress can be controlled. The film-forming method and film-forming conditions of the insulating film 30 are the same as the film-forming method and film-forming conditions of the second interlayer insulating film 16 . However, in reality, since there are also influences of stress on the wiring layer 20a and the like, the conductive pads 20b, and the third and fourth interlayer insulating films 21 and 25, the film-forming method and film-forming conditions of the stress control insulating film 30 , it is not necessary to be the same as the film forming method and film forming conditions of the second interlayer insulating film 16, and appropriate selection can be made so that the stress of the capacitor can be finally reduced.

Although the second interlayer insulating film 16 and the stress control insulating film 30 are composed of a single-layer SiO ₂ film, they may be composed of a single-layer silicon nitride film, aluminum oxide film, etc. instead of the SiO ₂ film.

Although the second interlayer insulating film 16 and the stress control insulating film 30 are composed of a single layer, they may be composed of a multilayer structure of two or more layers composed of the same type of insulating film or different types of insulating films. .

The second interlayer insulating film 16 and the stress control insulating film 30 are formed by a chemical vapor growth method at a film forming temperature of 390°C, but they may be formed at 400°C or below by chemical vapor deposition under a film forming temperature condition that can form a film. Vapor phase growth method to form.

According to the present invention described above, after the second insulating film covering the capacitor is formed, the stress control insulating film is formed on the back surface of the substrate. In this way, while relieving the stress generated by the second insulating film, the stress can be uniformly adjusted, and as a result, it is possible to achieve good and uniform maintenance or improvement of capacitance characteristics.

In addition, since the stress on the entire wafer can be reduced, it is possible to prevent the so-called terminal degradation from being remarkably generated in the planar FeRAM.

Claims (20)

1. the manufacture method of a semiconductor device is characterized in that, comprising:

Above semiconductor substrate, form the operation of the 1st dielectric film;

On above-mentioned the 1st dielectric film, form the operation of electric capacity with lower electrode, dielectric film and upper electrode;

Form the operation of the 2nd dielectric film that covers above-mentioned electric capacity;

After forming above-mentioned the 2nd dielectric film, form the operation of Stress Control dielectric film at the back side of above-mentioned semiconductor substrate.

2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, above-mentioned the 2nd dielectric film and above-mentioned Stress Control dielectric film all have identical compression stress or identical tensile stress.

3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film have the sandwich construction more than 2 layers or 2 layers respectively.

4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film are individual layer or the sandwich constructions that includes the dielectric film of silicon.

5. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film are film forming by the chemical vapor-phase growing method.

6. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film are to form under the film-forming temperature below 400 ℃ or 400 ℃.

7. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film are film forming under identical chemical vapor-phase growing method and the membrance casting condition.

8. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the material of the dielectric film of above-mentioned electric capacity is a strong dielectric.

9. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, before the operation that forms above-mentioned the 1st dielectric film, has the transistorized operation of formation on above-mentioned semiconductor substrate.

10. the manufacture method of semiconductor device as claimed in claim 9 is characterized in that, is formed with a plurality of electric capacity on above-mentioned lower electrode, and above-mentioned lower electrode is common for above-mentioned a plurality of electric capacity.

11. the manufacture method of semiconductor device as claimed in claim 9 is characterized in that, comprising:

The lower electrode of above-mentioned electric capacity has not the contact area that is covered by above-mentioned dielectric film and upper electrode, after forming above-mentioned the 2nd dielectric film, in the above-mentioned operation that forms the 1st through hole that connects the above-mentioned the 1st and the 2nd dielectric film above transistorized;

Above above-mentioned contact area, form the operation of the 2nd through hole that connects above-mentioned the 2nd dielectric film;

Above the upper electrode of above-mentioned electric capacity, form the operation of the 3rd through hole that connects above-mentioned the 2nd dielectric film;

On above-mentioned the 2nd dielectric film, form the operation that is connected above-mentioned lower electrode and above-mentioned transistorized distribution with the 2nd through hole by the above-mentioned the 1st;

On above-mentioned the 2nd dielectric film, form the operation that connects above-mentioned upper electrode and above-mentioned transistorized distribution by above-mentioned the 3rd through hole.

12. the manufacture method of semiconductor device as claimed in claim 10 is characterized in that, comprising:

The lower electrode of above-mentioned electric capacity has not the contact area that is covered by above-mentioned dielectric film and upper electrode, after forming above-mentioned the 2nd dielectric film, in the above-mentioned operation that forms the 1st through hole that connects the above-mentioned the 1st and the 2nd dielectric film above transistorized;

Above above-mentioned contact area, form the operation of the 2nd through hole that connects above-mentioned the 2nd dielectric film;

Above the upper electrode of above-mentioned electric capacity, form the operation of the 3rd through hole that connects above-mentioned the 2nd dielectric film;

On above-mentioned the 2nd dielectric film, form the operation that is connected above-mentioned lower electrode and above-mentioned transistorized distribution with the 2nd through hole by the above-mentioned the 1st;

On above-mentioned the 2nd dielectric film, form the operation that connects above-mentioned upper electrode and above-mentioned transistorized distribution by above-mentioned the 3rd through hole.

13. the manufacture method of semiconductor device as claimed in claim 11 is characterized in that, after the operation that forms above-mentioned electric capacity, has the operation that above-mentioned electric capacity is annealed.

14. the manufacture method of semiconductor device as claimed in claim 13, it is characterized in that, the operation that above-mentioned electric capacity is annealed, be above the upper electrode of above-mentioned electric capacity, to form after the operation of the 3rd or the 4th through hole that connects above-mentioned the 2nd dielectric film, in oxygen atmosphere, carry out by the 3rd or the 4th through hole.

15. the manufacture method of semiconductor device as claimed in claim 11 is characterized in that, after the operation that forms above-mentioned distribution, has the operation of removing above-mentioned Stress Control dielectric film.

16. the manufacture method of semiconductor device as claimed in claim 9 is characterized in that, has:

Through hole by the 1st dielectric film under the lower electrode that connects above-mentioned electric capacity connects above-mentioned lower electrode and above-mentioned transistor, after forming above-mentioned the 2nd dielectric film, above the upper electrode of above-mentioned electric capacity, form the operation of the 4th through hole that connects above-mentioned the 2nd dielectric film;

On above-mentioned the 2nd dielectric film, form the operation that connects the distribution of above-mentioned upper electrode by above-mentioned the 4th through hole.

17. the manufacture method of semiconductor device as claimed in claim 10 is characterized in that, has:

Through hole by the 1st dielectric film under the lower electrode that connects above-mentioned electric capacity connects above-mentioned lower electrode and above-mentioned transistor, after forming above-mentioned the 2nd dielectric film, above the upper electrode of above-mentioned electric capacity, form the operation of the 4th through hole that connects above-mentioned the 2nd dielectric film;

On above-mentioned the 2nd dielectric film, form the operation that connects the distribution of above-mentioned upper electrode by above-mentioned the 4th through hole.

18. the manufacture method of semiconductor device as claimed in claim 16 is characterized in that, after the operation that forms above-mentioned electric capacity, has the operation that above-mentioned electric capacity is annealed.

19. the manufacture method of semiconductor device as claimed in claim 18, it is characterized in that, the operation that above-mentioned electric capacity is annealed, be above the upper electrode of above-mentioned electric capacity, to form after the operation of the 3rd or the 4th through hole that connects above-mentioned the 2nd dielectric film, in oxygen atmosphere, carry out by the 3rd or the 4th through hole.

20. the manufacture method of semiconductor device as claimed in claim 16 is characterized in that, after the operation that forms above-mentioned distribution, has the operation of removing above-mentioned Stress Control dielectric film.

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