JP2008270303A - Multilayer semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a stacked semiconductor device which has no warp inflection point and has excellent mountability when stacking upper and lower semiconductor devices.
A lower-layer semiconductor device after solder melting is provided by providing a connection terminal for suppressing warpage in a region facing a semiconductor element mounted on a lower-layer semiconductor device in a resin substrate of the upper-layer semiconductor device to be stacked. Even if warpage occurs in the semiconductor element mounting region in the above, by forcibly suppressing from the upper surface, when stacking the upper and lower semiconductor devices, there is no inflection point and the warpage is reduced, so that the stacking is excellent in mountability Type semiconductor device can be provided.
[Selection] Figure 1

Description

  The present invention relates to a stacked semiconductor device in which a plurality of semiconductor devices on which semiconductor elements are mounted are stacked.

  In recent years, in semiconductor devices, SiP (system in package) that accommodates a plurality of semiconductor elements in one semiconductor device and PoP (package on package) that accommodates a plurality of semiconductor devices in combination with miniaturization and thinning. Such stacked semiconductor devices are emerging. On the other hand, with the advancement of functions and multifunctions of semiconductor elements, it has become a major technical issue how to achieve a reduction in size and thickness as a semiconductor device.

  In a stacked semiconductor device, a thin substrate of about 0.3 mm and a thin wafer of 0.2 mm or less are used because of demands for miniaturization and thinning. Therefore, warpage tends to occur in general, and the upper and lower packages including initial reliability are caused by the warpage. There is a problem that the connectivity and mounting properties on a printed circuit board are reduced.

  On the other hand, for example, the diameter of the electrode opening provided in the carrier substrate of the upper and lower semiconductor devices is decreased in order from the central portion to the outer peripheral portion so that the solder electrodes between the upper and lower portions of the stacked package can follow the warp. A setting method has been proposed (see, for example, Patent Document 1).

  However, the above method is effective when the upper and lower semiconductor devices are stacked, and the influence is suppressed by absorbing the warp due to the height change from the central part to the outer peripheral part of the solder electrode, thereby suppressing the upper and lower semiconductor devices. The devices can be joined, but when mounting them on a printed circuit board, problems remain in their mountability. At the time of mounting on the printed circuit board, the solder connection terminals between the upper and lower semiconductor devices are melted again, so that the warpage behavior of the lower layer semiconductor device directly affects the warpage behavior of the stacked semiconductor device. In general, the chip mounting part warps in the concave direction when the solder is melted (around 220 ° C.) and is cooled thereafter, and the upper and lower connection terminals solidify, but at that time, the vicinity of the chip mounting part is cooled to room temperature and convex Have warping to. In other words, at room temperature, there are concave directions near the upper and lower connection terminals, and there are different warping directions in the convex direction in the vicinity of the chip mounting part. , Had a problem that the mountability decreased.

On the other hand, as another problem of the conventional form, there is no connection between the upper and lower sides of the heat conduction of the upper and lower semiconductor devices other than the connection terminals, and in particular, there are few heat dissipation paths from the semiconductor elements of the lower layer semiconductor device. . In particular, a semiconductor device with high power consumption is often mounted in a lower layer semiconductor device, but there is a limit to a space for mounting a heat radiating plate or a heat radiating fin on the upper part of the device. In addition, since a variety of memories are mounted on the stacked semiconductor device as an upper package, the heat dissipation of the stacked semiconductor is worse than that obtained by adding the upper and lower semiconductor devices individually. Had.
JP 2004-289002 A

  SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a stacked semiconductor device that has no warping inflection point and reduces warping when stacking upper and lower semiconductor devices and has excellent mountability.

  To achieve the above object, a stacked semiconductor device according to claim 1 of the present invention is a stacked semiconductor device in which a plurality of semiconductor devices are stacked, and at least one of the stacked semiconductor devices. One or a plurality of warp-suppressing connection terminals are formed in a region facing a semiconductor element mounted on the semiconductor device, which is a lower layer of the semiconductor devices to be stacked, on the substrate of the two semiconductor devices, and the lower layer is stacked Even if warpage occurs in the substrate of the semiconductor device, the warpage suppressing connection terminal is in contact with the semiconductor element, thereby suppressing warpage of the substrate of the underlying semiconductor device.

  The stacked semiconductor device according to claim 2 is a stacked semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, the first semiconductor device being a substrate of the first semiconductor device. A first semiconductor element mounted on one surface of the first substrate, a plurality of first external connection terminals formed on the other surface of the first substrate, and the first A first connection electrode formed on the first semiconductor element mounting surface on the substrate, a second substrate to be a substrate of the second semiconductor device, and mounted on one surface of the second substrate A second semiconductor element, a plurality of second connection terminals formed on the other surface of the first substrate and connected to the first connection electrode, and the other of the first substrate. One or a plurality of warp suppressing connection terminals formed in a region facing the first semiconductor element on the surface; Even when the first substrate is warped during the stacking, the warp suppressing connection terminal is in contact with the first semiconductor element, thereby suppressing the warp of the first substrate. Features.

  The stacked semiconductor device according to claim 3 is the stacked semiconductor device according to claim 2, wherein a height of the warp suppressing connection terminal is lower than a height of the second connection terminal. To do.

  The stacked semiconductor device according to claim 4 is the stacked semiconductor device according to claim 3, wherein the warp suppressing connection terminal has a height lower than that of the second connection terminal, and the first substrate surface. The height from the first semiconductor element to the upper surface of the first semiconductor element is lower.

  The stacked semiconductor device according to claim 5 is a solder on a second substrate provided for forming the warp suppressing connection terminal in the stacked semiconductor device according to claim 3. The resist opening area is larger than the solder resist opening area on the second substrate provided for forming the second connection terminal.

  The multilayer semiconductor device according to claim 6 is the multilayer semiconductor device according to claim 2, claim 3, claim 4, or claim 5, wherein the warp suppressing connection terminal has a terminal diameter of the multilayer semiconductor device. It is smaller than the terminal diameter of the second connection terminal.

  The stacked semiconductor device according to claim 7 is the stacked semiconductor device according to claim 2, claim 3, claim 4, claim 5, or claim 6, wherein An Sn—Ag—Bi—In solder material is used, and an Sn—Ag—Cu solder material is used for the second connection terminal.

  The stacked semiconductor device according to claim 8 is the stacked semiconductor device according to claim 2, claim 3, claim 4, claim 5, or claim 6, wherein A solder material of Sn-3Ag-0.5Cu is used, and a solder material of Sn-3.5Ag-0.75Cu is used for the second connection terminal.

  The stacked semiconductor device according to claim 9 is the stacked semiconductor device according to claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, or claim 8. At least one of the warp suppressing connection terminals is joined to the first semiconductor element.

  As described above, when the upper and lower semiconductor devices are stacked, there is no warp inflection point and the warpage is reduced, and the mountability of the stacked semiconductor device can be improved.

  The present invention provides a semiconductor element in a lower-layer semiconductor device after melting of solder by providing a connection terminal for warpage suppression in a region facing a semiconductor element mounted on a lower-layer semiconductor device in a substrate of an upper-layer semiconductor device to be stacked. Even if warping occurs in the mounting area, it is forcibly suppressed from the upper surface, and when the upper and lower semiconductor devices are stacked and completed, there is no inflection point and the warpage is reduced, so that the stacked semiconductor device has excellent mountability. Can be provided.

  In addition, by connecting the external connection terminal of the upper semiconductor device to the upper surface of the semiconductor element mounted on the lower semiconductor device, the heat radiation from the lower semiconductor device is promoted, and the stacked semiconductor device with improved heat dissipation is obtained. Can be provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that the thickness, length, quantity, and the like of each member shown in the drawings may differ from the actual ones in creating the drawing. The same members are denoted by the same reference numerals, and description thereof may be omitted.
(Embodiment 1)
FIG. 1 is a diagram showing a stacked semiconductor device according to the first embodiment of the present invention.

  1A is a second semiconductor device, 1 is a semiconductor element, 2 is a resin substrate, FIG. 1B is a first semiconductor device, and 3 is an external connection terminal. In the method of mounting the semiconductor element 1 on the resin substrate 2 in the figure, the electric circuit surface of the semiconductor element 1 is made to face the resin substrate 2 surface, and the upper electrode 5 of the semiconductor element 1 and the substrate of the resin substrate 2 by the electrode protrusion 4 Although the flip chip connection method for electrically connecting the electrode 6 is illustrated, the present invention is not limited to this, and the surface opposite to the electric circuit surface of the semiconductor element 1 is mounted on the resin substrate 2, and the circuit electrode is formed by a wire such as gold. It is also possible to use a wire bonding method for joining the substrate electrode 6 and the circuit surface separately with a resin later.

  The manufacturing method of the first and second semiconductor devices is not different from that of a general semiconductor device. First, the semiconductor element 1 is mounted on the resin substrate 2, and the element upper electrode 5 and the substrate electrode 6 are bonded via the electrode protrusion 4. FIG. 1 shows an example of the flip-chip connection described above. Bonding to the connection electrode formed on the resin substrate 2 of the second semiconductor device by melting the connection terminals 7 called solder balls on the lower surface of the second semiconductor device through reflow at a high temperature of 220 ° C. or higher. It is. Furthermore, the second connection terminal 8 used for suppressing warpage is similarly melted and bonded to the lower surface of the resin substrate 2 of the second semiconductor device through reflow at a high temperature of 220 ° C. or higher. In FIG. 1C, the first and second semiconductor devices thus manufactured and configured are stacked. During the lamination, the first and second semiconductor devices are mounted so that the lamination connection electrodes 17 and the lamination connection terminals 7 correspond to each other, and the lamination connection terminals 7 are melted and bonded through reflow to form a lamination state. This is a stacked semiconductor device.

  In the present embodiment, as will be described later, the second connection used for suppressing warpage in a region facing the semiconductor element mounted on the second semiconductor device when the first semiconductor device is laminated on the back surface of the resin substrate. Terminal 8 is formed. Thereby, the warp of the semiconductor element mounting region of the first semiconductor device is forcibly suppressed by the second connection terminal provided there coming into contact with the upper surface of the semiconductor element of the first semiconductor device. be able to.

Next, the mechanism will be described in detail with reference to FIG.
FIG. 2 is a schematic diagram of the warping behavior of the stacked semiconductor device according to the first embodiment of the present invention.
In FIG. 2, FIG. 2A is a schematic diagram showing, as an example, warpage when the solder is melted in the stacked semiconductor device, and FIG. 2B is a diagram illustrating the conventional stacked semiconductor device to room temperature after subsequent solder solidification. The schematic diagram of the curvature at the time of returning is shown. After solidification, the semiconductor element mounting region tends to return in the convex direction as shown in FIG. In an example of flip chip connection with a 150 μm thick chip and a substrate thickness of 0.3 mm, the return amount is about 100 μm, and as a result in the completed state, a recess of 70-80 μm is formed on the bottom surface. On the other hand, in the stacked semiconductor device of the present embodiment, the second connection is made in the region facing the semiconductor element mounted on the first semiconductor device on the surface facing the first semiconductor device in the second semiconductor device. Since the terminal 8 is provided and the second connection terminal 8 in the semiconductor element mounting region is in contact with the semiconductor element mounted on the first semiconductor device, such warpage can be forcibly suppressed. At the time of melting the solder, the stacked semiconductor device as shown in FIG. 2C is a semiconductor device with little warpage and having no local dent on the bottom as shown in FIG. Can be provided. Therefore, the mountability of the stacked semiconductor device on the printed board can be ensured. In the above description, the structure in which the second connection terminal 8 is in contact with the semiconductor element mounted on the first semiconductor device is described. However, when the semiconductor element mounted on the first semiconductor device is sealed with resin. The second connection terminal 8 is in contact with the resin upper surface, and the configuration is not limited by this drawing.

  Further, in the present embodiment, FIG. 3 is a diagram showing a stacked semiconductor device having different connection terminal heights in the first embodiment of the present invention, FIG. 3A is a second semiconductor device, and FIG. (B) has shown the completed state after lamination | stacking.

  As shown in FIG. 3, the height of the second connection terminal 8 arranged on the lower surface of the resin substrate 2 of the second semiconductor device may be lower than the connection terminal 7 for lamination. Furthermore, in the state after lamination, even if the difference 9 in connection height is a distance 10 or more between the upper surface of the semiconductor element, which is the upper surface of the first semiconductor device, and the resin base material of the first semiconductor device. good.

  Since the height of the second connection terminal 8 is lower than the connection terminal 7 for stacking, the second connection terminal 8 is disposed on the lower surface of the resin substrate 2 of the second semiconductor device when the first and second semiconductor devices are stacked and connected. Since the connection terminal 7 for laminating in the peripheral region of the semiconductor element contacts the first semiconductor device or has the tendency before the second connection terminal 8 is in contact with the upper surface of the first semiconductor device, The second connection terminal 8 provided is brought into contact with the upper surface of the semiconductor element of the first semiconductor device, so that the connection between the stacking connection terminal 7 and the first semiconductor device is prevented from being minimized. can do. In addition, when the first and second semiconductor devices are stacked, the warp generated in the semiconductor element mounting region of the first semiconductor device after the connection terminal 7 for stacking is melted and solidified is provided there. The second connection terminal 8 can be forcibly suppressed by contacting the upper surface of the semiconductor element of the first semiconductor device.

Further, FIG. 4 is a diagram showing a stacked semiconductor device having different solder resist opening areas in the first embodiment of the present invention.
As shown in FIG. 4, the solder resist opening area 12 on the resin substrate 2 of the second semiconductor device in which the second connection terminals 8 are arranged is the second semiconductor in which the lamination connection terminals 7 are arranged. It may be larger than the solder resist opening area 13 on the resin substrate 2 of the apparatus.

  Since the solder resist opening area 12 is larger than the solder resist opening area 13, the connection terminal 7 for laminating and the second connection terminal 8 have the same configuration, the same size, and the same volume in the initial stage before the reflow melting. For example, after melting, it can be evenly connected to the opening and the height can be controlled by the difference in the bottom area. Therefore, the thickness of the second connection terminal 8 can be reduced at a low cost only by changing the wiring (opening) pattern of the resin substrate 2.

Further, FIG. 5 is a diagram showing stacked semiconductor devices having different connection terminal diameters according to the first embodiment of the present invention.
As shown in FIG. 5, the connection terminal diameter 14 of the second connection terminal 8 may be smaller than the connection terminal diameter 15 of the connection terminal 7 for lamination.

  Since the connection terminal diameter 14 of the second connection terminal 8 is smaller than the connection terminal diameter 15 of the connection terminal 7 for lamination, the solder ball as the second connection terminal 8 is different from the solder ball of the connection terminal 7 for lamination. In addition, since the size of the second connection terminal 8 used in the semiconductor element mounting region is made smaller than the normal terminal size, the terminal size of the connection terminal 7 for stacking can be set to a normal size. Even if an infrastructure such as an inspection socket matched to the size of a connection terminal electrically connected at the time of shipping inspection of the second semiconductor device is used, insertion into the socket has no problem in size. Therefore, the second semiconductor device can be inspected without particularly increasing the cost, and the thickness of the second connection terminal corresponding to the semiconductor element mounting region of the first semiconductor device can be reduced.

  Further, although not shown (see FIGS. 1 to 5 for the shape), the second connection terminal 8 is an Sn—Ag—Bi—In based solder material, and the lamination connection terminal 7 is a general Sn—Ag—Cu based. The solder material may be used. As an example, a combination of Sn-3.5Ag-0.5Bi-8In and Sn3Ag0.5Cu is also effective from the viewpoint of feasibility.

  By using a Sn—Ag—Bi—In solder material for the second connection terminal 8 and a general Sn—Ag—Cu solder material for the lamination connection terminal 7, the melting point of the second connection terminal 8 is reduced. Since the melting point of the connection terminal 7 is lower, when the solder is melted when the first and second semiconductor devices are stacked, the second connection terminal 8 is melted first, and then the connection terminal 7 is melted. First, solidification starts from the connection terminal 7 for lamination. Therefore, after the terminal connection of the stacking connection terminals 7 in the peripheral region of the semiconductor element to be electrically connected is completed, the warp suppression of the semiconductor element mounting region portion of the first semiconductor device is suppressed there. The connection terminal of the first semiconductor device can be brought into contact with the upper surface of the element mounting portion of the first semiconductor device, and the warp as the final finished product is good without affecting the stacked connection of the first and second semiconductor devices. Can be.

  Further, although not shown (see FIGS. 1 to 5 for the shape), the second connection terminal 8 is Sn-3Ag-0.5Cu solder material, and the lamination connection terminal 7 is Sn-3.5Ag-0. .75Cu solder material may be used.

By using a solder material of Sn-3Ag-0.5Cu for the second connection terminal 8 and a solder material of Sn-3.5Ag-0.75Cu for the connection terminal 7 for lamination, in this case, the second connection terminal 8, the melting point of the connection terminal 7 for lamination becomes higher. That is, in any case, the relationship that the melting point of the second connection terminal 8 is lower than that of the connection terminal 7 for laminating remains unchanged. In the former case, the melting point is lowered by changing the material of the second connection terminal 8. On the other hand, in this case, the material of the connection terminal 7 for lamination is changed to increase its melting point. With the above configuration, when the solder is melted when the first and second semiconductor devices are stacked, the second connection terminal 8 is melted first, and then the stacking connection terminal 7 is melted. Start with region. Therefore, after the connection of the stacking connection terminals 7 in the peripheral region of the semiconductor element to be electrically connected is completed, the warp suppression of the semiconductor element mounting region portion of the first semiconductor device is suppressed there. By connecting the connection terminal 8 to the upper surface of the element mounting portion of the first semiconductor device, it is possible to improve the warp as the final finished product without affecting the stacked connection of the first and second semiconductor devices. it can.
(Embodiment 2)
Next, Embodiment 2 will be described with reference to FIG.

  FIG. 6 is a diagram showing a stacked semiconductor device according to the second embodiment of the present invention. This embodiment is different from FIG. 1C of the first embodiment in that the second connection terminal 8 is the first one. The only difference is whether it is connected to the upper surface of the semiconductor element mounted on the semiconductor device and whether the land 11 for connection is provided on the upper surface of the semiconductor element mounted on the first semiconductor device. is there.

  At least one of the second connection terminals 8 is bonded to the upper surface of the semiconductor element mounted on the first semiconductor device. For this purpose, a connection land 11 in which NiAu plating or the like is applied to a land of AlCu or the like is provided on the upper surface of the semiconductor element, and the two connection terminals 8 are joined by alloying with solder melting of the second connection terminal 8. . Due to this configuration, heat dissipation from the first semiconductor device is transmitted to the second semiconductor device through the second connection terminal 8 provided in the second semiconductor device, and is promoted.

  At this time, the first semiconductor device and the second semiconductor device may be electrically connected via the land 11 and the second connection terminal 8, or the connection may be a connection provided only for heat dissipation. good.

  Further, the second connection terminal 8 corresponding to the corresponding portion is connected to a terminal 16 connected to a wiring layer having a large Cu foil area, such as a GND terminal, in the second semiconductor device, so that heat dissipation is further promoted. Is done.

  In the above description, the case where two semiconductor devices are stacked has been described. However, among the stacked semiconductor devices in which two or more semiconductor devices are stacked, a configuration in which the second connection terminal is used in a part or all of the stacked portions. It is also possible.

  In the present invention, when stacking upper and lower semiconductor devices, there is no warp inflection point, warpage is reduced, and mountability can be improved. Useful for.

The figure which shows the laminated semiconductor device in Embodiment 1 of this invention Schematic diagram of the warping behavior of the stacked semiconductor device in the first embodiment of the present invention The figure which shows the laminated semiconductor device from which the height of the connecting terminal in Embodiment 1 of this invention differs The figure which shows the laminated semiconductor device from which the soldering resist opening area in Embodiment 1 of this invention differs The figure which shows the laminated semiconductor device from which the connection terminal diameter in Embodiment 1 of this invention differs The figure which shows the laminated semiconductor device in Embodiment 2 of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Resin substrate 3 External connection terminal 4 Electrode protrusion 5 Element upper electrode 6 Substrate electrode 7 Lamination connection terminal 8 Second connection terminal 9 Height difference 10 Distance 11 Land 12 Solder resist opening area 13 Solder resist opening area 14 connection terminal diameter 15 connection terminal diameter 16 terminal 17 connection electrode for lamination

Claims (9)

A stacked semiconductor device in which a plurality of semiconductor devices are stacked,
One or a plurality of warp-suppressing connection terminals in a region facing a semiconductor element mounted on the semiconductor device, which is a lower layer of the semiconductor device to be stacked, in a substrate of at least one of the semiconductor devices to be stacked Even when the substrate of the underlying semiconductor device is warped during stacking, the warpage suppressing connection terminal comes into contact with the semiconductor element, thereby warping the substrate of the underlying semiconductor device. A laminated semiconductor device characterized by suppressing the above. A stacked semiconductor device in which a second semiconductor device is stacked on a first semiconductor device,
A first substrate to be a substrate of the first semiconductor device;
A first semiconductor element mounted on one surface of the first substrate;
A plurality of first external connection terminals formed on the other surface of the first substrate;
A first connection electrode formed on the first semiconductor element mounting surface on the first substrate;
A second substrate to be a substrate of the second semiconductor device;
A second semiconductor element mounted on one surface of the second substrate;
A plurality of second connection terminals formed on the other surface of the first substrate and connected to the first connection electrode;
The first substrate has one or a plurality of warp-suppressing connection terminals formed in a region facing the first semiconductor element on the other surface of the first substrate, and the first substrate is warped during lamination. Even if it occurs, the warp of the first substrate is suppressed by the warp suppressing connection terminal being in contact with the first semiconductor element.   The stacked semiconductor device according to claim 2, wherein a height of the warp suppressing connection terminal is lower than a height of the second connection terminal.   The height of the warp suppressing connection terminal is lower than the second connection terminal and lower than the height from the first substrate surface to the upper surface of the first semiconductor element. Multilayer semiconductor device.   The solder resist opening area on the second substrate provided for forming the warp suppressing connection terminal is larger than the solder resist opening area on the second substrate provided for forming the second connection terminal. The stacked semiconductor device according to claim 3, wherein   6. The stacked type according to claim 2, wherein the terminal diameter of the warp suppressing connection terminal is smaller than the terminal diameter of the second connection terminal. Semiconductor device.   3. The Sn-Ag-Bi-In solder material is used for the warp suppressing connection terminal, and the Sn-Ag-Cu solder material is used for the second connection terminal. The stacked semiconductor device according to claim 3, claim 4, claim 5, or claim 6.   3. A solder material of Sn-3Ag-0.5Cu is used for the warp suppressing connection terminal, and a solder material of Sn-3.5Ag-0.75Cu is used for the second connection terminal. Alternatively, the stacked semiconductor device according to claim 3, claim 4, claim 5, or claim 6.   The at least one of the warp suppressing connection terminals is bonded to the first semiconductor element. The claim 2, the claim 3, the claim 4, the claim 5, the claim 6, the claim 7, or the claim Item 9. A stacked semiconductor device according to any one of Items 8 to 10.

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