JP2009054684A - Semiconductor POP equipment - Google Patents

Abstract

A semiconductor POP device that avoids breakage of solder microcontacts during semiconductor lamination is provided.
A semiconductor POP device 200 is mainly composed of semiconductor packages 210 and 220 having a plurality of solder microcontacts and a solder material 230 for soldering and connecting the solder microcontacts. Each semiconductor package 210, 220 has substrates 211, 221 and chips 212, 222 placed on the substrate. The solder microcontacts of the lower semiconductor package 210 are located on the plurality of upper layer bumps 213 on the upper surface 211A of the substrate 211, and the solder microcontacts of the upper semiconductor package 220 are located on the plurality of lower layer bumps 223 on the lower surface 221B of the substrate 221. To do. The lower bumps 223 are respectively aimed at the upper bumps 213 so that the upper bumps 213 and the lower bumps 223 are joined by the solder material 230, and soldering is performed uniformly.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor POP device having a high-density structure in which a plurality of semiconductor packages are three-dimensionally stacked, and more particularly to a semiconductor POP device that avoids breakage of solder microcontacts during semiconductor stacking.

In recent years, with the miniaturization of printed circuit boards corresponding to the demand for miniaturization of electronic products, the area for storing electronic elements on the substrate surface has also been reduced. Conventionally, a plurality of semiconductor packages are arranged in parallel, and the size in the lateral direction is increased so as to be directly bonded to the printed circuit board, so that it is impossible to achieve downsizing.
In order to solve such problems, it is possible to realize a small and high-density structure in which a plurality of semiconductor packages are stacked three-dimensionally in the vertical direction, that is, an apparatus called POP (Package-On-Package). Conventionally, electrical continuity has been established between both semiconductor packages via a solder ball or a transfer board having solder material on the upper and lower surfaces. When solder balls are used, a tearing phenomenon appears, so that it is necessary to enlarge the solder balls, and there is a gap between the layers, which tends to cause problems such as solder ball short circuit (bridge) and solder material contamination. Solder balls within the interval cannot reach the requirements for solder microcontacts, limiting the number of leads and the wiring layout. On the other hand, when the transfer board is employed, a storage tank having an opening must be installed at the center of the transfer board, and a conduction hole is installed around the storage tank, resulting in an increase in cost.

Fujitsu has submitted a microcontact structure that can be applied to package stacking in Patent Document 1 and Tessera in Patent Document 2, respectively. As shown in FIG. 1, the conventional semiconductor POP device 100 mainly includes a first semiconductor package 110, a second semiconductor package 120, and a solder material 130. The second semiconductor package 120 is stacked on the first semiconductor package 110 and connects the semiconductor packages 110 and 120 with a solder material 130. The first semiconductor package 110 includes a first substrate 111, a first chip 112 installed on the upper surface 111A of the first substrate 111, and a plurality of bumps 113 formed on the lower surface 111B of the first substrate 111.
The plurality of first bonding wires 114 are used to electrically connect the bonding pads of the first chip 112 and the first substrate 111 through the first slots 111C of the first substrate 111, and the first bonding wires 114 group is first sealed. Sealed with the body 115.
Similar to the first semiconductor package 110, the second semiconductor package 120 is also formed on the second substrate 121, the second chip 122 installed on the upper surface 121A of the second substrate 121, and the lower surface 121B of the second substrate 121. A plurality of bumps 123 such as copper bumps and columnar bumps that cannot be reflowed. A plurality of second bonding wires 124 are used to electrically connect the second chip 122 and the second substrate 121 through the second slot 121C of the second substrate 121, and the second bonding wires 124 are sealed with the second sealing body 125. Stop.
A plurality of planar connection pads 111D are disposed on the upper surface 111A of the first substrate 111 of the first semiconductor package 110, and the bumps 123 of the second semiconductor package 120 and the corresponding connection pads 111D of the first semiconductor package 110 are soldered. It connects with the material 130, and becomes a form of a solder fine contact.
As described above, when the first semiconductor package 110 and the second semiconductor package 120 are stacked, the bump 123 group is used as a solder fine contact, whereby the number of signal leads can be increased and the wiring area can be increased. In addition, the gap in the POP stack can be reduced.
Since the shape and area of the solder joint are different, it is known that the solder joint strength does not coincide with the bump 123 group and the connection pad 111D group after reflow. In particular, the soldering surface of the connection pad 111D group is planar. Therefore, the resistance of the solder material 130 is relatively weak against the shear stress (that is, the thermal stress generated by the expansion and contraction of the first substrate 111).
Further, a Ni—Au plating layer is provided on the surface of the connection pad 111D group, and the Ni—Au layer melts and flows into the solder material 130, thereby causing a metal embrittlement phenomenon in the solder material 130 and a soldering contact surface. The strength of is even weaker. Therefore, in the conventional semiconductor POP device 100, in the environment where high-speed calculation or heat radiation is poor, the solder microcontact is easily torn at the contact surface between the connection pad 111D group and the solder or the surface of the bump 123 group.

US Patent No. 6,476,503 US Patent No. 2006/0138647

The main object of the present invention is to provide a semiconductor POP device that avoids breakage of solder microcontacts during semiconductor lamination, and to make solder microcontacts break during semiconductor lamination by equalizing the solder material joint shape and joint area. There is to avoid.
Another object of the present invention is to provide a semiconductor POP device that avoids breakage of solder microcontacts when stacking semiconductors, thereby enabling heat dissipation and maintaining a small interval.

The semiconductor POP device according to the present invention mainly includes a first semiconductor package, a second semiconductor package, and a plurality of solder materials.
The first semiconductor package includes a first substrate, a first chip, and a plurality of upper layer bumps, and the upper layer bump group and the first chip are disposed on an upper surface of the first substrate.
The second semiconductor package includes a second substrate, a second chip, and a plurality of lower layer bumps. The lower layer bump group is disposed on a lower surface of the second substrate, and the second chip is disposed on the second substrate. It is installed on the upper surface.
The solder material group is used for joining the upper layer bump and the lower layer bump.
The second semiconductor package is stacked above the first semiconductor package, and the lower bump group is aimed at the upper bump group and soldered evenly.

The first semiconductor package may further include a plurality of second lower layer bumps, and the second lower layer bumps are disposed on a lower surface of the first substrate.
In addition, a second solder material can be provided for covering the second lower bump.

The second semiconductor package may further include a plurality of second upper bumps, and the second upper bumps are disposed on the upper surface of the second substrate.
The first semiconductor package may further include a plurality of first bonding wires, the first substrate includes a first slot, and the first bonding wire passes through the first slot and the first chip and the first semiconductor package. The board is electrically connected.

The first semiconductor package may further include a first sealing body, and the first sealing body is formed in the first slot to seal the first bonding wire group.
The first sealing body may be exposed without covering the first chip.
Further, the second semiconductor package has a plurality of second bonding wires and a second sealing body, substantially like the first semiconductor package.

The lower bump group and the upper bump group may have the same size and outer shape.
The lower bump group and the upper bump group have a truncated cone shape or a cylindrical shape.
The lower layer bump group and the upper layer bump group may be copper pillars.

The second semiconductor package may have a plurality of dummy bumps, and the dummy bumps are disposed on a lower surface of the second substrate for heat dissipation and are located above the first chip of the first semiconductor package. ing.
The dummy bump group may contact the back surface of the first chip.
The solder material group may have an H-shaped soldering cross section.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
The semiconductor POP device 200 according to the first embodiment of the present invention mainly includes a first semiconductor package 210, a second semiconductor package 220, and a plurality of solder materials 230, as shown in FIG.
The first semiconductor package 210 includes a first substrate 211, a first chip 212, and a plurality of first upper layer bumps 213. The first upper layer bump 213 and the first chip 212 are disposed on the upper surface 211A of the first substrate 211. Is done. The first substrate 211 is a double-sided conductive substrate, for example, a printed circuit board. The first chip 212 is bonded to the upper surface 211 </ b> A of the first substrate 211 using a die attach adhesive, a tape with an adhesive, or a flip chip bump so that the active surface of the first chip 212 faces the first substrate 211.
In the first embodiment, the first substrate 211 has a first slot 211C, and the first slot 211C penetrates the upper surface 211A and the lower surface 211B of the first substrate 211. The first semiconductor package 210 may include a plurality of first bonding wires 215. The first bonding wires 215 are formed by a wire bonding method, and the plurality of first bonding pads of the first chip 212 are formed through the first slot 211C. 212A and the first substrate 211 are electrically connected.

The first semiconductor package 210 further includes a first sealing body 216, and the first sealing body 216 is formed in the first slot 211 </ b> C by molding or dispensing, and is formed in the first bonding wire 215. Seal the group. However, the first chip 212 is not covered by exposing the back surface of the first chip 212 for heat dissipation and package thinning.
The second semiconductor package 220 includes a second substrate 221, a second chip 222, and a plurality of first lower layer bumps 223. The first lower layer bump 223 group is disposed on the lower surface 221B of the second substrate 221, and the second chip. 222 is installed on the upper surface 221 </ b> A of the second substrate 221.

  Preferably, the second semiconductor package 220 includes a plurality of second bonding wires 225 and a second sealing body 226, substantially like the first semiconductor package 210. The second bonding wires 225 are sealed to the second sealing body 226 by electrically connecting the plurality of second bonding pads 222A of the second chip 222 and the second substrate 221 through the second slots 221C. In the first embodiment, the first semiconductor package 210 further has a plurality of second lower layer bumps 214, and these second lower layer bumps 214 are disposed on the lower surface 211 </ b> B of the first substrate 211. The second semiconductor package 220 further includes a plurality of second upper layer bumps 224, and these second upper layer bumps 224 are disposed on the upper surface 221 </ b> A of the second substrate 221.

  The solder material 230 group is used to join the first upper layer bump 213 group and the first lower layer bump 223 group. The second semiconductor package 220 is stacked on the first semiconductor package 210, and the first lower bumps 223 are aimed at the first upper bumps 213, respectively, and are soldered evenly. The solder material 230 group can use a lead-free solder material. For example, in the case of a solder material of 96.5% tin, 3% silver and 0.5% copper, the reflow temperature (about 217 ° C, the maximum temperature is about 245 ° C) This reaches the solder wettability. However, the first upper bumps 213 and the first lower bumps 223 always have a melting point higher than the reflow temperature.

As shown in FIG. 3, the first upper bump 213 group and the first lower bump 223 group can have the same size and outer shape, and the first upper bump 213 group and the first lower bump 223 group are truncated cones. It may be a connection bump formed in a wire shape or a cylindrical shape. The first upper layer bump 213 group and the first lower layer bump 223 group may be copper pillars or bumps that do not need to be reflowed. The first upper bump 213 group and the first lower bump 223 group are in a fine contact form, and the package window has a solder ball diameter of about 0, taking the conventional WindowBGA used by the DDR2 DRAM as an example. .45 mm, the connection pad opening of the substrate to be joined to the solder ball is about 0.35 mm-0.4 mm, and the standoff height after completing the SMT is about 0.3 mm.
In the first embodiment, the height of the first upper layer bump 213 group and the first lower layer bump 223 group is about 0.08 mm-0.15 mm, the bump top surface size is 0.06 mm or more, and the bump bottom surface The size is about 0.18 mm. The interval height after the first semiconductor package 210 and the second semiconductor package 220 are stacked is about 0.275 mm. In the first embodiment, since the distance between the solder balls and the bonding board connecting pad group can be further reduced, it is possible to meet the demand for high density and high number of terminals.

  The solder material 230 group shown in FIG. 3 has an H-shaped soldering cross section, so that the strengths of the upper and lower soldering are the same and the resistance to shear stress is relatively strong. In other words, the first upper bump 213 group and the first lower bump 223 group can have the same solder joint shape and area, so that it is possible to avoid tearing of the solder microcontacts during semiconductor lamination, and both sides. The board level reliability of the laminate can be increased.

  As shown in FIG. 4, the semiconductor POP device 200 may further include a second solder material 240 that covers the second lower bump 214, and the semiconductor POP device 200 includes the second solder material 240. It is joined to the external circuit board 10 via In addition, an appropriate amount of the second semiconductor package 220 can be optionally stacked again above the semiconductor POP device 200 in order to expand memory capacity and functions.

(Second embodiment)
As shown in FIG. 5, the semiconductor POP apparatus 300 according to the second embodiment of the present invention includes a first semiconductor package 310, a second semiconductor package 320, and a plurality of first solder materials 330. The first semiconductor package 310 includes a first substrate 311, a first chip 312, and a plurality of upper layer bumps 313, and the upper layer bump 313 and the first chip 312 are disposed on the upper surface 311 A of the first substrate 311. In the second embodiment, the first chip 312 is installed on the first substrate 311 using a flip chip bonding method.
The second semiconductor package 320 includes a second substrate 321, a second chip 322, and a plurality of lower layer bumps 323. These lower layer bumps 323 are disposed on the lower surface 321 </ b> B of the second substrate 321, and the second chip 322 includes the second chip 322. Two substrates 321 are installed on the upper surface 321A.

  The first solder material 330 joins the upper layer bump 313 group and the lower layer bump 323 group. The second semiconductor package 320 is laminated on the first semiconductor package 310, and the lower bumps 323 are aimed at the upper bumps 313 and soldered evenly. Preferably, the joining shape of the upper layer bump 313 group and the lower layer bump 323 group by soldering is a large U-shaped opening.

The first semiconductor package 310 may further include a plurality of lower layer bumps 314, and the lower layer bumps 314 are disposed on the lower surface 311 </ b> B of the first substrate 311. Further, the semiconductor POP device 300 further includes a second solder material 340 for covering the lower layer bump 314 group.
Preferably, the second semiconductor package 320 may have a plurality of dummy bumps 324, which are disposed on the lower surface 321 </ b> B of the second substrate 321 and above the first chip 312 of the first semiconductor package 310. Located in the role of heat dissipation. The dummy bumps 324 can contact the back surface of the first chip 312 so that heat can be dissipated and a minute interval can be maintained.
Although the present invention has been described based on the preferred embodiments thereof, the scope of protection of the present invention is limited by the scope of the claims, and on the basis of this scope of protection, how to touch the spirit and scope of the present invention. Various changes and modifications belong to the protection scope of the present invention.

It is sectional drawing of the conventional semiconductor POP apparatus. 1 is a cross-sectional view showing a semiconductor POP device according to a first embodiment of the present invention. In the semiconductor POP device according to the first embodiment of the present invention, FIG. 1 is a cross-sectional view showing a state in which a semiconductor POP device according to a first embodiment of the present invention is joined to an external circuit board by an assembly of a plurality of semiconductor packages. FIG. 6 is a cross-sectional view showing a semiconductor POP device according to a second embodiment of the present invention.

Explanation of symbols

  10: external circuit board, 200: semiconductor POP device, 210: first semiconductor package, 211: first substrate, 211A: upper surface, 211B: lower surface, 211C: first slot, 212: first chip, 212A: first 1 bonding pad, 213: first upper layer bump, 214: second lower layer bump, 215: first bonding wire, 216: first sealing body, 220: second semiconductor package, 221: second substrate, 221A: upper surface 221B: lower surface, 221C: second slot, 222: second chip, 222A: second bonding pad, 223: first lower layer bump, 224: second upper layer bump, 225: second bonding wire, 226: second Sealed body, 230: solder material, 240: second solder material, 300: semiconductor POP device, first semiconductor package, 311: first Plate, 311A: upper surface, 311B: lower surface, 312: first chip, 313: upper layer bump, 314: lower layer bump, 320: second semiconductor package, 321: second substrate, 321A: upper surface, 321B: lower surface 322: second chip, 323: lower bump, 324: dummy bump, 330: first solder material, 340: second solder material

Claims (23)

A first semiconductor package having a first substrate, a first chip and a plurality of upper layer bumps, wherein the upper layer bump and the first chip are disposed on an upper surface of the first substrate;
A second substrate having a second substrate, a second chip, and a plurality of lower bumps, wherein the lower bump is disposed on a lower surface of the second substrate, and the second chip is disposed on an upper surface of the second substrate; Package and
A plurality of solder materials that are used to join the upper layer bump group and the lower layer bump group, and are advantageous for soldering evenly by aiming the lower layer bump group to the upper layer bump group;
A semiconductor POP device characterized by comprising:   The semiconductor POP device according to claim 1, wherein the first semiconductor package further includes a plurality of second lower layer bumps, and the second lower layer bumps are disposed on a lower surface of the first substrate.   The semiconductor POP device according to claim 2, further comprising a second solder material for covering the second lower bump.   2. The semiconductor POP device according to claim 1, wherein the second semiconductor package has a plurality of second upper bumps, and the second upper bumps are disposed on an upper surface of the second substrate.   The first semiconductor package further includes a plurality of first bonding wires, the first substrate has a first slot, and the first bonding wire passes through the first slot, and the first chip, the first substrate, The semiconductor POP device according to claim 1, wherein the semiconductor POP devices are electrically connected.   6. The first semiconductor package includes a first sealing body, and the first sealing body is formed in the first slot to seal the first bonding wire group. The semiconductor POP device described.   6. The semiconductor POP device according to claim 5, wherein the first sealing body exposes the first chip.   8. The semiconductor POP device according to claim 6, wherein the second semiconductor package includes a plurality of second bonding wires and a second sealing body substantially similar to the first semiconductor package.   2. The semiconductor POP device according to claim 1, wherein the lower bump group has the same size and outer shape as the upper bump group.   2. The semiconductor POP device according to claim 1, wherein the lower layer bump group and the upper layer bump group have a truncated cone shape or a cylindrical shape.   2. The semiconductor POP device according to claim 1, wherein the lower bump group and the upper bump group are copper pillars.   The second semiconductor package has a plurality of dummy bumps, and the dummy bumps are disposed on a lower surface of the second substrate and are located above the first chip of the first semiconductor package and serve as heat dissipation. The semiconductor POP device according to claim 1.   The semiconductor POP device according to claim 12, wherein the dummy bump group is in contact with a back surface of the first chip.   The semiconductor POP device according to claim 1, wherein the solder material group has an H-shaped soldering section.   The semiconductor POP device according to claim 1, wherein the solder material group is a lead-free soldering agent.   A substrate, a chip, a plurality of lower layer bumps and a plurality of upper layer bumps, wherein the lower layer bump group is disposed on a lower surface of the substrate, and the upper layer bump group and the chip are disposed on an upper surface of the substrate; An upper layer bump group and the lower layer bump group have a similar solder joint shape and area, and have a plurality of semiconductor packages stacked on each other.   17. The semiconductor POP device according to claim 16, wherein a bonding shape of the upper bump group and the lower bump group by soldering is a large U-shaped opening.   17. The semiconductor package according to claim 16, wherein each of the semiconductor packages further includes a plurality of bonding wires, the substrate has a slot, and the bonding wire electrically connects the chip and the substrate through the slot. The semiconductor POP device described.   19. The semiconductor POP device according to claim 18, wherein each of the semiconductor packages further includes a sealing body, and the sealing body is formed in the slot and seals the bonding wire group.   The semiconductor POP device according to claim 19, wherein each of the sealing bodies exposes the chip.   17. The semiconductor POP device according to claim 16, wherein the lower bump group and the upper bump group have a truncated cone shape or a cylindrical shape.   The semiconductor POP device according to claim 16, wherein the lower layer bump group and the upper layer bump group are copper pillars.   17. The semiconductor POP device according to claim 16, wherein each semiconductor package has a plurality of dummy bumps, and the dummy bumps are installed on a lower surface of the substrate for heat dissipation.

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