JP2008252150A - Laminated chip varistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated chip varistor capable of reducing a mounting area. <P>SOLUTION: The laminated chip varistor V1 is provided with a varistor body 1, first outer electrodes 5, 6, and second outer electrodes 7, 8. The first outer electrodes 5, 6 are formed respectively on one main surface 2 of the varistor body 1. The second outer electrodes 7, 8 are formed respectively on the other main surface 3 of the varistor body 1. The varistor body 1 is constituted as a laminate, where a plurality of varistor layers exhibiting varistor characteristics are respectively laminated on a plurality of first inner electrodes 11 and second inner electrodes 21. Each of the first inner electrodes 11 is electrically connected to the first outer electrode 5 and the second outer electrode 7 through second electrode parts 15 and an outer conductor 37. Each of the second inner electrodes 21 is electrically connected to the first outer electrode 6 and the second outer electrode 8 through second electrode parts 25 and an external conductor 47. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer chip varistor and a method for manufacturing an electronic device including the multilayer chip varistor.

As this type of multilayer chip varistor, a varistor element having a varistor layer that exhibits voltage nonlinear characteristics and a pair of internal electrodes arranged so as to sandwich the varistor layer, and at both end portions of the varistor element A device including a pair of terminal electrodes that are located and connected to corresponding internal electrodes among a plurality of internal electrodes is known (for example, see Patent Document 1).
JP 2002-246207 A

  In recent years, ESD (Electrostatic Discharge) is used in various electric circuits in electronic devices such as DSC (Digital Still Camera), DVC (Digital Video Camera), PDA (Personal Digital Assistant), notebook personal computers or mobile phones. In order to protect from the above, a multilayer chip varistor is used as an ESD countermeasure component. The multilayer chip varistor is used in, for example, an LCD panel, a button unit, a battery terminal, a video I / O terminal, an audio I / O terminal, a headphone terminal, a keyboard terminal, a microphone unit, and the like.

  By the way, when a semiconductor light emitting element for illuminating the button part is arranged on the button part, static electricity may be applied to the button part due to contact with the human body. It is necessary to protect the semiconductor light emitting device. That is, it is necessary to connect a multilayer chip varistor to the semiconductor light emitting element in parallel, and to protect the semiconductor light emitting element from an ESD surge by the multilayer chip varistor connected in parallel.

  However, it is necessary to use a multilayer chip varistor for each button portion, that is, for each semiconductor light emitting element, and when a plurality of multilayer chip varistors are mounted, the mounting area of the multilayer chip varistor increases, and the electronic device described above It will be a factor that hinders downsizing.

  An object of the present invention is to provide a multilayer chip varistor capable of reducing the mounting area, and a method for manufacturing an electronic device including the multilayer chip varistor.

  A multilayer chip varistor according to the present invention includes a multilayer body including a varistor layer that exhibits voltage nonlinear characteristics, and a plurality of internal electrodes that are arranged to face each other so as to sandwich the varistor layer, and an outer surface of the multilayer body. A plurality of first external electrodes formed on one outer surface perpendicular to a direction opposite to each other and electrically connected to a corresponding one of the plurality of internal electrodes; A plurality of second external electrodes formed on the outer surface opposite to the outer surface on which one external electrode is formed and electrically connected to the corresponding internal electrode among the plurality of internal electrodes. It is characterized by.

  In the multilayer chip varistor according to the present invention, the plurality of first external electrodes are formed on one outer surface perpendicular to the direction in which the plurality of internal electrodes face each other among the outer surfaces of the multilayer body. The plurality of first external electrodes are electrically connected to the corresponding internal electrodes, respectively. Therefore, by mounting the outer surface on which the plurality of first external electrodes are formed facing the external substrate or the like, the multilayer chip varistor is mounted on the external substrate or the like.

  In the present invention, the plurality of second external electrodes are formed on the outer surface opposite to the outer surface on which the plurality of first external electrodes are formed. The plurality of second external electrodes are electrically connected to the corresponding internal electrodes, respectively. Therefore, the outer surface on which the second external electrode is formed functions as a mounting surface for mounting various electronic components such as a semiconductor light emitting element, and various electronic components are formed on the outer surface on which the plurality of second external electrodes are formed. Can be implemented. In this case, various electronic components are connected in parallel to the multilayer chip varistor.

  From the above, according to the present invention, the mounting area can be reduced when the multilayer chip varistor is mounted. In addition, mounting for electrically connecting various electronic components and the plurality of second external electrodes can be easily and simply performed.

  Preferably, the first and second external electrodes and the internal electrodes corresponding to the first and second external electrodes are electrically connected through a through-hole conductor formed in the multilayer body.

  Preferably, the through-hole conductor is composed of one or more metals selected from the group consisting of Pd, Ag, Cu, W, Mo, Sn and Ni, or an alloy containing one or more of the above metals. .

  Preferably, the first and second external electrodes and the internal electrodes corresponding to the first and second external electrodes are parallel to a direction in which the plurality of internal electrodes face each other on the outer surface of the stacked body. It is electrically connected through an outer conductor formed on the outer surface.

  Preferably, the outer conductor is composed of one or more metals selected from the group consisting of Pd, Ag, Cu, W, Mo, Sn and Ni, or an alloy containing one or more of the above metals.

  According to another aspect of the present invention, there is provided a method for manufacturing an electronic apparatus, comprising: preparing a plurality of aggregate substrates so that the multilayer chip varistors are arranged two-dimensionally; and providing each multilayer chip varistor formed so as to be two-dimensionally arranged. It is characterized in that each electronic component is mounted and the collective substrate is cut to obtain each multilayer chip varistor on which the electronic component is mounted.

  In the method for manufacturing an electronic device according to the present invention, a plurality of multilayer chip varistors are prepared in a two-dimensional array as a collective substrate. Therefore, when mounting electronic components, the plurality of multilayer chip varistors are aligned again. There is no need to let them. In addition, external electrodes are formed on each multilayer chip varistor, and the mounting position of the electronic device is determined in advance, which facilitates mounting of the electronic device. Of course, each of the obtained electronic devices is provided with the multilayer chip varistor, so that the mounting area can be reduced when mounting the multilayer chip varistor as described above.

  Preferably, the electronic component is a semiconductor light emitting element.

  According to the present invention, it is an object to provide a multilayer chip varistor capable of reducing the mounting area and a method of manufacturing an electronic device including the multilayer chip varistor.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

(First embodiment)
The configuration of the multilayer chip varistor V1 according to the first embodiment will be described with reference to FIGS. FIG. 1 is a top view showing the multilayer chip varistor according to the first embodiment. FIG. 2 is a bottom view showing the multilayer chip varistor according to the first embodiment. FIG. 3 is a view for explaining a cross-sectional configuration of the multilayer chip varistor according to the first embodiment. FIG. 4 is a diagram for explaining a cross-sectional configuration along the line IV-IV in FIG. 3.

  The multilayer chip varistor V1 includes a varistor element body 1 having a substantially rectangular parallelepiped shape, a plurality (a pair in the present embodiment) of first external electrodes 5 and 6, and a plurality (a pair in the present embodiment). Second external electrodes 7 and 8. The pair of first external electrodes 5 and 6 are respectively formed on one main surface (outer surface) 2 of the varistor element body 1. The pair of second external electrodes 7 and 8 are respectively formed on the other main surface (outer surface) 3 of the varistor element body 1. For example, the varistor element body 1 is set to have a length of about 1.0 mm, a width of about 0.8 mm, and a thickness of about 0.5 mm. One first external electrode 5 functions as an input terminal electrode of the multilayer chip varistor V1, and the other first external electrode 6 functions as an output terminal electrode of the multilayer chip varistor V1. The second external electrodes 7 and 8 function as pad electrodes that are electrically connected to an electronic component such as a semiconductor light emitting element.

  The varistor element body 1 includes a plurality of varistor layers that exhibit voltage nonlinear characteristics (hereinafter referred to as “varistor characteristics”), and a plurality of first internal electrodes 11 and second internal electrodes 21, respectively. It is comprised as a laminated body. The first internal electrode 11 and the second internal electrode 21 are arranged one by one in the varistor element body 1 along the stacking direction of the varistor layers (hereinafter simply referred to as “stacking direction”). The first internal electrode 11 and the second internal electrode 21 are arranged to face each other so that at least one varistor layer is sandwiched between them. The pair of main surfaces 2 and 3 of the varistor element body 1 face each other and are perpendicular to the stacking direction of the varistor layers, that is, the direction in which the first internal electrode 11 and the second internal electrode 21 face each other. In the actual multilayer chip varistor V1, the plurality of varistor layers are integrated so that the boundary between them cannot be visually recognized.

  The varistor layer contains ZnO (zinc oxide) as a main component and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, K) as subcomponents. Rb, Cs) and simple earth metals such as alkaline earth metal elements (Mg, Ca, Sr, Ba) and element bodies containing these oxides. In the present embodiment, the varistor layer contains Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. As a result, the region of the varistor layer that overlaps the first internal electrode 11 and the second internal electrode 21 contains ZnO as the main component and Pr.

  In the present embodiment, Pr is used as the rare earth metal. Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small. Although content of ZnO in a varistor layer is not specifically limited, When the whole material which comprises a varistor layer is 100 mass%, it is 99.8-69.0 mass% normally. The thickness of the varistor layer is, for example, about 20 to 30 μm.

  As shown in FIG. 4, the first internal electrode 11 includes a first electrode portion 13 and a second electrode portion 15. The first electrode portion 13 overlaps with a first electrode portion 23 of a second internal electrode 21 described later when viewed from the stacking direction. The first electrode portion 13 has a substantially rectangular shape. The second electrode portion 15 is drawn from the first electrode portion 13 and functions as a lead conductor. The second electrode portion 15 is formed integrally with the first electrode portion 13.

  Each second electrode portion 15 is physically and electrically connected to each other by a through-hole conductor 17. The through-hole conductor 17 is formed so as to extend in the stacking direction in the varistor element body 1. One end of the through-hole conductor 17 is physically and electrically connected to the first external electrode 5. The other end of the through-hole conductor 17 is physically and electrically connected to the second external electrode 7. Thereby, the first electrode portion 13 of each first internal electrode 11 is electrically connected to the first external electrode 5 and the second external electrode 7 through the second electrode portion 15 and the through-hole conductor 17. Will be.

  As shown in FIG. 4, the second internal electrode 21 includes a first electrode portion 23 and a second electrode portion 25. The first electrode portion 23 overlaps the first electrode portion 13 of the first internal electrode 11 when viewed from the stacking direction. The first electrode portion 23 has a substantially rectangular shape. The second electrode portion 25 is drawn from the first electrode portion 23 and functions as a lead conductor. The second electrode portion 25 is formed integrally with the first electrode portion 23.

  Each second electrode portion 25 is physically and electrically connected to each other by a through-hole conductor 27. The through-hole conductor 27 is formed extending in the laminating direction in the varistor element body 1. One end of the through-hole conductor 27 is physically and electrically connected to the first external electrode 6. The other end of the through-hole conductor 27 is physically and electrically connected to the second external electrode 8. Accordingly, the first electrode portion 23 of each second internal electrode 21 is electrically connected to the first external electrode 6 and the second external electrode 8 through the second electrode portion 25 and the through-hole conductor 27. Will be.

  The first and second internal electrodes 11 and 21 include a conductive material. Although it does not specifically limit as a electrically conductive material contained in the 1st and 2nd internal electrodes 11 and 21, It is preferable to consist of Pd or an Ag-Pd alloy. The thickness of the 1st and 2nd internal electrodes 11 and 21 is about 1-5 micrometers, for example. The through-hole conductors 17 and 27 include a conductive material. The conductive material contained in the through-hole conductors 17 and 27 is made of one or more metals selected from the group consisting of Pd, Ag, Cu, W, Mo, Sn and Ni, or an alloy containing one or more of the above metals. It is preferable. The diameter of the through-hole conductors 17 and 27 is, for example, about 10 to 200 μm.

  The first external electrode 5 and the first external electrode 6 are arranged on one main surface 2 of the varistor element body 1 with a predetermined interval in a direction perpendicular to the stacking direction of the varistor layers. . The first external electrodes 5 and 6 have a rectangular shape (in this embodiment, a rectangular shape). In the first external electrodes 5 and 6, for example, the length of each long side is set to about 600 μm, the length of each short side is set to about 300 μm, and the thickness is set to about 2 μm.

  The second external electrode 7 and the second external electrode 8 are arranged on the one main surface 3 of the varistor element body 1 with a predetermined interval in a direction perpendicular to the stacking direction of the varistor layers. . The second external electrodes 7 and 8 have a rectangular shape (in this embodiment, a rectangular shape). In the second external electrodes 7 and 8, for example, the length of each long side is set to about 600 μm, the length of each short side is set to about 300 μm, and the thickness is set to about 2 μm.

  The first external electrodes 5 and 6 and the second external electrodes 7 and 8 are transferred to the outer surface of the varistor element body 1 at a predetermined temperature (for example, about 700 ° C.) after transferring an electrode paste mainly composed of silver or the like. It is formed by baking and further electroplating. Ni / Au or the like can be used for electroplating.

  As described above, the first electrode portion 13 of the first internal electrode 11 and the first electrode portion 23 of the second internal electrode 21 overlap each other. Therefore, a region overlapping the first electrode portion 13 and the first electrode portion 23 in the varistor layer functions as a region that develops varistor characteristics. In the multilayer chip varistor V1 having the above-described configuration, the first electrode portion 13, the first electrode portion 23, and the region overlapping the first electrode portion 13 and the first electrode portion 23 in the varistor layer. One varistor portion is formed.

  As described above, in the first embodiment, the pair of first external electrodes 5 and 6 are formed on one main surface 2 of the varistor element body 1. The pair of first external electrodes 5 and 6 are electrically connected to the corresponding internal electrodes 11 and 21, respectively. Therefore, the multilayer chip varistor V1 is mounted on the external substrate or the like by mounting the main surface 2 on which the pair of first external electrodes 5 and 6 are formed facing the external substrate or the like. It becomes.

  In the first embodiment, the pair of second external electrodes 7 and 8 are formed on the other main surface 3 of the varistor element body 1. The pair of second external electrodes 7 and 8 are electrically connected to the corresponding internal electrodes 11 and 21, respectively. Therefore, the other main surface 3 of the varistor element body 1 functions as a mounting surface on which various electronic components such as a semiconductor light emitting element are mounted, and various electronic components can be mounted on the other main surface 3. In this case, various electronic components are connected in parallel to the multilayer chip varistor V1.

  From the above, according to the first embodiment, the mounting area can be reduced when mounting the multilayer chip varistor V1. Further, mounting for electrically connecting various electronic components and the pair of second external electrodes 7 and 8 can be easily and simply performed.

(Second Embodiment)
The configuration of the multilayer chip varistor V2 according to the second embodiment will be described with reference to FIGS. FIG. 5 is a top view showing the multilayer chip varistor according to the second embodiment. FIG. 6 is a bottom view showing the multilayer chip varistor according to the second embodiment. FIG. 7 is a view for explaining a cross-sectional configuration of the multilayer chip varistor according to the second embodiment. FIG. 8 is a diagram for explaining a cross-sectional configuration along the line VIII-VIII in FIG. 7.

  The multilayer chip varistor V2 includes a varistor element body 1, a pair of first external electrodes 5 and 6, and a pair of second external electrodes 7 and 8. The varistor element body 1 is configured as a stacked body in which a plurality of varistor layers and a plurality of first internal electrodes 11 and second internal electrodes 21 are stacked.

  As shown in FIG. 8, the first internal electrode 11 includes a first electrode portion 13 and a second electrode portion 15. Each second electrode portion 15 is physically and electrically connected to each other by an outer conductor 37. The outer conductor 37 is located at one end of the varistor element body 1. The outer conductor 37 is formed in a groove 38 formed at one end of the varistor element body 1 so as to extend along the stacking direction. Thus, the outer conductor 37 is formed to extend along the stacking direction, and is parallel to the direction in which the first inner electrode 11 and the second inner electrode 21 face each other on the outer surface of the varistor element body 1. It will be formed on the outer surface.

  One end of the external conductor 37 is physically and electrically connected to the first external electrode 5. The other end of the external conductor 37 is physically and electrically connected to the second external electrode 7. Thus, the first electrode portion 13 of each first internal electrode 11 is electrically connected to the first external electrode 5 and the second external electrode 7 through the second electrode portion 15 and the external conductor 37. The Rukoto.

  As shown in FIG. 8, the second internal electrode 21 includes a first electrode portion 23 and a second electrode portion 25. Each second electrode portion 25 is physically and electrically connected to each other by an outer conductor 47. The outer conductor 47 is located at the other end of the varistor element body 1. The outer conductor 47 is formed in a concave groove 48 formed at the other end of the varistor element body 1 so as to extend along the stacking direction. Thereby, the outer conductor 47 is formed extending along the stacking direction, and is parallel to the direction in which the first inner electrode 11 and the second inner electrode 21 face each other on the outer surface of the varistor element body 1. It will be formed on the outer surface.

  One end of the external conductor 47 is physically and electrically connected to the first external electrode 6. The other end of the external conductor 47 is physically and electrically connected to the second external electrode 8. Thereby, the first electrode portion 23 of each second internal electrode 21 is electrically connected to the first external electrode 6 and the second external electrode 8 through the second electrode portion 25 and the external conductor 47. The Rukoto.

  The outer conductors 37 and 47 include a conductive material. The conductive material contained in the outer conductors 37 and 47 is made of one or more metals selected from the group consisting of Pd, Ag, Cu, W, Mo, Sn and Ni, or an alloy containing one or more of the above metals. Is preferred. The width of the concave grooves 38 and 48 is, for example, about 100 to 300 μm. The depth of the concave grooves 38 and 48 is, for example, about 50 to 150 μm.

  As described above, according to the second embodiment, the mounting area can be reduced when mounting the multilayer chip varistor V2 as in the first embodiment. Further, mounting for electrically connecting various electronic components and the pair of second external electrodes 7 and 8 can be easily and simply performed.

(Third embodiment)
The configuration of the multilayer chip varistor V3 according to the third embodiment will be described with reference to FIGS. FIG. 9 is a top view showing the multilayer chip varistor according to the third embodiment. FIG. 10 is a bottom view showing the multilayer chip varistor according to the third embodiment. FIG. 11 is a diagram for explaining a cross-sectional configuration along the line XI-XI in FIG. 9. FIG. 12 is a diagram for explaining a cross-sectional configuration along the line XII-XII in FIG. 11.

  The multilayer chip varistor V3 includes a varistor element body 1, a pair of first external electrodes 5 and 6, and a pair of second external electrodes 7 and 8. The varistor element body 1 is configured as a stacked body in which a plurality of varistor layers and a plurality of first internal electrodes 11 and second internal electrodes 21 are stacked.

  The first internal electrode 11 includes a first electrode portion 13 and a second electrode portion 15 as shown in FIG. Each of the second electrode portions 15 is physically and electrically connected to each other by external conductors 37 at both ends thereof. The external conductors 37 are respectively located at one end of the varistor element body 1. One end of the external conductor 37 is physically and electrically connected to the first external electrode 5. The other end of the external conductor 37 is physically and electrically connected to the second external electrode 7. Thus, the first electrode portion 13 of each first internal electrode 11 is electrically connected to the first external electrode 5 and the second external electrode 7 through the second electrode portion 15 and the external conductor 37. The Rukoto.

  The second internal electrode 21 includes a first electrode portion 23 and a second electrode portion 25 as shown in FIG. Each second electrode portion 25 is physically and electrically connected to each other by an external conductor 47 at both ends thereof. The external conductors 47 are respectively located at the other end of the varistor element body 1. One end of the external conductor 47 is physically and electrically connected to the first external electrode 6. The other end of the external conductor 47 is physically and electrically connected to the second external electrode 8. Thereby, the first electrode portion 23 of each second internal electrode 21 is electrically connected to the first external electrode 6 and the second external electrode 8 through the second electrode portion 25 and the external conductor 47. The Rukoto.

  As described above, according to the third embodiment, the mounting area can be reduced when the multilayer chip varistor V3 is mounted as in the first and second embodiments described above. Further, mounting for electrically connecting various electronic components and the pair of second external electrodes 7 and 8 can be easily and simply performed.

(Fourth embodiment)
The configuration of the multilayer chip varistor V4 according to the fourth embodiment will be described with reference to FIGS. FIG. 13 is a top view showing the multilayer chip varistor according to the fourth embodiment. FIG. 14 is a view for explaining a cross-sectional configuration of the multilayer chip varistor according to the fourth embodiment.

  The multilayer chip varistor V4 is the same as the multilayer chip varistor V1 shown in FIGS. 1 to 4, the varistor element body 1, the pair of first external electrodes 5, 6, and the pair of second external electrodes 7. , 8 are provided. The varistor element body 1 is configured as a stacked body in which a plurality of varistor layers and a plurality of first internal electrodes 11 and second internal electrodes 21 are stacked.

  The first internal electrode 11 includes a first electrode portion 13 and a second electrode portion 15 as shown in FIG. Each of the second electrode portions 15 is physically and electrically connected to each other by through-hole conductors 17 at both ends thereof. Thereby, like the multilayer chip varistor V1 shown in FIGS. 1 to 4, the first electrode portion 13 of each first internal electrode 11 passes through the second electrode portion 15 and the through-hole conductor 17 to The first external electrode 5 and the second external electrode 7 are electrically connected.

  As shown in FIG. 14, the second internal electrode 21 includes a first electrode portion 23 and a second electrode portion 25. Each second electrode portion 25 is physically and electrically connected to each other by through-hole conductors 27 at both ends thereof. Thereby, like the multilayer chip varistor V1 shown in FIGS. 1 to 4, the first electrode portion 23 of each second internal electrode 21 passes through the second electrode portion 25 and the through-hole conductor 27 and passes through the first electrode portion 23. The first external electrode 6 and the second external electrode 8 are electrically connected.

  As described above, according to the fourth embodiment, the mounting area can be reduced when the multilayer chip varistor V4 is mounted, as in the first to third embodiments described above. Further, mounting for electrically connecting various electronic components and the pair of second external electrodes 7 and 8 can be easily and simply performed.

  Next, an example in which the multilayer chip varistors V1 to V4 according to the present embodiment on which the semiconductor light emitting element 51 is mounted is mounted on the circuit board 61 will be described with reference to FIGS. FIG. 15 is a perspective view showing a state in which a multilayer chip varistor on which a semiconductor light emitting element is mounted is mounted on a circuit board. FIG. 16 is a top view showing a state in which a multilayer chip varistor on which a semiconductor light emitting element is mounted is mounted on a circuit board.

  The semiconductor light emitting element 51 is mounted on the other main surface 3 of the varistor element body 1 so as to be connected in parallel with the multilayer chip varistor V1. Since the multilayer chip varistor V1 is thus connected in parallel to the semiconductor light emitting element 51, the semiconductor light emitting element 51 can be protected from an ESD surge. As a method for mounting the semiconductor light emitting element 51, methods such as soldering, bonding with a conductive adhesive, bump bonding, and the like can be used.

  The semiconductor light emitting element 51 is, for example, a GaN (gallium nitride) semiconductor light emitting diode (LED). GaN-based semiconductor LEDs are well-known and will not be described. The semiconductor light emitting element 51 includes a terminal electrode 53 electrically connected to a cathode electrode (not shown) and a terminal electrode 55 electrically connected to an anode electrode (not shown). The terminal electrode 53 is electrically and physically connected to the second external electrode 7. The terminal electrode 55 is electrically and physically connected to the second external electrode 8.

  Although a GaN-based semiconductor LED is used as the semiconductor light emitting element 51, the present invention is not limited to this. As the semiconductor light emitting element 51, for example, a nitride semiconductor LED other than GaN-based (for example, InGaNAs-based semiconductor LED), a compound semiconductor LED other than nitride-based, or a laser diode (LD) may be used. .

  The multilayer chip varistor V1 is mounted with the main surface 2 on which the pair of first external electrodes 5 and 6 are formed facing the circuit board 61. As a mounting method of the multilayer chip varistor V1, techniques such as soldering, bonding with a conductive adhesive, and bump bonding can be used. The circuit board 61 is formed with a pair of lands 63 and 65 corresponding to a pair of first external electrodes 5 and 6 (both not shown). The first external electrode 5 is electrically and physically connected to the land 63. The first external electrode 6 is electrically and physically connected to the land 65.

  By the way, the semiconductor light emitting element 51 emits heat during the light emitting operation. When the semiconductor light emitting element 51 becomes high temperature, the light emitting operation is affected. For this reason, it is necessary to dissipate the generated heat efficiently. In the multilayer chip varistor V1, since the first external electrodes 5 and 6 and the second external electrodes 7 and 8 are physically connected by the through-hole conductors 17 and 27, the through-hole conductors 17 and 27 dissipate heat. It becomes a path and heat generated in the semiconductor light emitting element 51 can be effectively released. As described above, in the multilayer chip varistor V1, when an electronic component that generates heat, such as the semiconductor light emitting device 51, is mounted, heat dissipation from the electronic component can be performed more efficiently.

  In the mounting example described above, the multilayer chip varistor V1 according to the first embodiment is used as the multilayer chip varistor. However, the present invention is not limited to this. As the multilayer chip varistor, any of the multilayer chip varistors V2 to V4 according to the second to fourth embodiments may be used.

  In the multilayer chip varistors V2 and V3, since the first external electrodes 5 and 6 and the second external electrodes 7 and 8 are physically connected by the external conductors 37 and 47, the external conductors 37 and 47 dissipate heat. It becomes a path and heat generated in the semiconductor light emitting element 51 can be effectively released. As described above, in the multilayer chip varistors V2 and V3, similarly to the multilayer chip varistors V1 and V4, when mounting an electronic component that generates heat like the semiconductor light emitting element 51, the heat radiation from the electronic component is further reduced. It can be done efficiently.

  Next, with reference to FIGS. 17-19, the manufacturing method of the multilayer chip varistor V1-V4 in which the semiconductor light-emitting device 51 was mounted is demonstrated. 17 to 19 are schematic views for explaining a method for manufacturing a multilayer chip varistor on which a semiconductor light emitting element is mounted.

  First, as shown in FIG. 17, a collective substrate 71 formed so that the multilayer chip varistors V1 are two-dimensionally arranged is prepared.

  The collective substrate 71 is obtained by laminating and firing a plurality of green sheets or the like on which electrode patterns corresponding to the internal electrodes 11 and 21 (not shown) are formed. The external electrodes 5 to 8 (only the second external electrodes 7 and 8 are illustrated) may be formed simultaneously with the firing of the green sheet or after the firing of the green sheet.

  The through-hole conductors 17 and 27 are formed by forming through holes in a plurality of stacked green sheets, filling the formed through holes with a conductive material (conductive paste), and simultaneously firing the green sheets. Also good. The through-hole conductors 17 and 27 may be formed by forming through holes in a plurality of stacked and fired green sheets, filling a conductive material (conductive paste), and baking. Alternatively, a plurality of green sheets on which conductor patterns corresponding to the through-hole conductors 17 and 27 are previously formed may be stacked and fired.

  Next, as shown in FIG. 18, the semiconductor light emitting element 51 is placed on each of the two-dimensionally arranged stacked chip varistors V1, and the second external electrodes 7 and 8 and the terminal electrodes 53 and 55 are physically and electrically connected. Implement to connect to each. As described above, techniques such as soldering, bonding with a conductive adhesive, bump bonding, and the like can be used for mounting the multilayer chip varistor V1.

  Next, as shown in FIG. 19, the collective substrate 71 is cut along the cutting line CL to obtain each stacked chip varistor V1 on which the semiconductor light emitting elements 51 are mounted.

  As described above, according to the manufacturing method described above, a plurality of stacked chip varistors V1 are prepared in a two-dimensional array as the collective substrate 71. There is no need to realign the chip varistor V1. In addition, since the second external electrodes 7 and 8 are formed in each multilayer chip varistor V1, and the mounting position of the semiconductor light emitting element 51 is determined in advance, it is easy to mount the semiconductor light emitting element 51. Become. Of course, since the obtained light emitting device is provided with the multilayer chip varistor V1, the mounting area can be reduced when the multilayer chip varistor V1 is mounted as described above.

  In the manufacturing method shown in FIGS. 17 to 19, the multilayer chip varistor formed on the collective substrate 71 is the multilayer chip varistor V <b> 1 according to the first embodiment, but is not limited thereto. The multilayer chip varistor formed on the collective substrate 71 may be the multilayer chip varistor V4 according to the fourth embodiment.

  Next, an example in which the multilayer chip varistor formed on the collective substrate 71 is the multilayer chip varistor V2 according to the second embodiment will be described with reference to FIG.

  In the collective substrate 71, conductor portions 73 corresponding to the external conductors 37 and 47 are formed. Each conductor portion 73 may be formed by forming a through hole in a plurality of stacked green sheets, filling the formed through hole with a conductive material (conductive paste), and simultaneously firing the green sheet. . Each conductor portion 73 may be formed by forming through holes in a plurality of laminated and fired green sheets, filling a conductive material (conductive paste), and baking. Moreover, you may form by laminating | stacking and baking the some green sheet in which the conductor pattern corresponding to each conductor part 73 was formed previously.

  Each conductor portion 73 is divided into two, an outer conductor 37 and an outer conductor 47, by cutting the collective substrate 71 along the cutting line. That is, the collective substrate 71 is cut so that each conductor portion 73 is divided into two.

  Next, an example in which the multilayer chip varistor formed on the collective substrate 71 is the multilayer chip varistor V3 according to the third embodiment will be described with reference to FIG.

  On the collective substrate 71, conductor portions 75 corresponding to the external conductors 37 and conductor portions 77 corresponding to the external conductors 47 are formed. Each of the conductor portions 75 and 77 is formed by forming through holes in a plurality of stacked green sheets, filling the formed through holes with a conductive material (conductive paste), and simultaneously firing the green sheets. Also good. The conductor portions 75 and 77 may be formed by forming through holes in a plurality of stacked and fired green sheets, filling a conductive material (conductive paste), and baking. Moreover, you may form by laminating | stacking and baking the some green sheet in which the conductor pattern corresponding to each conductor part 75 and 77 was formed previously.

  Each conductor portion 75 is divided into two outer conductors 37 by cutting the collective substrate 71 along a cutting line. Each conductor portion 77 is divided into two outer conductors 47 by cutting the collective substrate 71 along the cutting line. That is, the collective substrate 71 is cut so that each of the conductor portions 75 and 77 is divided into two.

  The electronic components mounted on the multilayer chip varistors V1 to V4 are not limited to the semiconductor light emitting element 51.

1 is a top view showing a multilayer chip varistor according to a first embodiment. It is a bottom view which shows the multilayer chip varistor concerning 1st Embodiment. It is a figure for demonstrating the cross-sectional structure of the multilayer chip varistor which concerns on 1st Embodiment. It is a figure for demonstrating the cross-sectional structure along the IV-IV line in FIG. It is a top view which shows the multilayer chip varistor concerning 2nd Embodiment. It is a bottom view which shows the multilayer chip varistor concerning 2nd Embodiment. It is a figure for demonstrating the cross-sectional structure of the multilayer chip varistor which concerns on 2nd Embodiment. It is a figure for demonstrating the cross-sectional structure along the VIII-VIII line in FIG. It is a top view which shows the multilayer chip varistor concerning 3rd Embodiment. It is a bottom view which shows the multilayer chip varistor concerning 3rd Embodiment. It is a figure for demonstrating the cross-sectional structure along the XI-XI line in FIG. It is a figure for demonstrating the cross-sectional structure along the XII-XII line | wire in FIG. It is a top view which shows the multilayer chip varistor concerning 4th Embodiment. It is a figure for demonstrating the cross-sectional structure of the multilayer chip varistor which concerns on 4th Embodiment. It is a perspective view which shows the state which mounted the multilayer chip varistor in which the semiconductor light-emitting device was mounted in the circuit board. It is a top view which shows the state which mounted the multilayer chip varistor in which the semiconductor light-emitting device was mounted in the circuit board. It is a schematic diagram for demonstrating the manufacturing method of the multilayer chip varistor in which the semiconductor light-emitting device was mounted. It is a schematic diagram for demonstrating the manufacturing method of the lamination type chip varistor in which the semiconductor light-emitting device was mounted. It is a schematic diagram for demonstrating the manufacturing method of the multilayer chip varistor in which the semiconductor light-emitting device was mounted. It is a schematic diagram for demonstrating the manufacturing method of a multilayer chip | tip varistor. It is a schematic diagram for demonstrating the manufacturing method of a multilayer chip | tip varistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Varistor element | base_body, 2, 3 ... Main surface, 5, 6 ... 1st external electrode, 7, 8 ... 2nd external electrode, 11 ... 1st internal electrode, 17 ... Through-hole conductor, 21 ... 1st 2 internal electrodes, 27 through-hole conductors, 37 and 47 external conductors, 51 semiconductor light emitting elements, 61 circuit boards, 71 collective substrates, V1 to V4 multilayer chip varistors.

Claims (6)

A laminate having a varistor layer that exhibits voltage non-linear characteristics, and a plurality of internal electrodes that are arranged to face each other so as to sandwich the varistor layer;
A plurality of outer electrodes formed on only one outer surface perpendicular to a direction in which the plurality of internal electrodes face each other, and electrically connected to corresponding ones of the plurality of internal electrodes. A first external electrode of
A plurality of second electrodes formed only on an outer surface opposite to the outer surface on which the plurality of first external electrodes are formed and electrically connected to corresponding internal electrodes among the plurality of internal electrodes. An external electrode,
The first and second external electrodes and the internal electrodes corresponding to the first and second external electrodes are externally parallel to a direction in which the plurality of internal electrodes face each other on the outer surface of the laminate. Electrically connected through an outer conductor formed on the surface,
The multilayer chip varistor is characterized in that the external conductor is formed in a concave groove formed so as to extend along the direction in which the plurality of internal electrodes face each other at an end of the multilayer body.   The outer conductor is composed of one or more metals selected from the group consisting of Pd, Ag, Cu, W, Mo, Sn, and Ni, or an alloy containing one or more of the metals. The multilayer chip varistor according to claim 1.   The plurality of internal electrodes include a first electrode portion facing each other with the varistor layer interposed therebetween, and a second electrode portion electrically and physically connected to each other by the external conductor. The multilayer chip varistor according to claim 1.   4. The multilayer chip varistor according to claim 3, wherein the second electrode portion is wider than the external electrode.   The external conductor that electrically connects the first external electrode and the internal electrode corresponding to the first external electrode, and the internal electrode corresponding to the second external electrode and the second external electrode 2. The multilayer chip varistor according to claim 1, wherein there are a plurality of external conductors that electrically connect each other. 2. The multilayer chip varistor according to claim 1, wherein the first and second external electrodes are formed by performing electroplating after baking an electrode paste. 3.

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