JP2000277380A - Multi-layer type multilayer ceramic capacitor - Google Patents
Multi-layer type multilayer ceramic capacitorInfo
- Publication number
- JP2000277380A JP2000277380A JP11081134A JP8113499A JP2000277380A JP 2000277380 A JP2000277380 A JP 2000277380A JP 11081134 A JP11081134 A JP 11081134A JP 8113499 A JP8113499 A JP 8113499A JP 2000277380 A JP2000277380 A JP 2000277380A
- Authority
- JP
- Japan
- Prior art keywords
- internal electrode
- ceramic capacitor
- layer
- multilayer ceramic
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】
【課題】 内部電極と外部電極との接続の信頼性を確保
し、隣合う外部電極どうしの短絡を防止し、有効層と内
部電極との隙間からメッキ液の浸入を防ぎ、各積層セラ
ミックコンデンサの絶縁抵抗の劣化を防止した信頼性の
高い多連型積層セラミックコンデンサを提供することを
目的とするものである。
【解決手段】 同一平面に複数の並設したクビレ部5a
を有する内部電極4aと、有効層としての誘電体セラミ
ック層を交互に複数層積層し、単一素体内部に並列方向
に所定間隔を置いて複数個の積層セラミックコンデンサ
11a〜11dを並設した多連型積層セラミックコンデ
ンサにおいて、前記内部電極4aを一個おきにその長手
方向に千鳥状に配置すると共に、内部電極4aのクビレ
部5aの端部を一個おきに交互に素体の相対向する外側
面9にそれぞれ露出させ、露出させた端部全体を覆うよ
うにして電気的に接続する複数対の外部電極10aを形
成する。
[57] [Abstract] [Problem] To secure the reliability of connection between an internal electrode and an external electrode, prevent short circuit between adjacent external electrodes, and prevent intrusion of plating solution from the gap between the effective layer and the internal electrode. It is another object of the present invention to provide a highly reliable multi-layer ceramic capacitor in which the insulation resistance of each multilayer ceramic capacitor is prevented from deteriorating. SOLUTION: A plurality of parallel concave portions 5a on the same plane.
, And a plurality of dielectric ceramic layers as effective layers are alternately laminated, and a plurality of laminated ceramic capacitors 11a to 11d are juxtaposed at predetermined intervals in a parallel direction inside a single element body. In the multiple-layered multilayer ceramic capacitor, every other one of the internal electrodes 4a is arranged in a staggered manner in the longitudinal direction, and the ends of the concave portions 5a of the internal electrodes 4a are alternately opposed to each other. A plurality of pairs of external electrodes 10a which are respectively exposed on the side surfaces 9 and are electrically connected to each other so as to cover the entire exposed end portions are formed.
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【発明の属する技術分野】本発明は積層セラミックコン
デンサを単一素体内に複数個形成した多連型積層セラミ
ックコンデンサに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor in which a plurality of multilayer ceramic capacitors are formed in a single body.
【0002】[0002]
【従来の技術】従来の多連型積層セラミックコンデンサ
27について、図を用いて説明する。2. Description of the Related Art A conventional multiple-layer ceramic capacitor 27 will be described with reference to the drawings.
【0003】図11は従来の多連型積層セラミックコン
デンサ27用のグリーンブロック21の展開斜視図、図
12は同グリーンブロック21の斜視図、図13は同多
連型積層セラミックコンデンサ27用のグリーンチップ
23の斜視図、図14は同多連型積層セラミックコンデ
ンサ27の完成品の部分切欠き斜視図、図15は同多連
型積層セラミックコンデンサ27の完成品の平断面図で
ある。図において17はグリーンシート、18は上部無
効層、19は下部無効層、20は内部電極、22は切断
線、24は外側面、25は外部電極、26a〜26dは
積層セラミックコンデンサを示す。FIG. 11 is an exploded perspective view of a conventional green block 21 for a multiple-layer ceramic capacitor 27, FIG. 12 is a perspective view of the same green block 21, and FIG. FIG. 14 is a partially cutaway perspective view of a completed product of the multiple-layer ceramic capacitor 27, and FIG. 15 is a plan sectional view of a completed product of the multiple-layer ceramic capacitor 27. In the figure, 17 is a green sheet, 18 is an upper ineffective layer, 19 is a lower ineffective layer, 20 is an internal electrode, 22 is a cutting line, 24 is an outer surface, 25 is an external electrode, and 26a to 26d are multilayer ceramic capacitors.
【0004】先ず、公知の積層セラミックコンデンサの
製造方法を用い、誘電体セラミックからなるグリーンシ
ート17を作製する。次に、作製したグリーンシート1
7を複数枚積層し上部無効層18と下部無効層19を作
製する。First, a green sheet 17 made of a dielectric ceramic is manufactured by using a known method of manufacturing a multilayer ceramic capacitor. Next, the prepared green sheet 1
7 are stacked to form an upper ineffective layer 18 and a lower ineffective layer 19.
【0005】次いで、下部無効層19面にグリーンシー
ト17を積層し、その上面に図11に示すように第一層
目の内部電極20を印刷した後、その上にグリーンシー
ト17を積層し第一層目の有効層とする。続いて、その
面に第一層の内部電極20と対になる第二層目の内部電
極20を所定寸法ずらして印刷し、更にその上にグリー
ンシート17を積層し第二層目の有効層とする。また更
に、その面に第二層目の内部電極20と対になる第一層
目と同じ第三層目の内部電極20を印刷し、その上にグ
リーンシート17を積層し第三層目の有効層とする。続
いて更に、その上面に第二層目と同じ内部電極20を印
刷した後、その上にグリーンシート17を積層する。こ
のようにしてグリーンシート17、内部電極20を順次
交互に複数層積層した後、最後に上部無効層18を重ね
て加圧積層して図12に示すグリーンブロック21を作
製する。[0005] Next, a green sheet 17 is laminated on the lower invalid layer 19 surface, and a first layer of internal electrodes 20 is printed on the upper surface thereof as shown in FIG. 11, and then the green sheet 17 is laminated thereon. This is the first effective layer. Subsequently, a second-layer internal electrode 20 that is to be paired with the first-layer internal electrode 20 is printed on the surface with a predetermined displacement, and a green sheet 17 is further laminated thereon to form a second-layer effective layer. And Furthermore, the same third-layer internal electrode 20 as the first-layer electrode that is to be paired with the second-layer internal electrode 20 is printed on that surface, and a green sheet 17 is laminated thereon to form a third-layer internal electrode 20. An effective layer. Subsequently, after the same internal electrode 20 as the second layer is printed on the upper surface, the green sheet 17 is laminated thereon. After a plurality of green sheets 17 and internal electrodes 20 are sequentially and alternately stacked in this manner, the upper ineffective layer 18 is finally stacked under pressure to manufacture a green block 21 shown in FIG.
【0006】作製したグリーンブロック21を切断線2
2に沿って切断、分離し図13に示すグリーンチップ2
3とした後、所定温度で焼成し焼結体(図示せず)を作
製する。得られた焼結体にバレル研磨を行い、焼結体の
内部に形成した各内部電極20の一方の端部を焼結体の
相対向する外側面24に露出させた後、露出させた各内
部電極20群を覆うように外部電極25となるペースト
を塗布し、焼付けを行い、更に焼付けた外部電極25面
にメッキ処理を施し、図14に示すように四個の積層セ
ラミックコンデンサ26a〜26dを単一素体内に並設
した多連型積層セラミックコンデンサ27を完成させ
る。[0006] The green block 21 is cut along the cutting line 2.
2 along the green chip 2 shown in FIG.
After that, firing is performed at a predetermined temperature to produce a sintered body (not shown). The obtained sintered body was subjected to barrel polishing, and one end of each of the internal electrodes 20 formed inside the sintered body was exposed to the opposite outer surface 24 of the sintered body. A paste for forming the external electrodes 25 is applied so as to cover the group of internal electrodes 20 and is baked. Further, the surface of the baked external electrodes 25 is plated, and the four laminated ceramic capacitors 26a to 26d are formed as shown in FIG. Are completed in a single body to complete a multi-layered multilayer ceramic capacitor 27.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、従来の
多連型積層セラミックコンデンサ27は、図15に示す
ように同一グリーンシート17面に並設した各内部電極
20はその一方の端部を多連型積層セラミックコンデン
サ27の同一外側面24に露出させ、露出させた端部全
体を覆うようにして外部電極25を形成する。従って隣
合う内部電極20の一方の端部が露出した外側面24は
積層セラミックコンデンサ26a〜26dを分離する有
効層どうしの密着面積が狭くなっており、露出した内部
電極20の端部全体を覆うように外部電極25を形成す
ると、隣合う外部電極25の間隔が狭くお互いが短絡し
たり、また完成品を回路基板に実装した際に、半田ブリ
ッジによる短絡が生じやすくなる。これを内部電極20
より狭く外部電極25を形成すると、外部電極25と内
部電極20の接続の信頼性を低下させると共に、外部電
極25の表面にメッキ処理を行う際に内部電極20と積
層セラミックコンデンサ26a〜26dを分離する有効
層の隙間からメッキ液が浸入し積層セラミックコンデン
サ26a〜26d間の絶縁抵抗を劣化させるという問題
があった。However, as shown in FIG. 15, in the conventional multi-layer monolithic ceramic capacitor 27, as shown in FIG. The external electrode 25 is formed so as to be exposed on the same outer surface 24 of the multilayer ceramic capacitor 27 and to cover the entire exposed end. Therefore, the outer surface 24 where one end of the adjacent internal electrode 20 is exposed has a narrow contact area between the effective layers separating the multilayer ceramic capacitors 26a to 26d, and covers the entire end of the exposed internal electrode 20. When the external electrodes 25 are formed as described above, the distance between the adjacent external electrodes 25 is narrow, and short-circuits occur between the external electrodes 25. Also, when the completed product is mounted on a circuit board, a short-circuit due to a solder bridge easily occurs. This is the internal electrode 20
When the external electrode 25 is formed more narrowly, the reliability of the connection between the external electrode 25 and the internal electrode 20 is reduced, and the internal electrode 20 and the multilayer ceramic capacitors 26a to 26d are separated when the surface of the external electrode 25 is plated. There is a problem that the plating solution infiltrates through the gaps between the effective layers and deteriorates the insulation resistance between the multilayer ceramic capacitors 26a to 26d.
【0008】本発明は前記従来の問題点を解決し、隣合
う積層セラミックコンデンサ間にメッキ液の浸入を防
ぎ、絶縁抵抗の劣化を防止し、しかも内部電極と外部電
極の接続の信頼性を確保し、外部電極間で短絡が生じな
い信頼性の高い多連型積層セラミックコンデンサを提供
することを目的とするものである。The present invention solves the above-mentioned conventional problems and prevents the intrusion of the plating solution between adjacent multilayer ceramic capacitors, prevents the insulation resistance from deteriorating, and ensures the reliability of the connection between the internal electrode and the external electrode. It is another object of the present invention to provide a highly reliable multilayer ceramic capacitor in which a short circuit does not occur between external electrodes.
【0009】[0009]
【課題を解決するための手段】前記目的を達成するため
に本発明は、同一平面に複数の並設したクビレ部を有す
る内部電極と有効層としての誘電体セラミック層を交互
に複数層積層し、単一素体内部に並列方向に所定間隔を
置いて複数個の積層セラミックコンデンサを並設した多
連型積層セラミックコンデンサにおいて、前記内部電極
を一個おきにその長手方向に千鳥状に配置すると共に、
内部電極のクビレ部の端部を一個おきに交互に素体の相
対向する外側面に端部を露出させ、露出させた端部全体
を覆うようにして複数対の外部電極を形成することによ
り、隣合う内部電極が露出した外側面では各積層セラミ
ックコンデンサを分離する有効層どうしの密着面積が広
くなり、しかも外部電極を露出させた内部電極のクビレ
部全体を覆うように形成するため、外部電極の幅が狭く
ても内部電極との接続の信頼性を確保し、しかも外部電
極の表面にメッキ処理を行う際に、クビレ部と各積層セ
ラミックコンデンサを分離する有効層の隙間からメッキ
液の浸入を防止することができるものである。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an internal electrode having a plurality of juxtaposed concave portions on the same plane and a dielectric ceramic layer as an effective layer which is alternately laminated in a plurality of layers. In a multiple-layer monolithic ceramic capacitor in which a plurality of monolithic ceramic capacitors are juxtaposed at predetermined intervals in a parallel direction inside a single element body, the internal electrodes are arranged in a staggered manner in the longitudinal direction every other one. ,
By alternately exposing the end portions of the crimped portion of the internal electrode to the opposite outer surfaces of the element body alternately, forming a plurality of pairs of external electrodes so as to cover the entire exposed end portion However, on the outer surface where the adjacent internal electrodes are exposed, the contact area between the effective layers separating the multilayer ceramic capacitors is increased, and furthermore, the external electrodes are formed so as to cover the entire crevices of the internal electrodes exposing the external electrodes. Even if the width of the electrode is narrow, the reliability of the connection with the internal electrode is ensured, and when plating the surface of the external electrode, the plating solution is removed from the gap between the cracked portion and the effective layer separating each multilayer ceramic capacitor. It can prevent intrusion.
【0010】[0010]
【発明の実施の形態】本発明の請求項1に記載の発明
は、同一平面に複数の並設したクビレ部を有する内部電
極と有効層としての誘電体セラミック層を交互に複数層
積層し、単一素体内部に並列方向に所定間隔を置いて複
数個の積層セラミックコンデンサを並設した多連型積層
セラミックコンデンサにおいて、前記内部電極を一個お
きにその長手方向に千鳥状に配置すると共に、内部電極
のクビレ部の端部を一個おきに交互に素体の相対向する
外側面にそれぞれ露出させ、露出させた端部全体を覆う
ようにして電気的に接続する複数対の外部電極を形成し
た構成であり、これにより隣合う内部電極は交互にその
長手方向に千鳥状に配置され、そのクビレ部の端部を一
個おきに交互に素体の相対向する異なる外側面に露出さ
せ、露出したクビレ部の端部全体を覆うようにして外部
電極を形成するため、クビレ部が露出した外側面では隣
合う積層セラミックコンデンサを分離する有効層どうし
の密着面積が広くなり、形成する外部電極の幅を狭くし
ても内部電極との接続の信頼性を確保し、狭くすること
により隣合う外部電極間の短絡を防ぎ、しかも外部電極
の表面にメッキ処理を行う際に露出させたクビレ部と各
積層セラミックコンデンサを分離する有効層との隙間か
らメッキ液の浸入を防止することが可能となるという作
用を有するものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is characterized in that a plurality of internal electrodes having a plurality of juxtaposed concave portions on the same plane and a plurality of dielectric ceramic layers as effective layers are alternately laminated, In a multiple-layered multilayer ceramic capacitor in which a plurality of multilayer ceramic capacitors are juxtaposed at a predetermined interval in a parallel direction inside a single element body, the internal electrodes are arranged in a staggered manner in the longitudinal direction every other one, A plurality of pairs of external electrodes that are electrically connected to each other by alternately exposing the end portions of the crimp portion of the internal electrode to the opposing outer surfaces of the element body alternately and alternately so as to cover the entire exposed end portion With this configuration, the adjacent internal electrodes are alternately arranged in a staggered manner in the longitudinal direction, and the ends of the rib portions are alternately exposed alternately on different outer surfaces facing each other of the element body. Crap Because the external electrodes are formed so as to cover the entire end of the external electrode, the area of contact between the effective layers separating adjacent multilayer ceramic capacitors is increased on the outer surface where the crack portion is exposed, and the width of the external electrode to be formed is reduced. Even though the connection with the internal electrodes is ensured, the narrowing prevents short-circuiting between adjacent external electrodes, and furthermore, the cracked parts exposed during plating on the surface of the external electrodes and each multilayer ceramic This has the effect that it is possible to prevent the intrusion of the plating solution from the gap with the effective layer separating the capacitor.
【0011】本発明の請求項2に記載の発明は、外部電
極と接続する内部電極のクビレ部の幅寸法を、素体内部
に形成した内部電極の幅寸法より狭くした請求項1に記
載の多連型積層セラミックコンデンサであり、これによ
り内部電極のクビレ部の端部が露出した外側面では隣合
う各積層セラミックコンデンサを分離する有効層どうし
の密着面積が更に広くなり、外部電極どうしの短絡を防
止し、外部電極の表面にメッキ処理を行う際にメッキ液
の浸入を防止することが更に容易となる。According to a second aspect of the present invention, the width dimension of the concave portion of the internal electrode connected to the external electrode is smaller than the width dimension of the internal electrode formed inside the element body. This is a multiple-layered multilayer ceramic capacitor, which further increases the area of contact between the effective layers that separate adjacent multilayer ceramic capacitors on the outer surface where the end of the internal electrode crack is exposed, and short-circuits the external electrodes. This makes it easier to prevent the plating solution from entering when performing plating on the surface of the external electrode.
【0012】本発明の請求項3に記載の発明は、外部電
極の幅を素体の外側面に露出させた内部電極のクビレ部
の幅より広く形成した請求項1または請求項2に記載の
多連型積層セラミックコンデンサであり、これにより素
体の外側面に露出した内部電極のクビレ部端部の全体が
外部電極に覆われるため、隣合う積層セラミックコンデ
ンサを分離する有効層の隙間からメッキ液が浸入するの
を防止することが一層容易となる。According to a third aspect of the present invention, the width of the external electrode is formed to be wider than the width of the concave portion of the internal electrode exposed on the outer surface of the body. This is a multiple-layer ceramic capacitor, which covers the entire end of the internal electrode exposed on the outer surface of the element with the external electrode, so plating is performed from the gap between the effective layers that separate adjacent multilayer ceramic capacitors. It becomes easier to prevent the liquid from entering.
【0013】本発明の請求項4に記載の発明は、同一平
面に複数の並設した内部電極と有効層としての誘電体セ
ラミック層を交互に複数層積層し、単一素体内部に並列
方向に所定間隔を置いて複数個の積層セラミックコンデ
ンサを並設した多連型積層セラミックコンデンサにおい
て、前記内部電極を一個おきにその長手方向に千鳥状に
配置すると共に、内部電極の一方の端部を一個おきに交
互に素体の相対向する外側面に露出しない程度まで接近
させ、素体の外側面から内部電極の端部と交差する切込
溝を設け、この切込溝の内面に前記内部電極の端部と電
気的に接続するように外部電極を形成した多連型積層セ
ラミックコンデンサであり、これにより素体の外側面全
体は有効層で覆われ、その外側面から内部電極に向け内
部電極の端部と交差するように切込溝を設け、この切込
溝の内部のみに外部電極と内部電極の接続を確保するに
足りる面積の内部電極の端部を露出させるため、隣合う
積層セラミックコンデンサを分離する有効層どうしの密
着面積が更に広くなると共に、切込溝の内面に形成した
外部電極によって内部電極の露出部は完全に覆われ、内
部電極と外部電極との接続の信頼性を確保し、隣合う積
層セラミックコンデンサを分離する有効層と内部電極と
の隙間からメッキ液が浸入するのを確実に防止すること
が可能となると共に、隣合う外部電極間の間隔が広くな
り短絡の発生を防ぐことができる。According to a fourth aspect of the present invention, a plurality of internal electrodes and a plurality of dielectric ceramic layers as effective layers are alternately stacked on the same plane, and a plurality of internal electrodes are arranged in parallel in a single element body. In a multiple-layer ceramic capacitor in which a plurality of multilayer ceramic capacitors are juxtaposed at predetermined intervals, the internal electrodes are alternately arranged in a staggered manner in the longitudinal direction, and one end of the internal electrodes is Every other one is alternately approached to the extent that it is not exposed to the opposing outer surfaces of the element body, and a notch groove is provided to intersect the end of the internal electrode from the outer surface of the element body. This is a multiple-layered multilayer ceramic capacitor in which external electrodes are formed so as to be electrically connected to the ends of the electrodes. With this structure, the entire outer surface of the element body is covered with an effective layer, and the inner surface extends from the outer surface toward the internal electrode. Exchange with the end of the electrode In order to expose the end of the internal electrode having an area sufficient to secure the connection between the external electrode and the internal electrode only inside the cut groove, it is effective to separate adjacent multilayer ceramic capacitors. As the contact area between the layers further increases, the exposed portion of the internal electrode is completely covered by the external electrode formed on the inner surface of the cut groove, ensuring the reliability of the connection between the internal electrode and the external electrode, and adjoining It is possible to reliably prevent the plating solution from entering through the gap between the effective layer separating the multilayer ceramic capacitor and the internal electrode, and to increase the distance between adjacent external electrodes, thereby preventing a short circuit from occurring. it can.
【0014】本発明の請求項5に記載の発明は、各内部
電極の一方の端部に内部電極の幅より狭い引出部を設
け、この引出部を介して内部電極を素体の外側面に露出
させ、その露出部に対し素体の外側面から内部電極と交
差するように切込溝を設け、この切込溝の内面に内部電
極の端部と電気的に接続する外部電極を形成した請求項
4に記載の多連型積層セラミックコンデンサであり、こ
れにより内部電極を引出部を介して素体の外側面に露出
させているため、素体の外側面から内部電極の端部と交
差するように切込む切込溝の位置決めが容易になると共
に、切込溝を内部電極の端部と交差するように設けるた
め、その後の外部電極の形成で内部電極と外部電極の接
続が確実なものとなり、隣合う積層セラミックコンデン
サを分離する有効層と内部電極との隙間からメッキ液が
浸入するのを確実に防止することが可能となると共に、
隣合う外部電極間の間隔が広くなり短絡の発生を防ぐこ
とができる。According to a fifth aspect of the present invention, a lead portion narrower than the width of the internal electrode is provided at one end of each internal electrode, and the internal electrode is connected to the outer surface of the element body through the lead portion. The exposed portion was provided with a cut groove for the exposed portion so as to intersect the internal electrode from the outer surface of the element body, and an external electrode electrically connected to an end of the internal electrode was formed on the inner surface of the cut groove. The multilayer ceramic capacitor according to claim 4, wherein the internal electrode is exposed to the outer surface of the body through the lead portion, so that the outer electrode of the body crosses the end of the internal electrode from the outer surface of the body. In addition to making it easy to position the cut groove to be cut, the cut groove is provided so as to intersect with the end of the internal electrode, so that the connection of the internal electrode and the external electrode is ensured in the subsequent formation of the external electrode. Effective layer that separates adjacent multilayer ceramic capacitors With the plating liquid from the gap between the internal electrodes becomes possible to reliably prevent the intrusion,
The interval between adjacent external electrodes is widened, and the occurrence of a short circuit can be prevented.
【0015】本発明の請求項6に記載の発明は、切込溝
の幅を内部電極引出部より広くまた内部電極の幅よりも
狭く、その深さは内部電極の端部と交差するように設け
た請求項4または請求項5に記載の多連型積層セラミッ
クコンデンサであり、これにより切込溝内のみに形成さ
れる外部電極の幅は内部電極幅よりも狭く、隣合う積層
セラミックコンデンサの外部電極どうし間の距離を十分
広く確保できるため、多連型積層セラミックコンデンサ
を基板実装した際に隣合う外部電極どうし間での半田ブ
リッジによる短絡を防止すると共に、切込溝の幅を内部
電極の幅より狭く加工することで、内部電極と外部電極
の信頼性を確保し、しかもメッキ液の浸入をより確実に
防止することが可能となる。According to a sixth aspect of the present invention, the width of the cut groove is wider than the internal electrode lead portion and smaller than the width of the internal electrode, and the depth thereof intersects the end of the internal electrode. The multi-layered multilayer ceramic capacitor according to claim 4 or 5, wherein the width of the external electrode formed only in the cut groove is smaller than the width of the internal electrode. Since the distance between the external electrodes can be sufficiently wide, when a multiple-layer monolithic ceramic capacitor is mounted on a board, short circuits due to solder bridges between adjacent external electrodes are prevented, and the width of the cut groove is set to the internal electrode. By making the width narrower than the width, the reliability of the internal electrode and the external electrode can be ensured, and the intrusion of the plating solution can be more reliably prevented.
【0016】本発明の請求項7に記載の発明は、切込溝
の幅を隣合う切込溝どうしの間隔より狭くした請求項4
から請求項6のいずれか1つに記載の多連型積層セラミ
ックコンデンサであり、これにより切込溝内のみに形成
する外部電極は、隣合う外部電極どうし間との距離を十
分に広く確保でき、多連型積層セラミックコンデンサを
基板実装した際、隣合う外部電極どうし間の半田ブリッ
ジによる短絡を防止すると共に、切込溝の幅を狭く加工
することでメッキ液の浸入をより確実に防止することが
可能となる。According to a seventh aspect of the present invention, the width of the cut groove is smaller than the interval between adjacent cut grooves.
To the multi-layered multilayer ceramic capacitor according to any one of claims 1 to 6, whereby the external electrodes formed only in the cut grooves can secure a sufficiently large distance between adjacent external electrodes. When a multiple-layered multilayer ceramic capacitor is mounted on a board, short circuits due to solder bridges between adjacent external electrodes are prevented, and the width of the cut grooves is narrowed to more reliably prevent the penetration of plating solution. It becomes possible.
【0017】本発明の請求項8に記載の発明は、切込溝
の底部のコーナ部分を曲面状にした請求項4から請求項
7のいずれか1つに記載の多連型積層セラミックコンデ
ンサであり、これにより切込溝の底部のコーナ部分に確
実に外部電極用ペーストを塗布することができると共
に、コーナ部分に外部電極用ペーストを塗布した際に生
じやすい気泡の入り込みを抑制することが可能となり、
内部電極と外部電極の接続が確実となる。According to an eighth aspect of the present invention, there is provided a multi-layer monolithic ceramic capacitor according to any one of the fourth to seventh aspects, wherein a corner portion at the bottom of the cut groove is curved. With this, it is possible to apply the external electrode paste reliably to the corners at the bottom of the cut grooves, and it is possible to suppress the entry of air bubbles that are likely to occur when applying the external electrode paste to the corners Becomes
The connection between the internal electrode and the external electrode is ensured.
【0018】本発明の請求項9に記載の発明は、切込溝
の底面を内方に向け曲面状にした請求項4から請求項8
のいずれか1つに記載の多連型積層セラミックコンデン
サであり、これにより切込溝の底面に確実に外部電極用
ペーストを塗布することができ、内部電極と外部電極と
の接続が確実となる。According to a ninth aspect of the present invention, the bottom surface of the cut groove is curved inward toward the inside.
Wherein the paste for external electrodes can be reliably applied to the bottom surfaces of the cut grooves, and the connection between the internal electrodes and the external electrodes is ensured. .
【0019】(実施の形態)以下、本発明の一実施の形
態を図1から図10を用いて説明する。(Embodiment) An embodiment of the present invention will be described below with reference to FIGS.
【0020】図1は本発明のグリーンブロック6aの展
開斜視図、図2は同斜視図、図3はグリーンブロック6
aを切断したグリーンチップ8aの斜視図、図4は多連
型積層セラミックコンデンサ12aの完成品の部分切欠
き斜視図、図5は同完成品の平断面図、図6は内部電極
4bに引出部5bを設けたグリーンブロック6bを切断
したグリーンチップ8bの斜視図、図7は同グリーンチ
ップ8bの展開斜視図、図8は切込溝14を設けた多連
型積層セラミックコンデンサ12bの焼結体13の斜視
図、図9は同完成品の斜視図、図10は同完成品の平断
面図である。FIG. 1 is an exploded perspective view of a green block 6a of the present invention, FIG. 2 is a perspective view of the same, and FIG.
a is a cutaway perspective view of the green chip 8a, FIG. 4 is a partially cutaway perspective view of a finished product of the multiple-layered ceramic capacitor 12a, FIG. 5 is a plan sectional view of the finished product, and FIG. 7 is a perspective view of the green chip 8b obtained by cutting the green block 6b provided with the portion 5b, FIG. 7 is an exploded perspective view of the green chip 8b, and FIG. 9 is a perspective view of the completed product, and FIG. 10 is a plan sectional view of the completed product.
【0021】図において1はグリーンシート、2は上部
無効層、3は下部無効層、4a,4bは内部電極、5a
は内部電極4aのクビレ部、5bは内部電極4bの引出
部、6a,6bはグリーンブロック、7は切断線、8
a,8bはグリーンチップ、9は外側面、10a,10
bは外部電極、11a〜11hは積層セラミックコンデ
ンサ、12a,12bは多連型積層セラミックコンデン
サ、13は焼結体、14は切込溝、15は切込溝14の
コーナ部、16は切込溝14の底部を示す。In the drawing, 1 is a green sheet, 2 is an upper ineffective layer, 3 is a lower ineffective layer, 4a and 4b are internal electrodes, 5a
Is a concave portion of the internal electrode 4a, 5b is a lead portion of the internal electrode 4b, 6a and 6b are green blocks, 7 is a cutting line, 8
a and 8b are green chips, 9 is an outer surface, 10a and 10
b is an external electrode, 11a to 11h are multilayer ceramic capacitors, 12a and 12b are multiple type multilayer ceramic capacitors, 13 is a sintered body, 14 is a cut groove, 15 is a corner portion of a cut groove 14, and 16 is a cut. 4 shows the bottom of the groove 14;
【0022】先ず、誘電体セラミック粉末と、有機バイ
ンダー、可塑剤等からなるスラリーを用い、公知の積層
セラミックコンデンサの製造方法に従ってグリーンシー
ト1を作製する。次に、作製したグリーンシート1を複
数枚積層し上部無効層2と下部無効層3を作製する。First, a green sheet 1 is manufactured using a slurry comprising dielectric ceramic powder, an organic binder, a plasticizer, and the like, according to a known method for manufacturing a multilayer ceramic capacitor. Next, a plurality of the produced green sheets 1 are laminated to produce an upper invalid layer 2 and a lower invalid layer 3.
【0023】次いで、下部無効層3上にグリーンシート
1を積層し、その面に図1に示すような第一層目のクビ
レ部5aを有する内部電極4aを印刷する。各内部電極
4aは一個おきに交互に、その長手方向に千鳥状に配置
するように印刷する。その上にグリーンシート1を積層
し第一層目の有効層とする。Next, the green sheet 1 is laminated on the lower ineffective layer 3, and the internal electrode 4a having the first layer of the concave portion 5a as shown in FIG. Each of the internal electrodes 4a is printed alternately every other electrode so as to be arranged in a staggered manner in the longitudinal direction. A green sheet 1 is laminated thereon to form a first effective layer.
【0024】続いて、その面に第一層目の内部電極4a
と対になる第二層目の内部電極4aを第一層目の内部電
極4aの長手方向に所定寸法ずらして印刷し、また更に
その上にグリーンシート1を積層し第二層目の有効層と
する。続けて更に、その面に第二層目の内部電極4aと
対になる第一層目と同じ第三層目の内部電極4aを印刷
し、その上にグリーンシート1を積層し第三層目の有効
層とする。このようにしてグリーンシート1と内部電極
4aを順次交互に複数層した後、最後に上部無効層2を
重ね加圧積層して図2に示すグリーンブロック8bを作
製する。Subsequently, the first-layer internal electrode 4a
The inner electrode 4a of the second layer which forms a pair with the first layer is printed while being shifted by a predetermined length in the longitudinal direction of the inner electrode 4a of the first layer, and the green sheet 1 is further laminated thereon to form an effective layer of the second layer. And Subsequently, the same third-layer internal electrodes 4a as the first-layer internal electrodes 4a paired with the second-layer internal electrodes 4a are printed on the surface, and the green sheet 1 is laminated thereon. Effective layer. After the green sheets 1 and the internal electrodes 4a are alternately and alternately formed in a plurality of layers in this manner, the upper ineffective layer 2 is finally stacked and laminated under pressure to produce a green block 8b shown in FIG.
【0025】その後、図3に示すように切断線7に沿っ
てグリーンブロック6aを切断後、分離しグリーンチッ
プ8aを得る。グリーンチップ8aの各内部電極4aは
一個おきにその長手方向に所定寸法ずらして千鳥状に配
置するように形成され、しかも隣合う内部電極4aはク
ビレ部5aの端部が一個おきに交互にグリーンチップ8
aの相対向する異なる外側面9に露出した構成となって
おり、同一平面に併設された内部電極4aのクビレ部5
aの端部が露出したグリーンチップ8aの外側面9は、
隣合う積層セラミックコンデンサ11a〜11dを分離
する有効層どうしの接着面積が広くなっている。Thereafter, as shown in FIG. 3, the green blocks 6a are cut along the cutting lines 7 and separated to obtain green chips 8a. Each of the internal electrodes 4a of the green chip 8a is formed so as to be staggered with a predetermined size shifted in the longitudinal direction thereof, and adjacent internal electrodes 4a are alternately green at every other end of the concave portion 5a. Chip 8
a of the internal electrode 4a which is exposed on different outer surfaces 9 facing each other.
The outer surface 9 of the green chip 8a whose end is exposed is
The bonding area between the effective layers separating the adjacent multilayer ceramic capacitors 11a to 11d is increased.
【0026】次に、グリーンチップ8aを所定温度で焼
成し焼結体(図示せず)を作製する。得られた焼結体に
バレル研磨を行い、焼結体の内部に形成された内部電極
4aのクビレ部5aの端群を焼結体の外側面9に確実に
露出させた後、露出した内部電極4aのクビレ部5aの
群全体を覆うように外部電極10aのペーストの塗布焼
付けを行い、更にその表面にメッキ処理を施し、図4に
示すように積層セラミックコンデンサ11a〜11dを
併設した多連型積層セラミックコンデンサ12aを完成
する。Next, the green chip 8a is fired at a predetermined temperature to produce a sintered body (not shown). Barrel polishing is performed on the obtained sintered body to surely expose the end group of the concave portion 5a of the internal electrode 4a formed inside the sintered body to the outer surface 9 of the sintered body. The paste of the external electrode 10a is applied and baked so as to cover the entire group of the crevices 5a of the electrode 4a, the surface thereof is further plated, and the multiple ceramic capacitors 11a to 11d are additionally provided as shown in FIG. The multilayer ceramic capacitor 12a is completed.
【0027】上記多連型積層セラミックコンデンサ12
aは、図5に示すように内部電極4aを一個おきにその
長手方向に所定寸法ずらして千鳥状に配置すると共に、
一個おきに交互にそのクビレ部5aの端部が相対向する
異なる外側面9に露出させているため、外側面9では隣
合う積層セラミックコンデンサ11a〜11dを分離す
る有効層どうしの接着面積が広くなると共に、露出した
クビレ部5aの全体を覆うように外部電極10aを形成
しているため、外部電極10aの表面にメッキ処理を行
う際に、隣合う積層セラミックコンデンサ11a〜11
dを分離する有効層とクビレ部5aとの隙間からメッキ
液の浸入を防止することが可能となる。これにより隣合
う積層セラミックコンデンサ11a〜11dの外部電極
10aどうしの短絡を防止し、メッキ液の浸入による絶
縁抵抗の劣化を防止した信頼性の高い多連型積層セラミ
ックコンデンサ12aを提供することが可能となる。The above-mentioned multiple type multilayer ceramic capacitor 12
a, as shown in FIG. 5, every other one of the internal electrodes 4a is arranged in a staggered manner by being shifted by a predetermined dimension in the longitudinal direction thereof,
Since the end portions of the crack portions 5a are alternately exposed every other one of the outer surfaces 9 facing each other, the bonding area between the effective layers for separating the adjacent multilayer ceramic capacitors 11a to 11d on the outer surface 9 is large. In addition, since the external electrode 10a is formed so as to cover the entire exposed crack portion 5a, when performing plating on the surface of the external electrode 10a, the adjacent multilayer ceramic capacitors 11a to 11
It is possible to prevent the plating solution from entering through the gap between the effective layer for separating d and the crack portion 5a. As a result, a short circuit between the external electrodes 10a of the adjacent multilayer ceramic capacitors 11a to 11d can be prevented, and a highly reliable multilayer ceramic capacitor 12a can be provided in which deterioration of insulation resistance due to infiltration of a plating solution is prevented. Becomes
【0028】次に、図9に示す焼結体13の外側面9に
切込溝14を設け、その切込溝14の内部に外部電極1
0bを形成した多連型積層セラミックコンデンサ12b
について図を用いて説明する。Next, a cut groove 14 is provided in the outer surface 9 of the sintered body 13 shown in FIG.
0b formed in a multilayer ceramic capacitor 12b
Will be described with reference to the drawings.
【0029】公知の積層セラミックコンデンサの製造方
法に従って、図6に示すようなグリーンブロック6bを
作製した後、切断線7に沿って切断分離しグリーンチッ
プ8bを作製する。このグリーンチップ8bは、図7に
示すように引出部5bを設けた内部電極4bを一個おき
にその長手方向に所定寸法ずらして千鳥状に配置するよ
うに形成され、内部電極4bは引出部5bを介して端部
が一個おきに交互にグリーンチップ8bの相対向する異
なる外側面9に露出させた構成となっており、同一平面
に併設され内部電極4bの引出部5bの端部が露出した
グリーンチップ8bの外側面9は、ほぼ有効層で覆われ
た状態となっている。A green block 6b as shown in FIG. 6 is manufactured according to a known method of manufacturing a multilayer ceramic capacitor, and then cut and separated along a cutting line 7 to manufacture a green chip 8b. As shown in FIG. 7, the green chip 8b is formed so that every other internal electrode 4b provided with a lead-out portion 5b is staggered by a predetermined distance in the longitudinal direction, and the internal electrodes 4b are connected to the lead-out portion 5b. The end portions of the lead portions 5b of the internal electrodes 4b are arranged on the same plane, and the end portions of the lead portions 5b of the internal electrodes 4b are exposed. The outer surface 9 of the green chip 8b is almost covered with the effective layer.
【0030】次に、このグリーンチップ8bを所定温度
で焼成した後、図8に示すように焼結体13の両外側面
9の引出部5b位置に、多連型積層セラミックコンデン
サ12bを構成する各積層セラミックコンデンサ11e
〜11hの単位毎に内部電極4bの端部と交差するよう
に、切込溝14の加工を行い内部電極4bの端部を切込
溝14の内部に露出させる。切込溝14の幅は内部電極
4bの幅より狭く、かつ引出部5bの幅より広く、その
深さは内部電極4bの引出部5b側の端部と交差し、し
かも対向する異なる外側面9の内部電極4bの端部と接
しないように、更に切込溝14の底部16及びコーナ部
15を曲面状に加工する。これにより全ての内部電極4
bは切込溝14の内面にのみ、外部電極10bとの接続
を確保するのに必要な一部を確実に露出させることがで
きると共に、次工程で外部電極10bのペーストを塗布
する際、切込溝14の底部16及びコーナ部15に曲面
を持たせて加工したことにより、電極ペーストを切込溝
14の内面に一様に塗布することができ、切込溝14の
立上がりコーナ部分15が角張っている場合、その隅に
取り残されやすい気泡の発生を防止し、内部電極4bと
外部電極10b間で良好な電気的接続状態を確保するこ
とができる。Next, after firing the green chip 8b at a predetermined temperature, as shown in FIG. 8, a multiple-layer ceramic capacitor 12b is formed at the position of the lead-out portion 5b on both outer surfaces 9 of the sintered body 13. Each multilayer ceramic capacitor 11e
The cut groove 14 is processed so as to intersect with the end of the internal electrode 4b for each unit of ~ 11h to expose the end of the internal electrode 4b to the inside of the cut groove 14. The width of the cut groove 14 is smaller than the width of the internal electrode 4b and wider than the width of the lead portion 5b, and the depth thereof intersects the end of the internal electrode 4b on the side of the lead portion 5b and is different from the outer surface 9 facing the same. The bottom 16 and the corner 15 of the cut groove 14 are further processed into a curved surface so as not to contact the end of the internal electrode 4b. This allows all internal electrodes 4
b can reliably expose only a part of the inner surface of the cut groove 14 necessary for securing the connection with the external electrode 10b, and when applying the paste of the external electrode 10b in the next step, Since the bottom portion 16 and the corner portion 15 of the cut groove 14 are processed so as to have a curved surface, the electrode paste can be uniformly applied to the inner surface of the cut groove 14, and the rising corner portion 15 of the cut groove 14 is formed. When it is angular, it is possible to prevent the generation of air bubbles that are easily left behind at the corners, and to ensure a good electrical connection between the internal electrode 4b and the external electrode 10b.
【0031】その後、加工した切込溝14の内面に図9
に示すように外部電極10bを設けるが、外部電極10
bを焼結体13の上下平面と同一平面となるように形成
する。外部電極10bの面が平らであるため多連型積層
セラミックコンデンサ12aの完成品を実装する、回路
基板の半田付けランド寸法の設計が容易となり、更に形
成した外部電極10bの幅を内部電極4bの幅より狭
く、また隣合う外部電極10bの間隔より狭く、しかも
切込溝14の内部にのみ設けるため、隣合う外部電極1
0bとの絶縁距離を十分広く確保でき、多連型積層セラ
ミックコンデンサ12bを基板に実装した際、隣合う外
部電極10b間の半田ブリッジによる短絡を防止するこ
とができる。Thereafter, the inner surface of the cut groove 14 is formed as shown in FIG.
The external electrode 10b is provided as shown in FIG.
b is formed so as to be flush with the upper and lower planes of the sintered body 13. Since the surface of the external electrode 10b is flat, it is easy to design the size of the soldering land of the circuit board for mounting the finished product of the multi-layered multilayer ceramic capacitor 12a, and furthermore, the width of the formed external electrode 10b is reduced by the width of the internal electrode 4b. Since it is narrower than the width and narrower than the interval between the adjacent external electrodes 10 b and is provided only inside the cut groove 14, the adjacent external electrodes 1
The insulation distance from the external electrodes 10b can be sufficiently widened, and when the multiple-layer ceramic capacitor 12b is mounted on a substrate, a short circuit due to a solder bridge between adjacent external electrodes 10b can be prevented.
【0032】また、内部電極4bをその長手方向に所定
寸法ずらして千鳥状に配置し、1つおきに交互に相対向
する外側面9の切込溝14の内部に露出させているため
に、外側面9付近では各積層セラミックコンデンサ11
e〜11hを分離する有効層どうしの接着面積がより広
くなると共に、外部電極10bで覆われた内部電極4b
の端部と有効層の隙間からメッキ液の浸入防止には更に
有効となり得る。よって隣合う積層セラミックコンデン
サ11e〜11h間の絶縁抵抗の劣化を防止し信頼性の
高い多連型積層セラミックコンデンサ12bを提供する
ことが可能となる。Further, since the internal electrodes 4b are staggered in the longitudinal direction by being shifted by a predetermined dimension in the longitudinal direction, and alternately alternately exposed inside the cut grooves 14 of the outer surface 9 opposed to each other, In the vicinity of the outer side surface 9, each multilayer ceramic capacitor 11
e to 11h, the adhesion area between the effective layers is increased, and the internal electrodes 4b covered with the external electrodes 10b
From the gap between the end portion and the effective layer can be more effective in preventing the intrusion of the plating solution. Therefore, it is possible to prevent the deterioration of the insulation resistance between the adjacent multilayer ceramic capacitors 11e to 11h and to provide a highly reliable multiple-layer ceramic capacitor 12b.
【0033】尚、本実施の形態では、内部電極4bの一
方の端部に引出部5bを設けたが、焼結体13の内部に
形成された内部電極4bの位置が外部から判定できる表
示を行うことで引出部5bを除くことは可能となる。In the present embodiment, the lead-out portion 5b is provided at one end of the internal electrode 4b. However, a display that allows the position of the internal electrode 4b formed inside the sintered body 13 to be determined from the outside is provided. By doing so, it is possible to remove the drawer 5b.
【0034】[0034]
【発明の効果】以上本発明によれば、同一平面に複数の
並設したクビレ部を有する内部電極と有効層としての誘
電体セラミック層を交互に複数層積層し、単一素体内部
に並列方向に所定間隔を置いて複数個の積層セラミック
コンデンサを並設した多連型積層セラミックコンデンサ
において、前記内部電極を一個おきにその長手方向に千
鳥状に配置すると共に、内部電極のクビレ部の端部を一
個おきに交互に素体の相対向する外側面にそれぞれ露出
させ、露出させた端部全体を覆うようにして電気的に接
続する複数対の外部電極を形成することにより、素体の
外側面では隣合う積層セラミックコンデンサを分離する
有効層どうしの接着面積が広くなり、外部電極の表面に
メッキ処理を行う際に内部電極と有効層との隙間からメ
ッキ液の浸入を防止することが可能となり、隣合う積層
セラミックコンデンサ間の絶縁抵抗の劣化を防止し、し
かも内部電極と外部電極との接続の信頼性を確保し、完
成品を回路基板に実装する際において、隣合う外部電極
どうしの短絡を防止することのできる信頼性の高い多連
型積層セラミックコンデンサを得ることができる。As described above, according to the present invention, a plurality of internal electrodes each having a plurality of parallel cracks on the same plane and a plurality of dielectric ceramic layers as effective layers are alternately laminated to form a parallel structure inside a single element body. In a multiple-layer ceramic capacitor in which a plurality of multilayer ceramic capacitors are juxtaposed at predetermined intervals in the direction, the internal electrodes are alternately arranged in a staggered manner in the longitudinal direction thereof, and the end of the internal electrode is formed in a staggered shape. By alternately exposing every other part to the opposing outer surfaces of the body and forming a plurality of pairs of external electrodes electrically connected to each other so as to cover the entire exposed end portion, On the outer side, the bonding area between the effective layers that separate adjacent multilayer ceramic capacitors is increased, and when plating the surface of the external electrode, the plating solution is prevented from entering through the gap between the internal electrode and the effective layer. To prevent the deterioration of the insulation resistance between adjacent multilayer ceramic capacitors, as well as to ensure the reliability of the connection between the internal electrodes and the external electrodes. It is possible to obtain a highly reliable multilayer ceramic capacitor that can prevent a short circuit between external electrodes.
【図1】本発明の一実施の形態の多連型積層セラミック
コンデンサのグリーンブロックの展開斜視図FIG. 1 is an exploded perspective view of a green block of a multiple-layer monolithic ceramic capacitor according to an embodiment of the present invention.
【図2】同グリーンブロックの斜視図FIG. 2 is a perspective view of the green block.
【図3】同グリーンブロックを切断した四連型積層セラ
ミックコンデンサのグリーンチップの斜視図FIG. 3 is a perspective view of a green chip of the quadruple-type multilayer ceramic capacitor obtained by cutting the green block.
【図4】同四連型積層セラミックコンデンサの完成品の
部分切欠き斜視図FIG. 4 is a partially cutaway perspective view of a finished product of the quadruple-type multilayer ceramic capacitor.
【図5】同四連型積層セラミックコンデンサの完成品の
平断面図FIG. 5 is a cross-sectional plan view of a completed product of the quadruple-type multilayer ceramic capacitor.
【図6】同内部電極に引出部を設けた四連型積層セラミ
ックコンデンサのグリーンチップの斜視図FIG. 6 is a perspective view of a green chip of a quadruple-type multilayer ceramic capacitor provided with a lead portion on the internal electrode.
【図7】同内部電極に引出部を設けた四連型積層セラミ
ックコンデンサのグリーンチップの展開斜視図FIG. 7 is an exploded perspective view of a green chip of a quadruple-type multilayer ceramic capacitor in which a lead portion is provided in the internal electrode.
【図8】同切込溝を入れた四連型積層セラミックコンデ
ンサの焼結体の斜視図FIG. 8 is a perspective view of a sintered body of a quadruple-type multilayer ceramic capacitor having the cut grooves.
【図9】同切込溝を入れた四連型積層セラミックコンデ
ンサの完成品の斜視図FIG. 9 is a perspective view of a finished product of a quadruple-type multilayer ceramic capacitor having the cut grooves.
【図10】同切込溝を入れた四連型積層セラミックコン
デンサの完成品の平断面図FIG. 10 is a cross-sectional plan view of a completed product of a quadruple-type multilayer ceramic capacitor having the cut grooves.
【図11】従来の多連型積層セラミックコンデンサのグ
リーンブロックの展開斜視図FIG. 11 is a developed perspective view of a green block of a conventional multiple-layer ceramic capacitor.
【図12】同グリーンブロックの斜視図FIG. 12 is a perspective view of the green block.
【図13】同グリーンブロックを切断した四連型積層セ
ラミックコンデンサのグリーンチップの斜視図FIG. 13 is a perspective view of a green chip of a quadruple-type multilayer ceramic capacitor obtained by cutting the green block.
【図14】同四連型積層セラミックコンデンサの完成品
の部分切欠き斜視図FIG. 14 is a partially cutaway perspective view of a completed product of the quadruple-type multilayer ceramic capacitor.
【図15】同四連型積層セラミックコンデンサの完成品
の平断面図FIG. 15 is a cross-sectional plan view of a completed product of the quadruple-type multilayer ceramic capacitor.
1 誘電体グリーンシート 2 上部無効層 3 下部無効層 4a,4b 内部電極 5a クビレ部 5b 引出部 6a,6b グリーンブロック 7 切断線 8a,8b グリーンチップ 9 外側面 10a,10b 外部電極 11a,11b,11c,11d,11e,11f,1
1g,11h 積層セラミックコンデンサ 12a,12b 多連型積層セラミックコンデンサ 13 焼結体 14 切込溝 15 切込溝のコーナ部 16 切込溝の底部 17 誘電体グリーンシート 18 上部無効層 19 下部無効層 20 内部電極 21 グリーンブロック 22 切断線 23 グリーンチップ 24 外側面 25 外部電極 26a,26b,26c,26d 積層セラミックコン
デンサ 27 多連型積層セラミックコンデンサDESCRIPTION OF SYMBOLS 1 Dielectric green sheet 2 Upper ineffective layer 3 Lower ineffective layer 4a, 4b Internal electrode 5a Crack part 5b Leader 6a, 6b Green block 7 Cutting line 8a, 8b Green chip 9 Outer side surface 10a, 10b External electrode 11a, 11b, 11c , 11d, 11e, 11f, 1
1g, 11h Multilayer Ceramic Capacitor 12a, 12b Multilayer Multilayer Ceramic Capacitor 13 Sintered Body 14 Cut Groove 15 Corner of Cut Groove 16 Bottom of Cut Groove 17 Dielectric Green Sheet 18 Upper Ineffective Layer 19 Lower Ineffective Layer 20 Internal electrode 21 Green block 22 Cutting line 23 Green chip 24 Outer surface 25 External electrode 26a, 26b, 26c, 26d Multilayer ceramic capacitor 27 Multiple-layer type multilayer ceramic capacitor
───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E001 AB03 AC02 AC03 AD03 AF00 AF06 AH01 AH05 AH06 AH09 AJ01 AJ02 AZ01 5E082 AA01 AB03 BC35 BC36 CC02 EE04 EE16 EE35 EE42 FG06 FG26 FG52 FG54 GG10 GG28 HH43 JJ03 JJ05 JJ21 JJ23 LL02 LL03 MM22 MM24 MM26 PP09 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) MM24 MM26 PP09
Claims (9)
する内部電極と有効層としての誘電体セラミック層を交
互に複数層積層し、単一素体内部に並列方向に所定間隔
を置いて複数個の積層セラミックコンデンサを並設した
多連型積層セラミックコンデンサにおいて、前記内部電
極を一個おきにその長手方向に千鳥状に配置すると共
に、内部電極のクビレ部の端部を一個おきに交互に素体
の相対向する外側面にそれぞれ露出させ、露出させた端
部全体を覆うようにして電気的に接続する複数対の外部
電極を形成した多連型積層セラミックコンデンサ。1. An internal electrode having a plurality of jutting portions arranged side by side on the same plane and a dielectric ceramic layer as an effective layer are alternately laminated in a plurality of layers, and are arranged inside a single element at predetermined intervals in a parallel direction. In a multiple-layer ceramic capacitor in which a plurality of multilayer ceramic capacitors are juxtaposed, the internal electrodes are alternately arranged every other one in a staggered manner in the longitudinal direction, and the end portions of the internal electrode are alternately alternately arranged. A multiple-layered multilayer ceramic capacitor having a plurality of pairs of external electrodes which are respectively exposed to opposing outer surfaces of a body and are electrically connected so as to cover the entire exposed end portions.
の幅寸法を、素体内部に形成した内部電極の幅寸法より
狭くした請求項1に記載の多連型積層セラミックコンデ
ンサ。2. The multiple-layer ceramic capacitor according to claim 1, wherein the width of the concave portion of the internal electrode connected to the external electrode is smaller than the width of the internal electrode formed inside the element body.
た内部電極のクビレ部の幅より広く形成した請求項1ま
たは請求項2に記載の多連型積層セラミックコンデン
サ。3. The multilayer ceramic capacitor as claimed in claim 1, wherein the width of the external electrode is wider than the width of the concave portion of the internal electrode exposed on the outer surface of the element body.
効層としての誘電体セラミック層を交互に複数層積層
し、単一素体内部に並列方向に所定間隔を置いて複数個
の積層セラミックコンデンサを並設した多連型積層セラ
ミックコンデンサにおいて、前記内部電極を一個おきに
その長手方向に千鳥状に配置すると共に、内部電極の一
方の端部を一個おきに交互に素体の相対向する外側面に
露出しない程度まで接近させ、素体の外側面から内部電
極の端部と交差する切込溝を加工し、この切込溝の内面
に前記内部電極の端部と電気的に接続するように外部電
極を形成した多連型積層セラミックコンデンサ。4. A plurality of internal electrodes and a plurality of dielectric ceramic layers as effective layers are alternately stacked on the same plane, and a plurality of internal electrodes are arranged inside the single element at predetermined intervals in a parallel direction. In a multi-layer type multilayer ceramic capacitor in which ceramic capacitors are juxtaposed, every other one of the internal electrodes is arranged in a staggered manner in the longitudinal direction, and one end of the internal electrode is alternately opposed to the element body every other one. Approach the outer surface to the extent that it is not exposed, process a notch groove crossing the end of the internal electrode from the outer surface of the element, and electrically connect the inner surface of the notch with the end of the internal electrode. Multi-layer ceramic capacitor with external electrodes formed in such a way.
け、この引出部を介して内部電極を素体外側面に露出さ
せ、その露出部に対し外側面から内部電極と交差するよ
うに切込溝を設け、この切込溝の内面に内部電極の端部
と電気的に接続する外部電極を形成した請求項4に記載
の多連型積層セラミックコンデンサ。5. A lead portion is provided at one end of each internal electrode, and the internal electrode is exposed to the outer surface of the body through the lead portion, and the exposed portion intersects the internal electrode from the outer surface. 5. The multilayer ceramic capacitor according to claim 4, wherein a cut groove is provided, and an external electrode electrically connected to an end of the internal electrode is formed on an inner surface of the cut groove.
くまた内部電極の幅よりも狭く、その深さは内部電極の
端部と交差するように設けた請求項4または請求項5に
記載の多連型積層セラミックコンデンサ。6. The width of the notch groove is wider than the lead-out portion of the internal electrode and narrower than the width of the internal electrode, and the depth thereof is provided so as to intersect the end of the internal electrode. 6. The multiple-layer monolithic ceramic capacitor according to 5.
隔より狭くした請求項4から請求項6のいずれか1つに
記載の多連型積層セラミックコンデンサ。7. The multi-layer monolithic ceramic capacitor according to claim 4, wherein a width of the cut groove is smaller than a distance between adjacent cut grooves.
した請求項4から請求項7のいずれか1つに記載の多連
型積層セラミックコンデンサ。8. The multiple-layer ceramic capacitor according to claim 4, wherein a corner portion at the bottom of the cut groove has a curved surface.
た請求項4から請求項8のいずれか1つに記載の多連型
積層セラミックコンデンサ。9. The multilayer ceramic capacitor according to claim 4, wherein a bottom surface of the cut groove is curved inward.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11081134A JP2000277380A (en) | 1999-03-25 | 1999-03-25 | Multi-layer type multilayer ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11081134A JP2000277380A (en) | 1999-03-25 | 1999-03-25 | Multi-layer type multilayer ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000277380A true JP2000277380A (en) | 2000-10-06 |
Family
ID=13737943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11081134A Pending JP2000277380A (en) | 1999-03-25 | 1999-03-25 | Multi-layer type multilayer ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000277380A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6829134B2 (en) | 2002-07-09 | 2004-12-07 | Murata Manufacturing Co., Ltd. | Laminated ceramic electronic component and method for manufacturing the same |
| JP2007258534A (en) * | 2006-03-24 | 2007-10-04 | Ngk Spark Plug Co Ltd | Laminated electronic component |
| JP2007266072A (en) * | 2006-03-27 | 2007-10-11 | Tdk Corp | Multilayer varistor array and multilayer varistor |
| JP2008141212A (en) * | 2001-08-10 | 2008-06-19 | Murata Mfg Co Ltd | Manufacture of laminated ceramic electronic component |
| JP2008252150A (en) * | 2008-07-22 | 2008-10-16 | Tdk Corp | Laminated chip varistor |
| JP2009099827A (en) * | 2007-10-18 | 2009-05-07 | Murata Mfg Co Ltd | Capacitor array and method of manufacturing the same |
| JP2010080570A (en) * | 2008-09-25 | 2010-04-08 | Sanyo Electric Co Ltd | Solid electrolytic capacitor and method of manufacturing the same |
| US8250747B2 (en) | 2009-08-25 | 2012-08-28 | Tdk Corporation | Method of mounting capacitor array |
| US9666366B2 (en) | 2002-04-15 | 2017-05-30 | Avx Corporation | Method of making multi-layer electronic components with plated terminations |
-
1999
- 1999-03-25 JP JP11081134A patent/JP2000277380A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008141212A (en) * | 2001-08-10 | 2008-06-19 | Murata Mfg Co Ltd | Manufacture of laminated ceramic electronic component |
| US9666366B2 (en) | 2002-04-15 | 2017-05-30 | Avx Corporation | Method of making multi-layer electronic components with plated terminations |
| US10020116B2 (en) | 2002-04-15 | 2018-07-10 | Avx Corporation | Plated terminations |
| US10366835B2 (en) | 2002-04-15 | 2019-07-30 | Avx Corporation | Plated terminations |
| US11195659B2 (en) | 2002-04-15 | 2021-12-07 | Avx Corporation | Plated terminations |
| US6829134B2 (en) | 2002-07-09 | 2004-12-07 | Murata Manufacturing Co., Ltd. | Laminated ceramic electronic component and method for manufacturing the same |
| JP2007258534A (en) * | 2006-03-24 | 2007-10-04 | Ngk Spark Plug Co Ltd | Laminated electronic component |
| JP2007266072A (en) * | 2006-03-27 | 2007-10-11 | Tdk Corp | Multilayer varistor array and multilayer varistor |
| JP2009099827A (en) * | 2007-10-18 | 2009-05-07 | Murata Mfg Co Ltd | Capacitor array and method of manufacturing the same |
| US8004819B2 (en) | 2007-10-18 | 2011-08-23 | Murata Manufacturing Co., Ltd. | Capacitor array and method for manufacturing the same |
| JP2008252150A (en) * | 2008-07-22 | 2008-10-16 | Tdk Corp | Laminated chip varistor |
| JP2010080570A (en) * | 2008-09-25 | 2010-04-08 | Sanyo Electric Co Ltd | Solid electrolytic capacitor and method of manufacturing the same |
| US8250747B2 (en) | 2009-08-25 | 2012-08-28 | Tdk Corporation | Method of mounting capacitor array |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8508912B2 (en) | Capacitor and method for manufacturing the same | |
| CN101868838B (en) | Multilayer Ceramic Electronic Components | |
| US6829134B2 (en) | Laminated ceramic electronic component and method for manufacturing the same | |
| JP4905498B2 (en) | Multilayer ceramic electronic components | |
| US7316755B2 (en) | Method of producing multi-terminal type laminated ceramic electronic component | |
| CN115148454B (en) | Laminated electronic component | |
| CN108364785B (en) | Multilayer capacitor and electronic component device | |
| JPH10270282A (en) | Multilayer ceramic capacitor | |
| JP2000277380A (en) | Multi-layer type multilayer ceramic capacitor | |
| JP6142650B2 (en) | Multilayer feedthrough capacitor | |
| JPH11135356A (en) | Multilayer ceramic capacitors | |
| JP2000277382A (en) | Multi-layer monolithic ceramic capacitor and method of manufacturing the same | |
| JP2000277381A (en) | Multi-layer type multilayer ceramic capacitor | |
| JP2004153502A (en) | Laminated lc composite component | |
| JP2003264118A (en) | Multilayer ceramic electronic component | |
| JP7055588B2 (en) | Electronic components | |
| JP2000049038A (en) | Multilayer ceramic capacitors | |
| CN115116696B (en) | Laminated inductor | |
| JP4692221B2 (en) | Multilayer electronic components | |
| JPH0945830A (en) | Chip electronic component | |
| JPH1197283A (en) | Manufacturing method of multi-layer type multilayer ceramic capacitor | |
| JP2006041319A (en) | Surface mount type multiple capacitor and its mounting structure | |
| JPH1154369A (en) | Multilayered electronic component | |
| JPH1197284A (en) | Manufacturing method of multi-layer type multilayer ceramic capacitor | |
| JP3955047B2 (en) | Electronic components |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040623 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040629 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20041102 |