JP2008252009A - 300 mm silicon test wafer and semiconductor manufacturing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a 300 mm silicon test wafer and the like, whereby high reproducibility is proper for the structure of an edge of the 300 mm test wafer for ensuring performance data evaluation in a semiconductor manufacturing apparatus, an evaluating apparatus, and the like, and wherein exfoliation of a film or scratches are not produced. <P>SOLUTION: The 300 mm silicon test wafer of the present invention is provided for developing or evaluating the semiconductor manufacturing apparatus, the evaluating apparatus, and a material. The test wafer is manufactured and designed, such that the end face of the edge and a surface within 0.3 mm from the end face of the edge are made of the same material up to a depth of at least 10 nm, and thus the surface of the edge has stable electrical characteristics. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a structure of an edge portion of a 300 mm test wafer and a processing technique for the edge portion to ensure performance data evaluation of a semiconductor manufacturing apparatus, an evaluation apparatus, or the like.

When manufacturing a semiconductor device on a wafer, the wafer is processed by several processing apparatuses using plasma, ions, or electric charges. At that time, the charge generated by the processing apparatus or the charge of the chemical used in the processing apparatus is transmitted to the gate electrode through the wiring metal, and the charge destroys the gate oxide film and causes damage. This phenomenon is called “charge damage”. In order to manufacture semiconductor devices with a high yield, a control technique for suppressing the charge damage has been developed. Since charge damage needs to be controlled to a smaller level as technology advances, development of charge damage control technology continues. In order to efficiently perform the development, a wafer that accelerates charge damage may be used. This wafer is called a “test wafer” for charge monitoring.

  In the above test wafer, polysilicon is used for the metal part of the MOS capacitor using the silicon wafer oxide film as the gate insulating film, and the polysilicon is extended over the field insulating film to produce a large-area electrode. By efficiently collecting the charges generated by the electrodes in the device manufacturing process, the breakdown of the gate insulating film due to the charges is accelerated, and the charge damage is evaluated.

An example of a test wafer structure (cell structure) used exclusively for damage monitoring is shown in FIGS. FIG. 8 shows a longitudinal sectional view, and FIG. 9 shows a plan view. In the test wafer 100 shown in FIGS. 8 and 9, 101 is a substrate, 102 is an insulating film (eg, a thickness of 350 nm) formed on the surface of the substrate 101, and 103 is formed on the insulating film 102. A polysilicon film (for example, 150 to 450 nm). As shown in FIG. 9, the polysilicon film 103 has each part of an antenna region 103a, a pad region 103b, and an active region 103c. In the active region 103c, a gate oxide film (for example, 4 nm thick) 102a is formed by the insulating film 102 described above. The ratio of the area of the antenna area to the active area is called the antenna ratio. The antenna ratio is designed from 2 to 1 million or more. The wafer used in the present invention is designed up to a million antenna ratio. The larger the antenna ratio is, the more charge is captured and passed through the oxide film in the active region. Since the oxide film is damaged according to the amount of charge passing therethrough, it becomes more sensitive as the antenna ratio increases. When the damage exceeds a certain amount, the oxide film is destroyed and changed to a material like a conductor. The oxide film remains insulative until it is destroyed, and a small amount of current flows through the injected charges and defects generated inside. Before and after the oxide film is destroyed, the current-voltage characteristics are markedly different. The typical characteristic curve is shown in FIG. 18 for reference. This is the characteristic after the broken line 502 is broken before the solid line 501 is broken. These characteristics 501 and 502 are typical characteristics when the thickness of the gate oxide film is 4 nm. By checking this characteristic curve for each chip, examining whether it was destroyed or not, and creating a wafer distribution map of destruction, the cause of the destruction can be identified. In the description of the embodiment, a destruction map is used. In order to easily determine the destruction from the curve, it is convenient to use a voltage when a current of a constant value, for example, 10 to the sixth power, flows. Therefore, the breakdown is determined by classifying the voltage. Charge damage is evaluated by the destruction of the metal film of the gate electrode with the antenna, the silicon oxide film, and the diode formed by the silicon substrate.

There are many types of devices that generate or use charge. Semiconductor device manufacturing apparatuses that generate electric charge are mainly apparatuses that use plasma, apparatuses that use ions, and apparatuses that use an electrolytic solution. For example, etchers, plasma chemical vapor deposition apparatuses, ion implantation apparatuses, sputtering apparatuses, and chemical machinery There is a polishing apparatus (CMP apparatus). In addition, although there is an apparatus that does not use an apparent charge, there is an apparatus in which insulating water generates an electric charge by friction. According to the following non-patent document 1, a surface potential of −30 volts (V) is generated according to the number of rotations of the wafer by causing pure water to collide with the silicon wafer.

It has been found that the effect of electric charges depends on the structure of the apparatus, and in particular, the method of fixing the wafer edge and the degree of adhesion of the surface of the fixing table are related. For this reason, it has become necessary to control the wafer edge condition clearly and electrically. However, the test wafer which is the object of the present invention is manufactured without considering the influence of the wafer edge. Test wafers are manufactured using various equipment from various companies. Since the material structure of the wafer edge is determined according to the wafer support mechanism of the apparatus to be used, the material structure is unintentionally determined. For reference, FIGS. 19, 20, 21, and 22 show how the film attached to the wafer edge differs depending on the apparatus. FIG. 19 shows an example of film growth by a batch processing furnace (tube 513) such as CVD for forming the growth film 512 on both surfaces of the wafer 511. Most of the growth of the oxide film, the silicon nitride film, and the polysilicon film is performed by this method. The film 512 is grown on the entire surface of the wafer 511 including the edge. FIG. 20 shows an example of an apparatus of a wafer support mechanism 522 provided with a clamp mechanism 521. Since the clamp mechanism 521 covers the edge of the wafer 523, the film 524 (metal film, insulating film, etc.) does not grow on the edge of the wafer 523. FIG. 21 shows an example in which the wafer 532 is attracted by, for example, the electrostatic chuck 531. Reference numeral 533 denotes a cover ring. The gas flows in the vapor phase to the back surface of the edge of the wafer 532, and the film 534 (metal film, insulating film, etc.) grows. Even if it is used in a sputtering apparatus, it does not grow on the back side, but it can be grown on the back side of the bevel by treating it with a relatively high pressure specification. FIG. 22 shows an example of an apparatus provided with a shield mechanism 541. The shield mechanism 541 includes a shield guide 542. The shield mechanism 541 acts so that film growth hardly occurs on the back surface of the edge of the wafer 532. In the sputtering apparatus in which the particles travel linearly, they do not grow in the shadow of the shield mechanism 541. The above is the film growth apparatus that affects the edge material, but the cleaning apparatus also determines the edge material structure of the test wafer. A wafer edge processing apparatus is shown in FIG. This is an example of a sheet processing apparatus. Nitrogen gas 552 is blown from the front surface of the wafer 551, and adjusting the strength ("strong" in (A), "weak" in (B)), the wafer back surface of the etching chemical 553 To the wafer surface is controlled. Since the same processing apparatus is used for processes for other purposes, it is fixedly used with a fixed cleaning specification unless it is specifically designed and data is taken and the control specification is changed according to the purpose. When the nitrogen 552 to be blown is weak, the chemicals wrap around the wafer surface and remove the film 554 up to the edge end surface and several mm of the edge portion of the surface. Since there was no need to intentionally design edge materials for test wafers, we measure the data of issues that depend on the edge material structure, design the equipment conditions based on that data, and design the manufacturing specifications. It never happened. In view of the above background, the present invention designs and defines the edge material structure by explaining the influence of the edge material structure on a test wafer called a wafer not intended for device manufacture.

  Here, with reference to FIGS. 10A and 10B, terms relating to locations around the edge of the wafer are defined. In FIG. 10, 201 indicates the edge or edge portion of the wafer, 201a indicates the wafer front surface, and 201b indicates the wafer back surface. A portion indicated by a broken line block 202 is an edge portion, and a tip portion 203 is an edge portion end surface. Further, the contour 203a shows the surface of the edge portion, the contour 203b shows the back surface of the edge portion, and the broken-line contour 204 is a bevel. The bevel 204 is obtained by adding an edge portion surface 203a and an edge portion back surface 203b.

The processing of the edge portion 202 is not only in terms of electrical contact. There is a process called CMP (Chemical Mechanical Polishing), which is used to flatten the wafer. For this, polishing powder mixed in a liquid called slurry is used, but when this polishes the material of the wafer edge, depending on the film structure of the edge part, it creates a new film peeling or scratches the peeled piece This creates a barrier. This is because when the polishing powder polishes the film on the wafer, a large horizontal stress is applied in accordance with the polishing motion under pressure. In particular, since stress concentrates on the edge portion of the wafer, if the film is locally thin, peeling pieces are generated from the film, and the failure tends to occur. In addition, peeling pieces are generated for other reasons. If there is insufficient edge rinse of the resist, the partially left tedist becomes a mask, which remains in the film etching process, which is the same as when dust remains. This also peels off and becomes a peeled piece, which causes damage to the wound. In order to solve this problem, a technique of polishing and scraping the edge portion has been adopted. The equipment needs for that purpose have also increased. The literature which describes it is the following non-patent literature 2.

Although it is one of the solutions to scrape the material film of the edge part that causes the obstacle, it is necessary to be able to define the electrical contact characteristics even in the case of scraping. The size of the pattern to be processed has become as fine as 130 nm or less, and the structure of the edge portion in a large 300 mm wafer has not been noticed before, but has emerged as a problem. Let us describe the timing of the problem, taking the thickness of the barrier film, which should be one of the problems, as an example. The thickness of the barrier film has a universal recognition, and is described in, for example, Non-Patent Document 3 below.

For reference, the design prediction of the thickness of the barrier metal is extracted and shown in Table 1 together with the technology node of fineness (MPU half pitch).

  The barrier metal also adheres to the wafer edge, but there is a risk that the electrical characteristics will not be clear if the film is thinner than 10 nm. When there are apparatus parts and apparatus chemicals that come into contact with the wafer edge, the material constituting the edge portion needs to be defined stably.

Since the wafer edge has a long perimeter and is exposed to non-uniform plasma in the periphery of the reaction chamber where plasma non-uniform parts are likely to occur in the plasma device, the influence of plasma non-uniformity that causes damage is affected. Easy to receive. Although the wafer is surrounded by a plasma filled with charge, it has been found that the overall electrical behavior is related to the conductivity characteristics of the wafer. In addition to plasma, the wafer has an electrical contact / non-contact relationship with the fixing pins and the wafer support. Since plasma is related to the potential distribution of the wafer, it has become necessary to control the entire contact area. For example, in order to obtain conductivity for measurement, backside etching is performed to make the backside conductive. However, a slight amount of insulating film and polysilicon remain on the surface of the wafer edge, and the wafer edge fixing pin makes electrical contact. , Sometimes not touching, not reproducible. A conventional structure of the edge portion of the wafer is shown in FIG. FIG. 11 shows an edge portion 202 of a 300 mm wafer, and the wafer 301 is a silicon wafer. As described above, the gate oxide film 302 and the polysilicon film 303 are formed on the wafer surface of the wafer 301. In the edge portion 202, the gate oxide film 302 is formed until reaching the edge portion end surface 203 of the wafer 301. The back surface of the wafer 301 is chemically etched as described above. As for the structure of the edge part, since the electrical contact depends on the structure of the fixing pin on the edge part end surface 203, a reproducible edge structure is desired for the purpose of evaluating the characteristics affected by this. It was.

In the edge portion 202, if the gate oxide film 302 has a film peeling, scratch, or hole, a chemical solution or water penetrates from the gate oxide film 302, thereby causing a problem that the film is corroded, depleted, or peeled off. If the polysilicon film residue is dotted, it may become a peeling piece. Examples thereof are shown in FIGS. 12 and 13, reference numeral 301 denotes a wafer, 302 denotes a gate silicon oxide film 401, three fixing pins, and 402 denotes film peeling and wear. One fixing pin 401 is in contact with the part 402 such as film peeling. In this portion, the conductive / nonconductive state becomes unstable as a pin contact state.

Further, the peeling of the polysilicon film causes the generation of particle dust 403 as shown in FIG. 14. Therefore, when the particle dust 403 destabilizes the electrical contact or is pushed by the fixing pin, the particle dust 403 causes new scratches. It created a chain of obstacles to create.

For this reason, it has become necessary to select a combination of a film that does not cause peeling, so that a chemical solution or the like does not permeate through a hole or a depletion portion of the film, and a peeling piece does not become a garbage piece. As a method for preventing film peeling at the edge portion, a method for removing the material at the edge portion by mechanical polishing is used. The following patent documents 1-4 can be mentioned as a well-known example which described this subject and countermeasure.

According to Patent Documents 2 and 3, the process of removing the film by polishing is performed before the patterning process of the film so as not to cause peeling that becomes an obstacle to pattern transfer. Patent Document 4 describes that polishing is performed while protecting the surface with water, and that there are no particles of 0.5 μm or more on the polished edge. Patent Document 1 describes the problem of peeling and the influence on manufacturing yield. In this way, the obstacle has been in the era of small-diameter wafers, but recently, in the era of mass production of 300 mm wafers, the processing of wafer edge portions that affect the chip yield has come to affect the cost.

In addition to the above-described problem that the electrical contact with the pins for fixing the wafer on the support table of the manufacturing apparatus is unstable, there is a problem also in a chemical mechanical polishing process called CMP, which is particularly mentioned. Mechanical polishing due to the fact that the strain of mechanical stress and film stress is maximized when dissimilar materials are on the edge, especially the end face, and in the case of metal, corrosion progresses due to battery action. There is a problem that the film peels off under the pressure of. Although it was a problem that was also a technology generation with a line width of 180 nm, when it comes to a technology generation that processes with a line width of 130 nm or less using a large wafer of 300 mm, the thickness of the film to be deposited becomes thin and is in the film Corrosion peeling depending on the penetration of chemicals through small holes is likely to occur, and the peeled film piece damages the polished surface, which is an obstacle to manufacturing yield. In actual device manufacturing, the dimensions are the same or close to each other so that the stress of the deposited film changes depending on the surface pattern shape, and the dimension-dependent peeling problem does not occur. That is, for example, if the required line width is 400 nm with reference to the line width of 200 nm, the design is such that two 200 nm are arranged instead of designing 400 nm. Therefore, generally different dimensions are not in the same layer. On the other hand, in test wafers for examining apparatus performance, there are actively designed dimensions that are greatly different in the same layer. Patent document 5 can be mentioned as the well-known example.

Patent Document 5 is a patent relating to an arrangement in which at least five levels of patterns between 40 nm and 130 nm exist in the same layer of a rectangular region of 50 μm or more. When an attempt is made to put a barrier metal and Cu in an 80 nm groove pattern of TEOS-SiO _{2 having} a thickness of 200 nm, when Ti 5 nm and TiN ₁₀ nm are deposited, only a width of 50 nm is opened on the groove. However, as will be understood from the following experiment, when TiN is further thinned to make the opening large, an incomplete film may be formed and there may be a hole. Such holes become the soaked holes of chemicals, causing corrosion and causing film peeling. Although it seems to be good to add TiN thickly, in the case of a test wafer, since it is designed to be widely distributed, it cannot be adjusted to the thicker one. Unlike wafers that make devices, test wafers need to be defined and defined. In particular, there should be an optimum region between the edge where stress is concentrated and the pattern size.
Japanese Patent Laid-Open No. 7-6985 JP-A-9-186234 JP-A-9-186120 Japanese Patent Laid-Open No. 2003-257717 JP 2006-80238 A Hidemitsu Aoki, “Cu / LOW-K Cleaning Technology”, NIKKEI MICRODEVICES Seminar Proceedings, A1-2, September 30, 2004 “Expanding edge treatment needs, full-scale edge inspection for semiconductor processes”, Electric Journal February 2006, page 84 ITRS (International Technology Roadmap for Semiconductors), 2003, SIA (Semiconductor Industry Association) issued

  An object of the present invention is to provide a technique related to processing of an edge portion of a 300 mm test wafer for ensuring the evaluation of performance data of an apparatus.

The edge portion of the test wafer has a long peripheral length and is exposed to non-uniform plasma in the plasma apparatus, and is easily affected by non-uniform plasma that causes damage. When non-uniformity occurs, the charge distribution of the plasma is biased. Alternatively, when ions are implanted into the upper surface of the wafer by using an ion implanter, how to remove the charge is variously distributed according to the electrical contact with the structure around the wafer and the parts for fixing the wafer. In addition, the edge portion has an electrical contact / non-contact relationship between the fixing pin and the wafer support, and the reproducibility of the edge portion structure is sometimes poor. Therefore, a reproducible edge structure is desired for the structure of the edge portion.

  Further, if there is a scratch or the like on the edge partial film, the film peels off. This resulted in a chain of failures that destabilized the electrical contact and created a new wound when pressed with a fixed pin. For this reason, it is desired to select a film combination that does not cause peeling.

  In view of the above-mentioned problems, the object of the present invention is that the reproducibility of the structure of the edge portion of a 300 mm test wafer for ensuring performance data evaluation of a semiconductor manufacturing apparatus, an evaluation apparatus, etc. It is an object of the present invention to provide a test wafer manufacturing method, a 300 mm silicon test wafer, and a semiconductor manufacturing apparatus using electric charges.

  In order to achieve the above object, a test wafer manufacturing method, a 300 mm silicon test wafer, and a semiconductor manufacturing apparatus using electric charges according to the present invention are configured as follows.

  A test wafer manufacturing method according to the present invention is a semiconductor manufacturing apparatus, an evaluation apparatus, and a method for manufacturing a test wafer for the purpose of development or evaluation of a material, wherein a metal film and an insulating film are formed on the surface of a 300 mm silicon wafer. In the case of applying the test wafer from which the film is removed from the edge portion to the above development or evaluation based on the above-mentioned purpose, the film is removed from the outer peripheral surface of the 300 mm silicon wafer to remove the silicon wafer surface. In the case of applying to the above development or evaluation with the film exposed to the outer surface of the 300 mm silicon wafer based on the above-mentioned purpose, the step of removing the film from the outer surface is omitted.

  The 300 mm silicon test wafer according to the present invention is a 300 mm silicon wafer having an insulating film and a metal film formed on the surface, and the same material up to a depth of 10 nm or more at the edge part end face and the surface within 0.3 mm from the edge part end face. It is characterized by being.

A 300 mm silicon test wafer according to the present invention includes a gate capacitor that uses an insulating film produced by oxidizing a silicon wafer as a dielectric, and an insulating film that surrounds the gate capacitor, and the polysilicon film is composed of a gate capacitor and an insulating film. It is a 300 mm silicon wafer arranged so as to cover a part of the region, and further, without removing either or both of the insulating film and the polysilicon film from the range within 0.3 mm from the edge part end face and the edge part end face. It is characterized by having left. Depending on the apparatus, it is possible to determine the stable edge specification by exposing the silicon surface by removing the insulating film and the polysilicon film on the front and back surfaces of the edge portion within 0.3 mm from the edge surface of the edge portion, the wafer back surface, and the polysilicon film. Therefore, it is also preferable to expose completely.

  In the above 300 mm silicon test wafer, one of the film materials is a metal film containing at least one of Ti nitride, Zr nitride, Ta nitride, Cu, W, Al, amorphous Si, and amorphous C. Features. In this case, the metal film preferably has a thickness of 10 nm or more. In other words, it is preferable that no portion of 10 nm or less exists in the metal film.

In the 300 nm silicon wafer, one of the materials is a silicon oxide film, a silicon nitride film, a silicon oxide film containing carbon, an Hf oxide film, or an insulating film containing a Zr oxide film. In this case, the insulating film preferably has a thickness of 10 nm or more. In other words, it is preferable that no portion of 10 nm or less exists in the metal film.

  Further, in the above 300 mm silicon wafer, it is preferable that particles of 10 μm or more are not present on the edge bevel.

A semiconductor manufacturing apparatus according to the present invention is developed using any of the 300 mm silicon wafers described above as a test wafer.

  According to the present invention, the reproducibility of the structure of the edge portion of a 300 mm silicon test wafer for ensuring performance data evaluation of a semiconductor manufacturing apparatus, an evaluation apparatus, etc. is prevented, and the occurrence of film peeling or scratches is prevented. A test wafer can be made. In addition, a 300 mm test wafer that can measure charge damage electrically and stably can be manufactured, and the electrical characteristics of the edge part have been clarified for various fixing methods of the wafer edge of the apparatus, so that the edge processing test suitable for the apparatus can be performed. A wafer can be selected.

  DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

  The structure of the edge portion of a 300 mm silicon wafer (300 mm silicon test wafer) according to the present invention used as a test wafer having a diameter of 300 mm will be described with reference to FIGS. This 300 mm silicon wafer is used as a test wafer for charge monitoring. 1 to 3 show a longitudinal sectional structure of an end or edge portion of a 300 mm silicon wafer.

  According to the structure of the edge portion of the 300 mm silicon wafer according to the present embodiment, whether to electrically insulate or conduct in the edge portion fixing of the silicon wafer in a semiconductor manufacturing apparatus or the like depends on the device of the 300 mm silicon wafer. In such a case, if the end face processing is controlled so as to have the following structure within a range of 0.3 mm from the edge face of the edge portion of the silicon wafer, the effects of the present invention can be sufficiently achieved in terms of structure.

When electrically insulating in the structure of the edge part of a 300 mm silicon wafer, the edge part end surface, the edge part surface, the wafer surface, the edge part back surface, and the wafer surface included in a range of 0.3 mm from the edge part end surface Are the same film structure and film material, and the film thickness may be controlled to ensure a certain film thickness. An example of the structure of the edge portion is shown in FIG. In FIG. 1, the test wafer is a silicon wafer 11. A broken line block 202 shown in FIG. 1 indicates the edge portion described above. A gate oxide film (SiO ₂ ) 12 is formed on the wafer surface and the wafer back surface, the edge portion surface, the edge portion back surface, and the edge portion end surface of the silicon wafer 11, and the entire surface of the silicon wafer 11 is covered with the gate oxide film 12. ing. The film 13 is a polysilicon film formed on the surface side of the silicon wafer 11. The film 14 is a polysilicon film formed so as to cover the back surface side of the silicon wafer 11 and the range including the edge portion. In FIG. 1, a range A1 means a range of 0.3 mm from the edge portion end face. The thickness of the polysilicon film 14 is constant, for example 150 nm.

  Next, FIG. 2 shows a first structural example in the case where electrical conduction is made in the structure of the edge portion of the 300 mm silicon wafer. In FIG. 2, the entire surface of the silicon wafer 11 is covered with the gate oxide film 12, and the surface of the gate oxide film 12 is covered with the wafer surface, the edge portion surface, the edge portion end surface, and the edge portion back surface. A polysilicon film 14 is formed. Further, a metal film 15 is formed on the surface of the polysilicon film 14 so as to cover the entire polysilicon film 14. The material of the metal film 15 is, for example, TiN or W. The metal film 15 has a certain thickness or more on the end face, for example, 10 nm or more. Also in the case of this structural example, as shown in FIG. 2, the range A1 means a range of 0.3 mm from the end face of the edge portion.

  Further, FIG. 3 shows a second structure example in the case of conducting electrically in the structure of the edge portion of the 300 mm silicon wafer. In FIG. 3, the gate oxide film 12 is formed only on the surface of the silicon wafer 11, and the polysilicon film 13 is formed only on the surface of the oxide film 12. In this structure example, all the films are removed by etching from the edge surface of the silicon wafer 11 and from the front and back surfaces of the silicon wafer 11 in a range A1 of 0.3 mm from the edge surface of the edge, The surface of the silicon wafer 11 is exposed.

  The thickness of the film that gives a stable result was determined experimentally for each of the case of electrically insulating and conducting the structure of the edge portion of a 300 mm silicon wafer, which is a 300 mm test wafer. FIG. 4 and FIG. 5 show experimental configurations and experimental results in the case of insulation, and FIG. 6 and FIG. 7 show experimental configurations and experimental results in the case of conducting, respectively.

In the experimental configuration in the case of insulation shown in FIG. 4, two needles 21 and 22 are arranged in contact with each other on the surface of an oxide film (SiO ₂ film) 12 formed on the surface of the silicon wafer 11. A DC power source 23 and an ammeter 24 are connected in series between the two needles 21 and 22. The applied voltage of the DC power supply 23 is 10V. The needles 21 and 22 are brought into contact with each of arbitrary two points on the surface of the oxide film 12, and a current flowing by applying a voltage of 10 V between the two needles 21 and 22 is measured. A measurement result corresponding to the thickness of the oxide film 12 is shown in FIG. The horizontal axis in FIG. 5 means the thickness of the oxide film (t1: nm), and the vertical axis means the current.

  In the experimental results of FIG. 5, when the thickness of the gate oxide film 12 is 10 nm or less (region A2), the insulating property is unstable. However, when the thickness is larger than 10 nm, the amount of current becomes zero and stable insulation is achieved. I was able to get sex.

Although it was considered that the energization phenomenon in the case of insulation depends on the pressure of the needles 21 and 22, it was assumed that the cause was particles. When the particles are on the silicon wafer 11, when a thin film having a thickness of 10 nm or less is grown on the silicon wafer 11 by the CVD method, it is considered that the shadowed portion of the particles does not grow or becomes extremely thin. Therefore, when a CVD-SiO ₂ film having a thickness of 10 nm was grown on the silicon wafer 11 and oxidized at 900 ° C., the particle portion was quickly oxidized and discolored into spots. This test method is a method used to confirm the presence or absence of pinholes in the silicon nitride film of the DRAM capacitor. In other words, if there are particles on the silicon wafer 11, when the gate oxide film 12 is formed, the portion becomes thin, which causes insufficient insulation. From experiments, it has been found that when the oxide film 12 is formed to a thickness of 10 nm or more, an insulating film having a sufficient thickness can be obtained and a stable insulating property can be obtained.

In the experimental configuration shown in FIG. 6, the gate oxide film (SiO ₂ film) 12 is formed on the surface of the silicon wafer 11 and further formed on the surface of the oxide film (SiO ₂ film) 12. Two needles 21 and 22 are arranged in contact with the surface of the metal film (TiN film) 15, and a DC power source 23 and an ammeter 24 are connected in series between the two needles 21 and 22. The needles 21 and 22 are brought into contact with each of arbitrary two points on the surface of the metal film 15, and a current flowing by applying a voltage of 10 V between the two needles 21 and 22 is measured. A measurement result corresponding to the thickness of the metal film 15 is shown in FIG. In FIG. 7, the horizontal axis represents the thickness (nm) of the metal film, and the vertical axis represents the current. The infinite symbol means that enough current has flowed.

  In the experimental results of FIG. 7, when the thickness of the metal film 15 is 10 nm or less (region A3), the conductivity is unstable. However, when the thickness is larger than 10 nm, the current becomes infinite and stable conductivity. Could get.

  The concept of the energization phenomenon when conducting is basically the same as the concept of the energization phenomenon when insulating. A TiN film having a thickness of 10 nm was grown on a silicon wafer by sputtering a titanium target and oxidized at 800 ° C. In this case, discoloration was observed in the presence of a particle. This is considered that titanium was oxidized through the pin hole of TiN. When the metal film 15 was formed to a thickness of 10 nm or more, it was confirmed that a sufficiently thick conductive film could be obtained and stable conductivity was obtained.

  Next, a method for manufacturing a 300 mm test wafer for charge monitoring will be described. In this manufacturing method, as a 300 mm test wafer for charge monitoring, the manufacturing process is divided so that the insulation and conductivity of the edge portion can be clearly understood. The process flow is shown below.

(Process 1) 300mm p-type silicon (or n-type silicon)
(Process 2) Pre-cleaning RCA treatment SC1
(Process 3) Pad oxidation 20nm
(Process 4) Low pressure silicon nitride film growth SiH ₂ Cl ₂ ammonia 820 ° C.
100nm
(Process 5) Field oxide film pattern exposure (Process 6) Etch silicon nitride film,
(Step 7) Resist peeling Cleaning (Step 8) Field oxidation 350 nm
(Step 9) Silicon nitride film removal Pad oxide film removal (Step 10) Gate oxidation 4 nm
(Step 11) Polysilicon 620 ° C. 450 nm or 150 nm
(Step 12) Phosphorus ion implantation 0.5E14 / cm ²
(Boron for n-type silicon)
(Step 13) Annealing 850 ° C. 1 minute (Step 14) Gate pattern exposure (Step 15) Polysilicon etch (Step 16) Resist stripping Cleaning

The edge of the wafer manufactured by the above process flow has a structure covered with an oxide film and a polysilicon film. In the conventional process, this was followed by a backside polishing process. In that case, as shown in the prior art, it was not necessary to limit the specification design. Therefore, the edge portion end face was mixed with a portion covered with an oxide film and a portion not. At that time, there was a device where charge damage did not depend on the mixture, but there was also a manufacturing device depending on it. An example of a device that relies on was an ion implanter. Damage was measured using the charge damage monitor wafer having the end face structure shown in FIG. 11 fabricated in the above process flow example. Damage was observed where the gate oxide film was destroyed at a rate exceeding 10% at an antenna ratio of 1M. An example of the wafer map is shown in FIG. A diode with an antenna ratio of 1 million (1M) was selected, and a P-type substrate (300 mm wafer 601) was used. Therefore, the substrate 601 was made positive, and the current-voltage characteristics of the diode were examined. A hatched chip 602 indicates a chip in which the gate oxide film is broken. In this example, 54 chips out of all 158 chips were destroyed. It corresponds to 34%. However, when this was examined with the wafer of the above process flow, the gate oxide film breaking chip 602 was not measured with an antenna ratio of 1M. This is shown in FIG. In FIG. 16, the destructive chip 602 is not generated. A 450 nm polysilicon film acts as a conductor film, although not as much as a metal film. Since the charge of the ions implanted around the wafer leaked through the polysilicon, it was determined that charge accumulation and non-uniformity were eliminated. As a result, when no charge damage is observed, this apparatus has been confirmed to be capable of being manufactured without damaging the gate when the periphery of the edge is reliably covered with the conductor film. If confirmed in this way, the apparatus is evaluated as an apparatus capable of implanting without damage according to the specifications of the used wafer edge portion. When the following (Step 17) is performed after Step 16, wafers having different electrical properties of the end face structure can be manufactured.

(Step 17) Removal of polysilicon and gate oxide film by chemical cleaning of back side In this step, HF and nitric acid are sprayed while nitrogen is blown to the surface so that only a part of the chemical solution wraps around the surface edge portion and does not wrap around the entire surface. The polysilicon is removed with the mixed chemical and the gate oxide film is removed with the HF cleaning solution. It was designed to take the film by controlling it to the edge and the surface 1-3mm.

  A 300 mm silicon wafer having a structural specification in which at least 0.3 mm of the edge portion and the wafer surface and the entire surface of the wafer back surface was exposed was designed and manufactured by the process in the step 17. This 300 mm silicon wafer was used to examine the damage of the TiN sputtering apparatus. When TiN is actually sputtered, it is difficult to peel off the film. Therefore, only Ar sputtering treatment was performed to form a natural oxide film at the bottom of the contact hole. Since this apparatus has a structure in which the wafer is fixed with a metal claw, the claw surely makes electrical contact with the wafer substrate. When the wafer having an end face structure with uncertain electrical contact shown in FIG. 11 was used, the gate oxide film destruction damage exceeded 30% at the antenna ratio of 1M. 1M destruction damage was not lost, but charge damage was reduced to 10% or less. If it confirms in this way, if the wafer substrate of the specification of the edge part of the used silicon wafer is designed and used, the sputtering device will be evaluated as a device capable of suppressing damage.

A laminated structure of W / WN / polysilicon was used as the gate metal film instead of the polysilicon film. The W film is grown by a single wafer apparatus that can be edge-shielded and grown. The process is as follows.

(Process 1) 300mm p-type silicon (or n-type silicon)
(Process 2) Pre-cleaning RCA treatment SC1
(Process 3) Pad oxidation 20nm
(Process 4) Low pressure silicon nitride film growth SiH ₂ Cl ₂ ammonia 820 ° C.
100nm
(Process 5) Field oxide film pattern exposure (resist is left only on gate capacitor)
(Process 6) Etch (Polycon nitride film other than capacitor, pad oxide film)
(Step 7) Resist peeling Cleaning (Step 8) Field oxidation 350 nm
(Step 9) Silicon nitride film removal Pad oxide film removal (Step 10) Gate oxidation 4 nm
(Process 11) Single wafer polysilicon 350 nm
(Step 12) Phosphorus ion implantation 0.5E14 / cm ²
(Boron for n-type silicon)
(Step 13) Annealing 850 ° C. for 1 minute (Step 14) WN film 50 nm (No edge growth at the peripheral shield)
(Process 15) W sputter 300nm (no shield edge growth around)
(Step 16) Gate pattern exposure (Step 17) W / WN / polysilicon film etching (Step 18) Resist stripping Cleaning

  The surface of the wafer other than the capacitor that has been processed in the above-described state is covered with a field oxide film, and the edge portion is covered with a silicon nitride film and a pad oxide film. This wafer is electrically insulated from the support and pins for fixing the wafer. There is no location dependence around the conductive and non-conductive wafers. The damage of a plasma etching apparatus that is designed and used with a silicon wafer having this edge structure was evaluated and compared with a wafer having a conventional structure. In the conventional edge structure (FIG. 11), more than 30% of damaged chips were observed in the antenna ratio of 1M, similar to the wafer map of FIG. However, a map similar to the wafer map of FIG. 16 was obtained for the wafer of this processing. That is, the damaged chip was not observed. The apparatus is provided with a wafer support (chuck) called an electrostatic chuck, which is a type that adsorbs the entire back surface of the wafer with electrostatic force, and has no portion that makes electrical contact with the edge of the wafer. However, it is predicted that the charge for electrostatic adsorption is distributed and distributed throughout the chuck depending on the design of the electrode embedded electrode. It was confirmed that the design specification that completely insulates the wafer with an insulating film as in this example is effective in reducing damage.

Although a W / WN / polysilicon laminated structure is used instead of the polysilicon film as the gate metal film, the whole surface growth apparatus is used instead of the shield type fixing covering the periphery of the wafer. The process is as follows.

(Process 1) 300mm p-type silicon (or n-type silicon)
(Process 2) Pre-cleaning RCA treatment SC1
(Process 3) Pad oxidation 20nm
(Process 4) Low pressure silicon nitride film growth SiH ₂ Cl ₂ ammonia 820 ° C.
100nm
(Step 5) Field oxide film pattern exposure (resist is left only on the gate capacitor. At this time, the resist remains in the periphery)
(Process 6) Etch (Polycon nitride film other than capacitor)
(Step 7) Resist peeling Cleaning (Step 8) Field oxidation 350 nm
(Step 9) Silicon nitride film removal Pad oxide film removal (Step 10) Gate oxidation 4 nm
(Process 11) Single wafer polysilicon 350 nm
(Step 12) Phosphorus ion implantation 0.5E14 / cm ²
(Boron for n-type silicon)
(Step 13) Annealing 850 ° C. for 1 minute (Step 14) WN film sputtering 50 nm
(Process 15) CVD-W 300nm
(Step 16) Gate pattern exposure (Step 17) W / WN / Polysilicon film etching (Step 18) Resist stripping Cleaning

  The process is terminated in the above state. When the process is finished in this state, the CVD-W / WN / polysilicon film is surely grown to the upper bevel portion of the edge portion of the wafer and the portion of 0.3 mm from the end face of the edge portion. In this process, the support base for fixing the wafer and the pins are electrically connected. The damage of the Ar sputtering apparatus was evaluated using the wafer having this designed edge structure. At this time, it was compared with a wafer having a conventional structure. In the conventional edge structure, in a device in which 30% damaged chips were observed at an antenna ratio of 1M, damaged chips were not observed on the wafer of this processing. It was confirmed that conducting completely was also effective in reducing damage. Therefore, it has been confirmed that the design of conducting the edge portion and the back surface of the wafer is also an effective method for reducing or eliminating the damage with this sputtering apparatus. The above evaluated the finished structure of the wafer edge by evaluating gate oxide film destruction. The materials for forming the gate structure described above are given as examples. In addition to the materials listed here, the metal film as the gate electrode can be freely designed using TiN, ZrN, TaN, Cu, W, Al, amorphous silicon, or amorphous carbon. As the oxide film, in addition to the silicon oxide film, a silicon nitride film, an oxide film containing carbon (SiOC), an Hf oxide film, or a Zr oxide film can be freely used by design.

  Conventionally, only a 0.18 μm pattern that can be transferred by a KrF exposure apparatus can be used for a test wafer. However, as ArF exposure and X-ray exposure become possible, a pattern of 130 nm or less can be produced. There is a 300 mm test wafer for CMP evaluation of a line pattern having a line width including 100 nm produced using this technique. Patent Document 5 described above discloses a prior invention with a pattern arrangement, but does not describe the processing of the edge portion of the wafer. An X-ray exposure mask was designed to make a test wafer to confirm the optimum area. The design line width ranges from 100 nm to 100 μm, and is a pattern that changes with the line width using the line density as a parameter. The steps of this 300 mm test wafer manufacturing method are as follows.

(Process 1) 300 mm p-type Si wafer (Process 2) Thermal oxidation 200 nm
(Process 3) X-ray exposure transfer of a line pattern including 100 nm (patent pattern of Patent Document 5) (Process 4) Etching Thermal oxide film 200 nm
(Process 5) Resist peeling Cleaning (Process 6) Ti sputtering 10 nm
(Step 7) TiN film sputtering 30 nm
(Process 8) Seed Cu sputtering 100nm
(Process 9) Plating Cu 1 μm (Grows only in the inner region excluding the peripheral 2 mm)
(Process 10) Seed Cu removal 1mm around edge

Up to the above steps, the edge part end face and the edge part surface were covered with a TiN metal film having a thickness of 30 nm in a range of 0.3 mm in the edge part. Conventionally, since CVD-SiO ₂ was used in Step 2 and the seed Cu removal step was omitted, the SiO ₂ and Cu film dissimilar materials appeared on the surface at the edge portion of 0.3 mm, and the CMP slurry electrocorrosion. The Cu piece was peeled off by the action and mechanical pressure, which caused scratches on the polished surface and became an obstacle. This example is schematically shown in FIG. FIG. 17 shows the surface of the wafer 701, and further shows a laser mark 702 and a scratch 703 after CMP. The pattern including 100 nm is covered with the Cu plating film and is not visible on the surface. On the other hand, in the wafer of this process, the Cu film at the edge was removed, and the edge surface of the edge was uniformly covered with the Ti film 10 nm of the glue layer and the TiN film 30 nm thereon. The same material as that used in the inner area of the wafer extends to the wafer edge, and electrical connection is maintained. Since it was uniformly covered with sufficiently thick TiN and there was no electrocorrosion action in principle, there was no problem of peeling.

  The present invention can design and provide a 300 mm test wafer having an electrically stable end face. There are various methods for fixing the wafer edge of the apparatus, but since the electrical characteristics of the edge portion are clearly designed, it is possible to select a 300 mm test wafer with an appropriate edge processing depending on the wafer fixing method of the apparatus.

It is a fragmentary longitudinal cross-section which shows the 1st example of the structure of the edge part of the 300 mm silicon wafer based on this invention used as a test wafer with a diameter of 300 mm. It is a fragmentary longitudinal cross-section which shows the 2nd example of the structure of the edge part of the 300 mm silicon wafer based on this invention used as a test wafer whose diameter is 300 mm. It is a fragmentary longitudinal cross-section which shows the 3rd example of the structure of the edge part of the 300 mm silicon wafer based on this invention used as a test wafer with a diameter of 300 mm. It is a figure which shows the structure of the experimental apparatus which test | inspects the insulation characteristic of the insulating film of the edge structure of the silicon wafer which concerns on this embodiment. It is a graph which shows the insulation characteristic of the insulating film of an edge structure. It is a figure which shows the structure of the experimental apparatus which test | inspects the electroconductive characteristic of the metal film of the edge structure of the silicon wafer which concerns on this embodiment. It is a graph which shows the electrical conductivity characteristic of the metal film of an edge structure. It is a longitudinal cross-sectional view which shows the conventional test wafer. It is a top view which shows the conventional test wafer. It is a figure for demonstrating the term of each part of the edge structure of a wafer. It is a fragmentary longitudinal cross-section which shows the conventional edge structure of a wafer. It is a top view which shows the fixation structure of a wafer. It is a figure explaining the problem on the contact of the edge part of a wafer, and a fixing pin. It is a figure explaining the problem on the contact of the edge part of a wafer, and a fixing pin. It is a map figure of the chip | tip with the diode of a million antenna ratio which the oxide film destroyed. It is a map figure of the chip | tip with a diode of the antenna ratio million which has no broken oxide film. It is a schematic diagram of a scratch on a 300 mm test wafer after a Cu plating film is grown on a 100 nm oxide film pattern and subjected to CMP. It is a schematic diagram of typical current-voltage characteristics of an oxide film. It is a schematic diagram of a cross-sectional view of a batch processing furnace for growing a film on both surfaces of a wafer. It is a schematic diagram of a wafer support of an apparatus for growing a film on the wafer surface excluding an edge portion. It is a schematic diagram of the wafer support stand of the apparatus which makes a film grow on the surface containing a bevel. It is a schematic diagram of the wafer support stand of the sputtering device which makes the film grow on the surface. It is a schematic diagram of a battlefield apparatus in which the flow of chemicals differs depending on nitrogen gas.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Silicon wafer 12 Gate oxide film 13,14 Polysilicon film 15 Metal film 202 Edge part 203 Edge part end surface 203a Edge part surface 203b Edge part back surface 204 Bevel

Claims (10)

A 300 mm silicon test wafer in which a metal film, an insulating film, and a diode formed of a silicon substrate are arranged on the surface for the purpose of developing or evaluating a semiconductor manufacturing apparatus, an evaluation apparatus, and a material. 300 mm silicon test wafer, characterized in that the surface is within 3 mm and is the same material up to a depth of 10 nm or more. A gate capacitor using an insulating film formed by oxidizing a silicon wafer as a dielectric, and an insulating film surrounding the gate capacitor, the polysilicon film covering a part of the region of the gate capacitor and the insulating film In the arranged 300 mm silicon wafer,
A 300 mm silicon test wafer, wherein one or both of the insulating film and the polysilicon film are left without being removed from an edge portion end face and a range within 0.3 mm from the edge portion end face. 3. The 300 mm silicon according to claim 2, wherein the front and back regions of the edge portion within 0.3 mm from the edge surface of the edge portion, the insulating film on the back surface of the wafer, and the polysilicon film are removed to expose the silicon surface. Test wafer. 2. The 300 mm film according to claim 1, wherein one of the film materials is a metal film containing at least one of Ti nitride, Zr nitride, Ta nitride, Cu, W, Al, amorphous Si, and amorphous C. Silicon test wafer. The 300 mm silicon test wafer according to claim 4, wherein the metal film has a thickness of 10 nm or more. 2. The 300 mm silicon test wafer according to claim 1, wherein one of the film materials is a silicon oxide film, a silicon nitride film, a silicon oxide film containing carbon, an Hf oxide film, and an insulating film containing a Zr oxide film. The 300 mm silicon test wafer according to claim 6, wherein the insulating film has a thickness of 10 nm or more. The 300 mm silicon test wafer according to claim 1, wherein particles having a size of 10 μm or more are not present on the edge bevel. In a 300 mm silicon test wafer in which an insulating film having a line width of 100 nm or less aligned with a metal film is formed on a surface for the purpose of development or evaluation of a semiconductor manufacturing apparatus, evaluation apparatus, and material, an edge end face and the edge end face A 300 mm silicon test wafer characterized in that a surface within 0.3 mm is the same material up to a depth of 10 nm or more. A semiconductor manufacturing apparatus developed using the 300 mm silicon test wafer according to any one of claims 1 to 9.

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