JP2008129435A - Data latch circuit and liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data latch circuit capable of reducing power consumption, and to provide a liquid crystal display device comprising the data latch circuit. <P>SOLUTION: The data latch circuit connects a storage circuit composed of inverters 11, 12 connected to a power source having power potential VDD(5V) larger than an amplitude (0-3V) of a digital signal via TFTs 13, 14 to a data bus line to which the digital signal is applied via a TFT 16, and controls the TFTs 13, 14, 16 by using a sampling signal S. Thereby, the data latch circuit can obtain an output (0 to 5V) larger than the amplitude (0-3V) of the input digital signal and can transfer the digital signal at low potential. Further, by inputting an intermediate potential VDC/2(1.5V) between high potential side potential (3V) and low potential side potential (0V) of the digital signal to another input terminal of the storage circuit, the input of a negative phase signal of the input digital signal is made unnecessary, therefore, the number of necessary elements can be reduced and power consumption can be reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data latch circuit that latches digital data, and more particularly to a data latch circuit used in a liquid crystal display device.

  In an active matrix type liquid crystal display device, signal lines and scanning lines are arranged in a matrix on a glass substrate, and thin film transistors (TFTs) are formed at intersections of the signal lines and the scanning lines to form pixels. Yes. In recent years, a drive circuit integrated liquid crystal display device in which a signal line driving circuit for driving signal lines and a scanning line driving circuit for driving scanning lines are formed on a glass substrate using TFTs has been developed.

  FIG. 7 is a block diagram showing a configuration of a liquid crystal display device integrated with a drive circuit. The liquid crystal display device shown in FIG. 1 includes a display unit 1 in which pixels 100 are formed at intersections of a plurality of scanning lines 4 and a plurality of signal lines 5 arranged in a matrix, and scanning line driving for driving the scanning lines 4. A circuit 2 and a signal line driving circuit 3 for driving the signal line 5 are provided. A pixel 100 includes a TFT 101, a liquid crystal 102, an auxiliary capacitor 103, and the like. The signal line driving circuit 3 includes a shift register 31, a sampling latch circuit 32, a load latch circuit 33, and a digital / analog conversion circuit 34. The operation of the liquid crystal display device shown in FIG.

  The digital video signal input to the signal line driving circuit 3 is latched by the sampling latch circuit 32 by the timing signal from the shift register 31. The digital video signal sequentially latched by the sampling latch circuit 32 is latched at the same timing by the load latch circuit 33, converted into an analog signal by the digital / analog conversion circuit 34, and applied to the signal line 5. When the scanning line driving circuit 2 applies the scanning line signal to the scanning line 4, the video signal input to the signal line 5 is written to the pixel 100 and an image is displayed.

Low power consumption is regarded as important in liquid crystal display devices, but the bus line for transferring digital video signals is a size that cannot be ignored as a capacitive load. Digital video signals are used as much as possible to reduce consumption by charging and discharging the bus lines. Is preferably transferred at a low voltage. A data latch circuit described in Patent Document 1 is known as a data latch circuit for reducing power consumption.
JP 2002-189439 A

  However, since the TFT formed on the glass substrate has a higher threshold value and lower mobility than crystal silicon, it is difficult to lower the power supply voltage of the memory circuit. In addition, since the voltage for driving the liquid crystal is determined, the power supply voltage of the circuit cannot often be determined freely.

  The present invention has been made in view of the above, and an object of the present invention is to provide a data latch circuit and a liquid crystal display device which can reduce power consumption.

  A data latch circuit according to a first aspect of the present invention includes a data bus line to which a digital signal is applied, a first power supply having a power supply potential in which the difference between the reference potential and the power supply potential is larger than the amplitude of the digital signal, The first and second inverters supplied with power from one power source, the memory circuit formed by connecting the input terminals and the output terminals of the first and second inverters in a loop, the data bus line and the first A first switching element which is connected to one of the input terminals of the first and second inverters and is turned on during a sampling period in which a digital signal is written to the memory circuit; and a high potential side potential and a low potential side of the digital signal A second power source having an intermediate potential between the first power source and the second power source and the input terminal of the first or second inverter not connected to the data bus line Is connected to, during the sampling period are characterized by having a second switching element is turned on, the.

  In the present invention, the memory circuit is constituted by the first and second inverters driven by the first power source having a power source potential whose difference between the reference potential and the power source potential is larger than the amplitude of the digital signal. Since an output having a larger amplitude than that of the input digital signal can be obtained, the digital signal can be transferred at a low potential, and power consumption due to charging / discharging during the transfer of the digital signal is reduced. In addition, by inputting an intermediate potential between the high potential side and the low potential side potential of the digital signal to the memory circuit, it is not necessary to input a signal having a phase opposite to that of the input digital signal. The number of can be reduced.

  The data latch circuit includes third and fourth switching elements that are respectively disposed between the first power supply and the power supply terminals of the first and second inverters and are turned on during a period other than the sampling period. And

  In the present invention, switching elements are provided between the first power source and the first and second inverters, respectively, and during the sampling period when the digital signal is input, the power to the first and second inverters is supplied. By stopping the supply and supplying power during a period other than the sampling period, data input during the sampling period can be latched and output as a digital signal having a larger amplitude during the period other than the sampling period.

  The data latch circuit includes fifth and sixth switching elements that are respectively connected to output terminals of the first and second inverters and are turned on in a period other than the sampling period.

  In the present invention, each of the outputs of the first and second inverters is provided with a switching element, the switching element is turned off during the sampling period, and the switching element is turned on during a period other than the sampling period. It is possible to latch the data input to and output it as a digital signal having a larger amplitude.

  A liquid crystal display device according to a second aspect of the present invention drives a plurality of scanning lines and a plurality of signal lines arranged in a matrix, a display element arranged at the intersection of the scanning lines and the signal lines, and the scanning lines. A scanning line driving circuit, any one of the data latch circuits described above, and a digital / analog conversion circuit that converts the output of the data latch circuit from digital to analog and inputs the converted data to a signal line.

  ADVANTAGE OF THE INVENTION According to this invention, the data latch circuit and liquid crystal display device which aim at reduction of power consumption can be provided.

[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of a data latch circuit according to the first embodiment. The data latch circuit shown in the figure is used in the sampling latch circuit 32 of the liquid crystal display device shown in FIG. 7, etc., and latches the input video signal by the timing signal from the shift register 31 and outputs it to the load latch circuit 33. To do.

  The data latch circuit shown in FIG. 1 includes a memory circuit composed of inverters 11 and 12 whose input terminals and output terminals are connected in a loop, a power supply having a power supply potential VDD, and a power supply terminal of the inverters 11 and 12. P-type TFTs 13 and 14 disposed between them and an N-type TFT 16 connected to the input terminal of the inverter 12 for controlling whether or not a digital signal is input to the memory circuit, and an input terminal of the inverter 11 for digital And an N-type TFT 15 for controlling whether or not a potential VDC / 2 between the high potential VDC and the low potential VSS is input to the memory circuit, and P-type TFTs 13 and 14 and The N-type TFTs 15 and 16 are supplied with a sampling signal S that defines a sampling period in which a digital signal applied to the data bus line is written to the memory circuit. It is controlled.

  The power supply potential VDD is 5 V, which is higher than the high potential VDC (3 V) of the digital signal applied to the data bus line. The potential VDC / 2 applied to the input terminal of the inverter 11 is 1.5V. As shown in FIG. 1, since the TFTs 13, 14, 15, and 16 controlled by the sampling signal S are provided, the memory circuit can be driven with a voltage larger than that of the input digital signal, so that the digital circuit can be applied at a low potential. Signals can be transferred, and power consumption due to charging / discharging during transfer of digital signals is reduced. Further, by inputting an intermediate potential VDC / 2 between the high potential side VDC and the low potential side potential VSS of the digital signal to the memory circuit, when the digital signal is at a high level (VDC), VDC / 2 is low. When the digital signal is at a low level (VSS), VDC / 2 is at a high level. Therefore, it is not necessary to input a signal having a phase opposite to that of the input digital signal, and the number of necessary elements can be reduced. it can. Even if the potential applied to the input terminal of the inverter 11 is not the intermediate potential VDC / 2 between the high-potential side potential VDC and the low-potential side potential VSS of the digital signal, the inverters 11 and 12 are not at the high level of the digital signal. Any potential that can identify the low level is acceptable.

  FIG. 2 is a circuit diagram showing a configuration of inverters 11 and 12 of the circuit of FIG. As shown in the figure, the inverters 11 and 12 are each composed of a P-type TFT and an N-type TFT to which a gate electrode and a drain electrode are connected, and the point where the gate electrode is connected is the input terminal IN of the inverters 11 and 12. Thus, the point where the drain electrode is connected becomes the output terminal OUT of the inverters 11 and 12. The source electrode of the P-type TFT is connected to the power supply potential VDD via the P-type TFT controlled by the sampling signal S, and the source electrode of the N-type TFT is connected to the reference potential VSS. When the sampling signal S is at the high level, the P-type TFT connected to the power supply potential is turned off, so that the output terminal OUT becomes the high impedance or the reference potential VSS, and the signal input to the input terminal IN when the sampling signal S is at the low level. When it is at a low level, the output of the output terminal OUT is at a high level (VDD).

  Next, the operation of the data latch circuit shown in FIG. 1 will be described with reference to the operation timing chart of FIG.

  When the sampling signal S becomes high level at time t1, the P-type TFTs 13 and 14 are turned off and the N-type TFTs 15 and 16 are turned on. At this time, the inverters 11 and 12 are disconnected from the power source, the digital signal of the data bus line is applied to the node A shown in FIG. 1, and the potential of VDC / 2 is applied to the node B. When the digital signal becomes high level at time t2, the potential of the node A also becomes the high level potential VDC of the digital signal.

  When the sampling signal S becomes low level at time t3, the P-type TFTs 13 and 14 are turned on and the N-type TFTs 15 and 16 are turned off. At this time, power is supplied to the inverters 11 and 12, and the input of digital signals is blocked. In the memory circuit, the potentials of the digital signal and VDC / 2 are compared between the node A and the node B, and a node having a high potential becomes VDD and a node having a low potential becomes VSS.

  FIG. 4 is a circuit diagram showing a configuration of another data latch circuit in the first embodiment. The data latch circuit shown in the figure uses clocked inverters 41 and 42 instead of the inverters 11 and 12 in the circuit shown in FIG. As shown in FIG. 5, the clocked inverters 41 and 42 have a configuration in which four TFTs are connected in series, and the sampling signals S and V are applied to the gate electrodes of the TFTs connected to the power supply potential VDD and the reference potential VSS. A signal / S having a phase opposite to that of the sampling signal S is input. When the sampling signal S becomes a high level, the TFT connected to the power supply potential VDD and the reference potential VSS is turned off, and the output terminal OUT is in a high impedance state.

  Therefore, according to the present embodiment, the memory constituted by the inverters 11 and 12 connected via the TFTs 13 and 14 to the power source having the power source potential VDD (5 V) larger than the amplitude (0-3 V) of the digital signal. The circuit and a data bus line to which a digital signal is applied are connected via the TFT 16, and the TFTs 13, 14, 15, and 16 are controlled by controlling the TFTs 13, 14, 15, and 16 with a sampling signal S that defines a sampling period for writing data to the memory circuit. Since an output (0-5V) larger than the amplitude (0-3V) of the digital signal can be obtained, it is possible to transfer the digital signal at a low potential, and power consumption due to charging / discharging during the transfer of the digital signal is reduced. Is done. In addition, by inputting a potential VDC / 2 (1.5 V) between the high potential side (3 V) and the low potential side potential (0 V) of the digital signal to the other input terminal of the memory circuit, Since it is not necessary to input a signal having a phase opposite to that of the digital signal, the number of necessary elements can be reduced.

[Second Embodiment]
FIG. 6 is a circuit diagram showing a configuration of the data latch circuit in the second embodiment. In the data latch circuit shown in the figure, the TFTs 63 and 64 are connected to the output terminals of the inverters 61 and 62 instead of connecting the TFT to the power supply terminal of the inverter as in the first embodiment, and the sampling signal S is used. It controls on / off. Since other configurations are the same as those in the first embodiment, description thereof will be omitted.

  When the sampling signal S is at a high level, the TFTs 63 and 64 connected to the output terminals of the inverters 61 and 62 are turned off, and the TFTs 65 and 66 connected to the power source of VDC / 2 and the data bus line are turned on. A digital signal of the data bus line is applied to A, and a potential of VDC / 2 is applied to node B. When the sampling signal S changes from the high level to the low level, the TFTs 63 and 64 are turned on, the TFTs 65 and 66 are turned off, and the value of the input digital signal is latched. Since the inverters 61 and 62 are driven by VDD, the potential of a node having a high potential is VDD, the potential of a node having a low potential is VSS, and an output larger than the amplitude of the input digital signal can be obtained. it can.

  Therefore, according to the present embodiment, the TFTs 63 and 64 are connected to the output terminals of the memory circuit constituted by the inverters 61 and 62 driven by the power supply potential VDD (5 V) larger than the amplitude (0-3 V) of the digital signal. The storage circuit and the data bus line to which the digital signal is applied are connected via the TFT 66, and the TFTs 63, 64, 65, 66 are controlled by the sampling signal S, whereby the amplitude ( Since an output (0-5V) larger than 0-3V) can be obtained, a digital signal can be transferred at a low potential, and power consumption due to charging / discharging during the transfer of the digital signal is reduced.

1 is a circuit diagram showing a configuration of a data latch circuit in a first embodiment. FIG. It is a circuit diagram which shows the structure of the inverter of the circuit of FIG. FIG. 2 is an operation timing chart of the circuit of FIG. 1. FIG. 5 is a circuit diagram showing a configuration of another data latch circuit in the first embodiment. FIG. 5 is a circuit diagram showing a configuration of a clocked inverter of the circuit of FIG. 4. It is a circuit diagram which shows the structure of the data latch circuit in 2nd Embodiment. It is a block diagram which shows the structure of the conventional liquid crystal display device integrated with a drive circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display part 2 ... Scanning line drive circuit 3 ... Signal line drive circuit 4 ... Scanning line 5 ... Signal line 11, 12, 61, 62 ... Inverter 41, 42 ... Clocked inverter 13, 14, 15, 16, 43, 44, 63, 64, 65, 66 ... TFT
100 ... Pixel 101 ... TFT
102 ... Liquid crystal 103 ... Auxiliary capacity

Claims (4)

A data bus line to which a digital signal is applied;
A first power supply having a power supply potential in which a difference between a reference potential and a power supply potential is larger than an amplitude of the digital signal;
First and second inverters powered by the first power source;
A memory circuit configured by connecting the input terminal and the output terminal of the first and second inverters in a loop;
A first switching element connected to the data bus line and either one of the input terminals of the first or second inverter and turned on during a sampling period for writing the digital signal to the memory circuit;
A second power source having an intermediate potential between a high potential side potential and a low potential side potential of the digital signal;
A second switching element connected to the second power supply and an input terminal not connected to the data bus line among the input terminals of the first or second inverter and turned on during the sampling period; ,
A data latch circuit comprising:   3. A third switching element and a fourth switching element which are respectively disposed between the first power supply and the power supply terminals of the first and second inverters and are turned on in a period other than the sampling period. Item 2. A data latch circuit according to Item 1.   2. The data latch circuit according to claim 1, further comprising fifth and sixth switching elements that are respectively connected to output terminals of the first and second inverters and are turned on in a period other than the sampling period. A plurality of scanning lines and a plurality of signal lines arranged in a matrix;
A display element disposed at an intersection of the scanning line and the signal line;
A scanning line driving circuit for driving the scanning lines;
A data latch circuit according to any one of claims 1 to 3,
Digital-to-analog conversion of the output of the data latch circuit and input to the signal line; and
A liquid crystal display device comprising:

Images