JP2008122840A - Method for driving image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device capable of suppressing degradation of a liquid crystal material due to flickers in an image or application of a DC voltage. <P>SOLUTION: In a method for driving an image display device for displaying an image with a plurality of grayscales by constituting each frame of image signals from a plurality of sub-frames and selectively turning on or off the sub-frames in a display unit 42 comprising pixels having a liquid crystal LC formed in a matrix, the display period of each sub-frame is divided into a first half display period and a second half display period and polarities are inverted between the first half display period and the second half display period. The ratio of the sum length of the first half display period in each sub-frame to the sum length of the second half display period of each sub-frame is determined in such a manner that the sum product of the length Tk_p (T1_p, T2_p, T3_p) of the first half display period and the potential difference between a pixel electrode and a counter electrode in each sub-frame is equal to the sum product of the length Tk_n (T1_n, T2_n, T3_n) of the second half display period and the potential difference between the pixel electrode and the counter electrode of each sub-frame. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information display terminal for home use, office use, and industrial use, a liquid crystal projector and a driving method of an image display apparatus used for a projection TV.

  In general, there are two methods of driving an image display device using liquid crystal, mainly an analog driving method using amplitude modulation and a digital driving method using pulse width modulation. Compared with the analog drive system, the digital drive system has advantages such as simple electrical adjustment.

  In the digital drive method, each frame of an image signal is composed of a plurality of subframes having different display periods shorter than one frame period, and each subframe is selectively turned on and off in order to control one frame. Is displayed. In this case, in each sub-frame, AC driving is performed by reversing the polarity of the voltage applied to the liquid crystal in the first half and the second half, thereby canceling the DC component applied to the liquid crystal and causing an image called flicker. It is intended to suppress flickering and deterioration of the liquid crystal material due to application of a DC voltage (Patent Documents 1 and 2).

In this method, the value of the pixel electrode voltage V_pix applied to the pixel electrode and the value of the counter electrode voltage V_com applied to the counter electrode are divided into two equal in time for each of the positive polarity application time t1 and the negative polarity application time t2. Then, reverse driving is performed. At this time, the symmetry of the input signal is achieved by inputting a signal satisfying the following expression for the saturation voltage | V_pix−V_com | on the positive polarity side at the input signal level. Here, Vp indicates positive polarity, and Vn indicates negative polarity.
| Vp_pix−Vp_com | − | Vn_pix−Vn_com | = 0

US 2004/0174328 A1 JP 2005-352457 A 2000 S1D, ISSN 1083-1312 / 00 / 2001-0001. [Reflective Nematic LC Devices for LCOS Applications] by Minhua Lu, K. et al. H. Yang, IBM T .; J. et al. Watson Research Center

  As described above, in the conventional image display apparatus, the symmetry of the drive signal is achieved at the input signal level. However, in a reflective image display device formed of a pixel electrode, a counter electrode, a liquid crystal material, and an alignment film, the material that sandwiches the liquid crystal layer is made of a different material, resulting in a voltage level shift. (Non-Patent Document 1), the symmetry of the voltage applied to the liquid crystal layer is lost. Such a problem has occurred even in a transmissive image display device in which the pixel electrode is made transparent.

  The present invention has been devised to pay attention to the above problems and to effectively solve them. The object of the present invention is to optimize the symmetry of the positive polarity voltage and the negative polarity voltage applied to each liquid crystal layer when the polarity is reversed and applied in the first half and the second half in each subframe. An object of the present invention is to provide a driving method of an image display device that can improve symmetry of applied voltage and suppress flickering of an image called flicker and deterioration of a liquid crystal material due to application of a DC voltage.

  According to the first aspect of the present invention, a plurality of pixel electrodes each having an alignment film formed on the surface and a common electrode having an alignment film formed on the surface are arranged to face each other with a liquid crystal interposed therebetween. When a digitized pixel signal is applied to a display unit in which pixels are formed in a matrix and an image is displayed, each frame of the image signal has a plurality of sub periods having a display period shorter than one frame period. In a driving method of an image display device configured by a frame, wherein a desired subframe is selectively turned on or off to display an image of one frame with a plurality of gradations, the display period of each subframe is a first half display period. And the polarity of the first half display period section and the second half display period section are reversed, and the length of the first half display period section in each sub-frame and the pixel electrode-counter electrode The first half of each subframe is set so that the sum of the products of the potential difference between the first electrode and the potential difference between the pixel electrode and the counter electrode is the same as the sum of the product of the length of the second half display period in each subframe. A driving method for an image display device, characterized in that a ratio between a total length of display period portions and a total length of the latter half display period portions in each subframe is set.

  According to the driving method of the image display device according to the present invention, the symmetry of the positive polarity voltage and the negative polarity voltage to be applied is optimal for each frame when the polarity is reversed and applied in the first half and the second half in each subframe. As a result, the symmetry of the voltage applied to the liquid crystal layer can be improved, and flickering of an image called flicker and deterioration of the liquid crystal material due to application of a DC voltage can be suppressed.

Hereinafter, an embodiment of a method for driving an image display apparatus according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a diagram showing a schematic configuration of a projection display device as an example of an image display device, FIG. 2 is a graph showing a relationship between a driving voltage for driving a liquid crystal and emitted light intensity, and FIG. 3 is an image display device according to the present invention. FIG. 4 is a schematic block diagram of the display unit of the image display device applied to the present invention, and FIG. 5 is a pixel in the display unit of the image display device applied to the present invention. 6 is a schematic block configuration diagram of a drive circuit, FIG. 6 is a timing chart showing schematic timings of voltages applied to a pixel electrode and a counter electrode applied to the present invention, and FIG. 7 is a display pattern between gradation levels and subframes. FIG. 8 is an explanatory diagram for explaining the problems of the conventional image display device, and FIG. 9 is an explanatory diagram showing an example of the driving method of the image display device of the present invention.

  The present invention can be applied to panel-type image display devices such as LCDs, PDPs, DLPs, FEDs, and ELs each having a display unit in which a plurality of pixels are arranged in a matrix. In the present embodiment, a projection type display unit having an active matrix type liquid crystal element as a display unit will be described as an example.

  In FIG. 1, incident light Lin generated from a light source (not shown) enters a polarization beam splitter 11. The incident light Lin includes an S-polarized component indicated by “●” and a P-polarized component indicated by “−”. The joining surface 111 of the polarizing beam splitter 11 is configured to reflect the S-polarized component and transmit the P-polarized component. Therefore, the incident light Lin reflected by the joint surface 111 of the polarization beam splitter 11 becomes only the S-polarized component and is incident on the display unit 42. The display unit 42 includes a pixel substrate PE and a counter electrode that are formed of a semiconductor substrate 101 on which a reflective pixel electrode PE provided corresponding to each pixel Px is formed and a transparent substrate 102 on which a transparent counter electrode CE is formed. The liquid crystal layer LC is provided between the semiconductor substrate 101 and the transparent substrate 102 so that the CEs face each other inward. Note that alignment films (not shown) are formed on the pixel electrode PE and the counter electrode CE on the liquid crystal layer LC side.

  The light that is only the S-polarized component incident on the display unit 42 is reflected by each pixel electrode PE, and is modulated according to the video signal by the liquid crystal of the liquid crystal layer LC. As a result of the modulation by the liquid crystal layer LC, a part of the S-polarized component of the light emitted from the display unit 42 becomes a P-polarized component, and enters the junction surface 111 of the polarization beam splitter 11 as light including the S-polarized component and the P-polarized component. To do. The light incident on the joint surface 111 of the polarization beam splitter 11 has only a P-polarized component, and the light having only the P-polarized component is projected on the screen 13 through the projection lens 12. In this way, an image corresponding to the image signal is displayed on the screen 13. Here, the emitted light from the liquid crystal layer LC is given as shown in FIG. In FIG. 2, the voltage that gives the threshold value of the emitted light intensity is Vth, and the voltage that gives the maximum value (saturation voltage) is Vsat. Vdd is a voltage slightly higher than the saturation voltage Vsat.

  Next, the configuration of the image display apparatus will be described with reference to FIGS. FIG. 3 is a schematic configuration diagram showing the drive unit 41 and the display unit 42 of the image display apparatus in the present embodiment. The image signal is converted into subframe data, which is a digital signal, by the signal processing circuit 44 and supplied to the sample hold unit 50 of the display unit 42. In the reference voltage generation circuit 46, voltages for the electrodes V 0 and V 1 are generated, and this voltage is supplied to the selector 48 of the display unit 42. In addition, as the voltage of the pixel electrode PE, the voltage of one of the electrodes V0 and V1 is selectively output by the selector 48 according to the subframe data written in the sample and hold unit 50. The reference voltage generation circuit 46 generates a voltage Vcom applied to the counter electrode CE from the relationship between the effective voltage applied to the liquid crystal and the emitted light intensity. This voltage Vcom is given to the counter electrode CE by the selector 54 in accordance with the timing signal from the timing circuit 52.

  FIG. 4 shows the entire display unit 42, and the display unit 42 includes a column signal electrode drive circuit 14, a row scanning electrode drive circuit 16, and display means 18. Here, the column signal electrode driving circuit 14 has a data shift register 14A extending in the horizontal direction therein, and the data is inverted with respect to each column signal electrode D (D1, D2,..., Di). Inverted column signal electrodes XD (XD1, XD2,..., XDi) for supplying inverted data to the pixels are provided, and are provided in parallel with the corresponding column signal electrodes. The row scan electrode driving circuit 16 has therein a line shift register 16A having the number of stages corresponding to the total number of display rows, and row scan electrodes W (W1, W2,..., Wj corresponding to the total number of display rows. ) Are arranged perpendicular to the column signal electrodes D and XD. Pixels Px are arranged at the intersections between the column signal electrodes D and the row scanning electrodes W. Therefore, the pixels Px are arranged in a matrix as a whole. The external input electrodes V1 and V0 are commonly connected to all the pixels Px.

  In the column signal electrode driving circuit 14 having such a configuration, a horizontal data shift register is driven by a horizontal start signal HST and a horizontal shift clock HCK supplied by a driving timing pulse generation circuit (not shown), and each subframe is driven. Are sequentially sampled into column signal electrodes D1, XD1, D2, XD2,..., Di, XDi. On the other hand, the row scanning electrode drive circuit 16 includes a line shift register 16A having a number of stages corresponding to the total number of display rows. The line shift register 16A is driven by a vertical start signal VST synchronized with a start signal of each subframe supplied from a drive timing pulse generation circuit (not shown) and a vertical shift clock VCT synchronized with a horizontal period, and the row scan electrode W1. , W2,..., Wj, pulses are sequentially output every horizontal period. As a result, display data is held row by row in the sample hold portion 50 (see FIG. 5) of the pixel Px connected to the row scanning electrodes W1, W2,.

Next, an example of a pixel driving circuit corresponding to one pixel will be described with reference to FIG. This pixel drive circuit outputs a voltage to the pixel electrode PE through the switch unit 60 and the sample hold unit 50 that holds the display data supplied from the column signal electrode drive circuit 14 and the output data from the sample hold unit 50. The sample hold unit 50 includes one or a plurality of DRAM circuits or SRAM circuits.
The switch unit 60 selectively outputs one of the two external input electrodes V0 and V1 according to the data output from the sample hold unit 50. The two external input electrodes V0 and V1 are wired in common for all the pixels and are supplied from the reference voltage generation circuit 46 of the drive unit 41 (see FIG. 3) of the image display device. The switch unit 60 selects the voltage input to the two external input electrodes V0 and V1 based on the data of the sample hold unit 50, and applies the selected voltage to the pixel electrode PE.

  Now, a driving method of the image display apparatus configured as described above will be described with reference to FIGS. FIG. 6 is a timing chart showing voltage waveforms of respective portions in the pixel drive circuit, and FIG. 7 is a view showing an example of a display pattern between a gradation level and a subframe. In FIG. 7, one frame is composed of eight sub-frames having different display periods from SF1 to SF8. By selectively turning on or off the display of each sub-frame, pulse width modulation is performed. It is set so that 256 kinds of gradation levels from 0 to 255 can be displayed. For example, when one frame is displayed with a certain gradation level for one pixel, the gradation level is displayed by displaying from SF1 to SF8 in order with the display pattern of the gradation level. Become. It should be noted that the description where the number of gradation levels on the vertical axis is skipped is omitted.

  The unit of the display period is, for example, “μsec”. In the display pattern, “0” indicates “low” (off), and “1” indicates “high” (on). For example, the gradation level 0 indicates “true white” and the display is “0” in all the subframes SF1 to SF8, whereas the gradation level 255 indicates “true black” and all the subframes SF1 to SF8. The display is “1”. Here, the high voltage of the digital voltage applied to the two external input electrodes V0 and V1 is Vdd, and the low voltage is 0V.

  First, each subframe includes a data address period in which data is transferred from the column signal electrode driving circuit 14 to all pixels, and a display period in which the liquid crystal is driven based on the transferred data to display data. In each subframe, the data address period is the same, and the display period is different. Here, as described above, the subframe is indicated by SF, and when one frame is composed of eight frames, SF1 to SF8 are displayed on / off in a display period set in advance corresponding to each subframe.

  FIG. 6 is a schematic timing chart of voltages applied to the pixel electrode PE and the counter electrode CE. As shown in FIG. 6, when the data of the sub-frame SF is “High”, the voltage applied to the pixel electrode PE is the voltage of the electrode V1 in the first half of the display period and the voltage of the electrode V0 in the second half. When the data is “Low”, contrary to the above, the first half of the display period is the voltage of the electrode V0 and the second half is the voltage of the electrode V1. In the data address period, the voltage of the electrode V0 is used. On the other hand, the voltage applied to the counter electrode CE is Vp_com in the first half of the display period and Vn_com in the second half.

Next, the contents of each subframe will be described in detail by taking one subframe as an example. Here, T represents the length of the display period of one subframe, and Tp represents the length of the first half display period portion (hereinafter also referred to as “first half display period”). (Hereinafter also referred to as “second half display period”) is Tn. The above p represents a positive voltage and n represents a negative voltage.
In FIG. 6, the length of each period is shown as an example in SF3. FIG. 8 shows the display period portion of the sub-frame and displays the combination of the potentials between the electrodes, and shows the transition of the potential difference between the pixel electrode and the counter electrode. Here, three subframes SF1 to SF3 are extracted and described as representatives, and the display period of each subframe is T1 to T3. Further, the length of the first half display period portion is represented by Tk_p (= T1_p, T2_p, T3_p...), And the length of the second half display period portion is represented by Tk_n (= T1_n, T2_n, T3_n. Note that k represents a natural number. The positive and negative potentials of the counter electrode are expressed as Vp_com and Vn_com, respectively.

FIG. 8 shows a case of a conventional image display device. As shown in FIG. 8A, the first half display period portion Tk_p and the second half display period portion Tk_n are set to be the same in each subfield. Yes. Specifically, T1_p = T1_n, T2_p = T2_n, and T3_p = T3_n. Here, when no voltage level shift caused by the substrate material occurs, the potential of each electrode is set so that Vth and Vsat satisfy the following expressions.
Vth = V0−Vp_com = − (V1−Vn_com)
Vsat = V1-Vp_com =-(V0-Vn_com)
That is, “H1 × Tk_p (first hatched portion) = H2 × Tk_n (second hatched portion)”. In each subframe, the area of the first hatched portion and the latter hatched portion are equal. Specifically, S1p = S1n, S2p = S2n, and S3p = S3n. This area is given by the product of the length of the first half display period portion or the second half display period portion and the potential difference between the pixel electrode and the counter electrode.

  However, in the actual image display device, the voltage level shift Vsft caused by the substrate material occurs as shown in FIG. 8B, so the above relationship does not hold, and as shown in FIG. 8B. It becomes a state. That is, it is inevitable that the voltage levels of Vn_com and Vp_com are shifted downward by Vsft in the same manner as in the illustrated example. For this reason, H1 ≠ H2, and “H1 × Tk_p ≠ H2 × Tk_n”, and the areas of the hatched portion in the first half and the hatched portion in the latter half are different (the voltages applied to the liquid crystals are different). Specifically, S1p ≠ S1n, S2p ≠ S2n, and S3p ≠ S3n. As a result, the symmetry of the voltage applied to the liquid crystal is lost between the first half and the second half of the subframe, causing flicker and the like as described above.

Therefore, in the present invention, as shown in FIG. 9, the sum of the product of the length of the first half display period portion in each subframe and the potential difference between the pixel electrode and the counter electrode, and the second half display period portion in each subframe. The sum of the lengths of the first half display period portions in each subframe and the second half display period in each subframe so that the sum of the product of the length and the potential difference between the pixel electrode and the counter electrode is the same. Set the ratio to the total length of the parts.
When the above relationship is expressed by an expression, the following expression 1 is obtained.
S1p + S2p + S3p + ... + S (m-1) p + Smp = S1n + S2n + S3n + ... + S (m-1) p + Smn (1)
Here, m indicates the number of subframes in one frame, p indicates a positive voltage, and n indicates a negative voltage.

Each S represents the area of the hatched portion in FIG. 9, and is represented by Skp (1 ≦ k ≦ m) and Skn (1 ≦ k ≦ m) in the general formula.
In this case, control is performed so that Equation 1 is established in units of one frame, so that depending on the subframe, Tk_p ≠ Tk_n may occur or Tk_p = Tk_n may occur. Regarding SF1 to SF3 shown in FIG. 9, all are Tk_p ≠ Tk_n. That is, T1_p ≠ T1_n, T2_p ≠ T2_n, and T3_p ≠ T3_n.

By processing in this way, the amount of the voltage level shift Vsft generated can be compensated, and even if the voltage level shift occurs, it is possible to prevent a DC component from being generated in one frame.
Here, since the amount of the voltage level shift Vsft can be estimated empirically, the length Tk_p of the first half display period portion and the length Tk_n of the second half display period portion in each subframe are set in the control system (see FIG. It can be easily obtained by a computer or the like (not shown). FIG. 7 only shows an example of the display pattern, and depending on the display pattern, the display period may be set to be the same even in different subframes.

  In this way, when applying the display with the polarity reversed in the first half and the second half in each subframe, the symmetry of the applied voltage is optimized by optimizing the symmetry of the positive voltage and the negative voltage in units of frames. And the flickering of the image called flicker and the deterioration of the liquid crystal material due to DC voltage application can be suppressed.

It is a figure which shows schematic structure of the projection type display apparatus as an example of an image display apparatus. It is a graph which shows the relationship between the drive voltage which drives a liquid crystal, and emitted light intensity. It is a schematic block diagram which shows the drive part and display part of the image display apparatus in this invention. It is a schematic block block diagram of the display part of the image display apparatus applied to this invention. It is a schematic block diagram of a pixel drive circuit in a display unit of an image display device applied to the present invention. It is a timing chart which shows the rough timing of the voltage given to the pixel electrode applied to this invention, and a counter electrode. It is a figure which shows an example of the display pattern between a gradation level and a sub-frame. It is explanatory drawing for demonstrating the problem of the conventional image display apparatus. It is explanatory drawing which shows an example of the drive method of the image display apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 41 ... Drive part, 42 ... Display part, 50 ... Sample hold part, 60 ... Switch part, 101 ... Semiconductor substrate, 102 ... Transparent substrate, CE ... Counter electrode, LC ... Liquid crystal layer, PE ... Pixel electrode, Px ... Pixel.

Claims (1)

A plurality of pixels are formed in a matrix by disposing a plurality of pixel electrodes having an alignment film formed on the surface and a counter electrode formed in common by forming an alignment film on the surface through a liquid crystal therebetween. When an image is displayed by applying a digitized pixel signal to the display unit, each frame of the image signal is configured by a plurality of subframes having a display period shorter than one frame period, and a desired subframe is formed. In a driving method of an image display apparatus for selectively turning on or off a frame and displaying an image of one frame at a plurality of gradations,
The display period of each subframe is divided into a first half display period part and a second half display period part, and the polarity is reversed between the first half display period part and the second half display period part, and the length of the first half display period part in each subframe And the sum of the product of the potential difference between the pixel electrode and the counter electrode, and the sum of the products of the length of the second half display period and the potential difference between the pixel electrode and the counter electrode in each subframe are the same. An image display device characterized in that a ratio between the total length of the first half display period portion in each subframe and the total length of the second half display period portion in each subframe is set. Driving method.

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