JP2008118162A - Printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed wiring board capable of enhancing connection reliability of a solder pad. <P>SOLUTION: An opening 71 of a solder resist layer 70 is formed such that the opening 71 overlaps a peripheral portion of a solder pad 75 by 5 μm and overlapping thickness thereof is 20 μm; and therefore, the solder pad 75 does not come off from an interlayer insulating layer 150 and the connection reliability is improved. Furthermore, since the solder pad 75 is closely adhered to the solder resist layer 70, the underlying interlayer insulating layer 150 hardly cracks. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a printed wiring board for forming a package substrate or the like for mounting an integrated circuit chip via solder bumps.

FIG. 11 shows a printed wiring board constituting a package substrate according to the prior art. In the printed wiring board 210, solder bumps 276 are formed in order to mount the IC chip 290, and a solder resist layer 270 is provided so that the solder bumps 276 are not fused to each other.

FIG. 12A shows the F portion of FIG. 11 in an enlarged manner. FIG. 12B shows a view taken in the direction of arrow B in FIG. 12A, that is, the surface of the solder resist layer 270. As shown in FIG. 12A, the solder resist layer 270 is provided on the conductor circuit 258, and is formed so that the opening 271 does not overlap the solder pad 275 as shown in FIG. 12B. . A solder bump 276U is formed by providing a nickel plating layer 272 and a gold plating layer 274 on the solder pad 275, and further printing and reflowing a solder paste or the like.
Japanese Patent Laid-Open No. 10-93235

However, since the solder pad 275 of the prior art has low adhesion to the lower interlayer resin insulation layer 250, it is easy to peel off and the connection reliability with the IC chip 290 may be lacking. Further, when thermal contraction is repeated during use, cracks C are generated in the lower interlayer resin insulation layer 250 as shown in FIG. 12A starting from the wall surface of the solder pad 275, and the lower side of the interlayer resin insulation layer 250 The conductor circuit 358 may be disconnected.

In order to deal with such a problem, for example, in Japanese Patent Laid-Open No. 10-93235, the side surface of the solder pad 275 is tapered as shown in FIG. 12C, and the solder pad 275 is brought into contact with the solder resist layer 270. A technique for pressing with a solder resist 270 has been proposed. However, in this technique, since the thickness of the solder resist layer 270 and the thickness of the solder pad 275 are the same, the solder resist cannot sufficiently hold the solder pad. Peeling occurs between the lower interlayer resin insulation layer 250.

SUMMARY An advantage of some aspects of the invention is to provide a printed wiring board capable of improving the connection reliability of solder pads.

In order to achieve the above object, the invention of claim 1 is directed to a core substrate, a build-up wiring layer in which an interlayer resin insulation layer and a conductor circuit are alternately laminated on the core substrate, A solder resist layer formed on the interlayer resin insulation layer located on the outermost layer and having an opening exposing a portion of the conductor circuit on the surface of the interlayer resin insulation layer, and exposed from the opening in the conductor circuit In the printed wiring board in which solder pads for mounting semiconductor components are provided in the place,
The surface of the interlayer resin insulation layer located in the outermost layer of the build-up multilayer wiring board is roughened,
And the said conductor circuit provided with the said solder pad has a roughening surface on the whole surface including the side surface, and has a solder resist layer which comprises the periphery of the said opening with thickness in the peripheral part of the said conductor circuit provided with the said solder pad. A technical feature is that they are formed to overlap.

In the first aspect of the invention, since the solder resist layer forming the periphery of the opening is formed so that the solder resist layer overlaps the peripheral portion of the solder pad with a thickness, the solder resist layer is different from JP-A-1-93235. -The resist layer presses the solder pad from above, and the solder pad is not peeled off from the lower insulating layer, thereby improving connection reliability. Further, since the solder pad and the solder resist layer are brought into close contact with each other, cracks are unlikely to occur in the lower insulating layer (interlayer resin insulating layer).

It is desirable to form an opening in the solder resist layer so as to overlap the peripheral part of the solder pad by 3 μm or more. By holding the solder pad, it is possible to completely prevent the solder pad from peeling and the insulating layer from cracking during the cooling / heating cycle and moisture absorption.

It is desirable that the overlapping thickness of the solder resist layer on the periphery of the solder pad be 10 μm or more. The solder pad is not peeled off from the lower insulating layer, and the connection reliability is improved.

The thickness of the solder resist layer is desirably 10 to 50 μm. If it is less than 10 μm, it will not function as a solder dam that stops the flow of solder, and if it exceeds 50 μm, it will be difficult to form an opening, and contact with the solder body constituting the solder bump will cause cracks in the solder body. It is.

The opening of the solder resist layer is preferably circular with a diameter of 250 μm or less. The smaller the solder pad diameter is, the more easily peeling occurs, and the effect is remarkable when forming a solder pad having a diameter small enough to provide an opening having a diameter of 250 μm or less.

The solder resist layer is preferably made of a novolak type epoxy resin or an acrylate of a novolak type epoxy resin, and preferably contains an imidazole curing agent as a curing agent. The solder resist layer having such a configuration has an advantage that lead migration (a phenomenon in which lead ions diffuse in the solder resist layer) is small. Moreover, this solder resist layer is a resin layer obtained by curing an acrylate of a novolak type epoxy resin with an imidazole curing agent, and has excellent heat resistance and alkali resistance, and does not deteriorate even at a temperature at which the solder melts (around 200 ° C.). It is not decomposed by a strongly basic plating solution when performing nickel plating and gold plating.

Various types of resins can be used as the solder resist layer. For example, bisphenol A type epoxy resin, bisphenol A type epoxy resin acrylate, novolak type epoxy resin, novolak type epoxy resin acrylate can be used as an amine curing agent or imidazole curing agent. A resin cured with an agent can be used.

On the other hand, since such a solder resist layer is made of a resin having a rigid skeleton, peeling may occur. For this reason, peeling of a soldering resist layer can also be prevented by providing a reinforcement layer.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid, methacrylic acid or the like can be used.

The imidazole curing agent is desirably liquid at 25 ° C. This is because uniform mixing is possible if it is liquid. Examples of such liquid imidazole curing agents include 1-benzyl-2-methylimidazole (product name: 1B2MZ), 1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN), 4-methyl-2- Ethylimidazole (product name: 2E4MZ) can be used.

The amount of the imidazole curing agent added is desirably 1 to 10% by weight based on the total solid content of the solder resist composition. This is because uniform mixing is easy if the added amount is within this range.

It is desirable that the pre-curing composition of the solder resist uses a glycol ether solvent as a solvent. A solder resist layer using such a composition does not generate free acid and does not oxidize the copper pad surface. In addition, it is less harmful to the human body.

As such a glycol ether solvent, at least one selected from the following structural formulas, particularly preferably diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C.
_{CH 3 O- (CH 2 CH 2} O) n -CH 3 (n = 1~5)
The glycol ether solvent is preferably 10 to 70 wt% with respect to the total weight of the solder resist composition.

In addition to the solder resist composition described above, various antifoaming agents and leveling agents, thermosetting resins for improving heat resistance and base resistance and providing flexibility, and photosensitive for improving resolution. A monomer can be added. For example, the leveling agent is preferably made of an acrylic ester polymer. Further, Irgacure I907 manufactured by Ciba Geigy is preferable as the initiator, and DETX-S manufactured by Nippon Kayaku is preferable as the photosensitizer. Furthermore, you may add a pigment | dye and a pigment to a soldering resist composition. This is because the wiring pattern can be concealed. It is desirable to use phthalocyanine green as this dye.

As the thermosetting resin as an additive component, a bisphenol type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin. When the basic resistance is important, the former is required when the viscosity is reduced (when the coating property is important). The latter is better.

As the photosensitive monomer as an additive component, a polyvalent acrylic monomer can be used. This is because the polyvalent acrylic monomer can improve the resolution. For example, Nippon Kayaku DPE-6A and Kyoeisha Chemical R-604 can be used as the polyvalent acrylic monomer.

Moreover, these solder resist compositions are 0.5-10 Pa.s at 25 degreeC, More preferably, 1-10 Pa.s is good. This is because the viscosity is easy to apply with a roll coater.

In the present invention, it is desirable to use an electroless plating adhesive as the insulating layer or interlayer insulating layer. This electroless plating adhesive is optimally prepared by dispersing heat-resistant resin particles that are soluble in a cured acid or oxidizing agent in an uncured heat-resistant resin that is sparingly soluble in acid or oxidizing agent. is there. By treating with an acid and an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface made of crucible-like anchors can be formed on the surface.

In the above electroless plating adhesive, the cured heat-resistant resin particles include (1) heat-resistant resin powder having an average particle size of 10 μm or less, and (2) heat-resistant resin having an average particle size of 2 μm or less. Aggregated particles obtained by agglomerating powder, (3) a mixture of heat-resistant powder resin powder having an average particle diameter of 2 to 10 μm and heat-resistant resin powder having an average particle diameter of 2 μm or less, and (4) an average particle diameter of 2 to 10 μm Pseudo-particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle size of 2 μm or less to the surface of the heat-resistant resin powder, and (5) an average particle size of 0.1 to 0.8 μm A heat-resistant powder resin powder having a mean particle diameter of more than 0.8 μm and less than 2 μm, and (6) a heat-resistant powder resin powder having an average particle diameter of 0.1 to 1.0 μm It is desirable. This is because more complex anchors can be formed.

The depth of the roughened surface is preferably Rmax = 0.01 to 20 μm. This is to ensure adhesion. Particularly in the semi-additive method, 0.1 to 5 μm is preferable. This is because the electroless plating film can be removed while ensuring adhesion.

The heat-resistant resin hardly soluble in the acid or the oxidizing agent may be composed of “a resin composite made of a thermosetting resin and a thermoplastic resin” or “a resin composite made of a photosensitive resin and a thermoplastic resin”. desirable. This is because the former has high heat resistance, and the latter can form a via hole opening by photolithography.

As the thermosetting resin, an epoxy resin, a phenol resin, a polyimide resin, or the like can be used. When sensitizing, methacrylic acid, acrylic acid, and the like are subjected to an acrylic reaction with a thermosetting group. In particular, epoxy resin acrylate is most suitable. As the epoxy resin, a novolak type epoxy resin such as a phenol novolac type or a cresol novolak type, a dicyclopentadiene-modified alicyclic epoxy resin, or the like can be used.

As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyetherimide (PI) and the like can be used. The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is preferably thermosetting resin (photosensitive resin) / thermoplastic resin = 95/5 to 50/50. This is because a high toughness value can be secured without impairing the heat resistance.

The mixing weight ratio of the heat resistant resin particles is 5 to 50% by weight, preferably 10 to 40% by weight, based on the solid content of the heat resistant resin matrix. The heat-resistant resin particles are preferably an amino resin (melamine resin, urea resin, guanamine resin), an epoxy resin, or the like. The adhesive may be composed of two layers having different compositions.

[Example]
Hereinafter, a printed wiring board and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. First, the configuration of the printed wiring board 10 according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board (package substrate) 10 before mounting the integrated circuit chip 90, which is a semiconductor component, and FIG. 8 shows a cross section of the printed wiring board 10 with the integrated circuit chip 90 mounted thereon. Yes. As shown in FIG. 8, the integrated circuit chip 90 is mounted on the upper surface side of the printed wiring board 10, and the lower surface side is connected to the daughter board 94.

The configuration of the printed wiring board will be described in detail with reference to FIG. In the printed wiring board 10, build-up wiring layers 80 </ b> A and 80 </ b> B are formed on the front and back surfaces of the multilayer core substrate 30. The built-up layer 80A includes an interlayer resin insulation layer 50 in which via holes 60 and conductor circuits 58 are formed, and an interlayer resin insulation layer 150 in which via holes 160 and conductor circuits 158 are formed. The build-up wiring layer 80B includes an interlayer resin insulation layer 50 in which the via hole 60 and the conductor circuit 58 are formed, and an interlayer resin insulation layer 150 in which the via hole 160 and the conductor circuit 158 are formed.

Solder bumps 76U for connection to the lands 92 (see FIG. 8) of the integrated circuit chip 90 are disposed on the upper surface side. The solder bump 76U is connected to the through hole 36 via the via hole 160 and the via hole 60. On the other hand, solder bumps 76D for connection to the lands 96 (see FIG. 8) of the daughter board (sub board) 94 are disposed on the lower surface side. The solder bump 76D is connected to the through hole 36 via the via hole 160 and the via hole 60. The solder bumps 76U and 76D have a solder body 77 disposed on a solder pad 75 in which a nickel plating layer 72 and a gold plating layer 74 are formed on the conductor circuit 158 and the via hole 160 in the opening 71 of the solder resist 70. It becomes.

As shown in FIG. 8, an underfill 88 for resin sealing is disposed between the printed wiring board 10 and the IC chip 90. Similarly, an underfill 88 is disposed between the printed wiring board 10 and the mother board 84.

FIG. 9A shows an enlarged view of a solder resist layer and solder pads indicated by G in FIG. Further, FIG. 9B shows a view taken in the direction of arrow H in FIG. 9A, that is, the surface of the solder resist layer 70. In the printed wiring board 10 of the present embodiment, as shown in FIG. 9B, the opening 71 of the solder resist layer 70 is formed so as to overlap with the peripheral portion of the solder pad 75 by 3 μm or more (5 μm in the embodiment). is there. For this reason, the solder pad 75 is pressed by the overlap of the solder resist 70 and the solder pad 75 is not peeled off from the lower interlayer resin insulation layer 150, and the connection reliability between the IC chip 90 and the daughter board 94 is improved. is doing. Further, since the solder pad 75 and the solder resist layer 70 are in close contact as shown in FIG. 9A, the printed wiring board differs from the conventional printed wiring board described above with reference to FIG. However, even if the thermal contraction is repeated, the lower interlayer resin insulation layer 150 is difficult to crack.

The opening 71 of the solder-resist layer 70 may be tapered as shown in FIG. 9A, or may have a vertical wall surface as shown in FIG. . Further, as shown in FIG. 13B, the solder-resist layer 70 may be slightly raised on the solder pad 75.

Further, in the printed wiring board of the present embodiment, as shown in FIG. 9A, the overlapping thickness of the solder resist layer 70 around the solder pad 75 is 10 μm or more (20 μm in the embodiment). The solder pad 75 is pressed by the overlap of the solder resist 70, so that the solder pad 75 is not peeled off from the lower interlayer resin insulation layer 150, and connection reliability is improved.

Furthermore, in the printed wiring board of the present embodiment, as shown in FIG. 9A, the thickness of the solder resist layer 70 is set to 40 μm. Here, the thickness of the solder resist layer 70 is preferably 20 to 50 μm. If it is less than 20 μm, it does not function as a solder dam that stops the flow of solder during reflow, and if it exceeds 50 μm, it becomes difficult to form the opening 70, and it contacts the solder body 77 constituting the solder bumps 76 U and 76 D. This is because it causes cracks on the solder body 77 side.

Subsequently, the method for producing the printed wiring board shown in FIG. 7 will be specifically described with an example. First, A. B. Adhesive for electroless plating, Interlayer resin insulation, C.I. Resin filler, D.I. The composition of the solder resist will be described.

A. Raw material composition for preparing electroless plating adhesive (upper layer adhesive)
[Resin composition (1)] 35 parts by weight of a resin solution prepared by dissolving 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) in DMDG at a concentration of 80 wt%, photosensitive monomer (Toa It was obtained by stirring and mixing 3.15 parts by weight of a synthetic product, Aronix M315), 0.5 parts by weight of an antifoaming agent (Sanopco, S-65) and 3.6 parts by weight of NMP.

[Resin composition (2)] Polyether sulfone (PES) 12 parts by weight, epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd., polymer pole) with an average particle size of 1.0 μm, 7.2 parts by weight, and an average particle size of 0.5 μm After mixing 3.09 parts by weight, 30 parts by weight of NMP was further added, and the mixture was stirred and mixed with a bead mill.

[Curing agent composition (3)] 2 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN), 2 parts by weight of photoinitiator (manufactured by Ciba Geigy, Irgacure I-907), photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight were obtained by stirring and mixing.

B. Raw material composition for preparing interlayer resin insulation (adhesive for lower layer)
[Resin composition (1)] 35 parts by weight of a resin solution prepared by dissolving 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) in DMDG at a concentration of 80 wt%, photosensitive monomer (Toa A synthetic product, Aronix M315) 4 parts by weight, an antifoaming agent (manufactured by Sannopco, S-65) 0.5 part by weight and NMP 3.6 parts by weight were obtained by stirring and mixing.

[Resin composition (2)] After mixing 12 parts by weight of polyethersulfone (PES) and 14.49 parts by weight of epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd., polymer pole) having an average particle size of 0.5 μm, further 30 weights of NMP Part was added and obtained by stirring and mixing with a bead mill.

[Curing agent composition (3)] 2 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN), 2 parts by weight of photoinitiator (manufactured by Ciba Geigy, Irgacure I-907), photosensitizer (manufactured by Nippon Kayaku) DETX-S) 0.2 parts by weight and 1.5 parts by weight of NMP were obtained by stirring and mixing.

C. Raw material composition for resin filler preparation [resin composition (1)]
100 parts by weight of bisphenol F type epoxy monomer (Oilized Shell, molecular weight 310, YL983U), SiO ₂ spherical particles with an average particle size of 1.6 μm coated with a silane coupling agent on the surface (manufactured by Admatech, CRS 1101-CE, here The maximum particle size is 170 mm by weight of the inner layer copper pattern (15 μm or less) described later, and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) is stirred and mixed, whereby the viscosity of the mixture is adjusted. It was obtained by adjusting to 45,000-49,000 cps at 23 ± 1 ° C.
(Curing agent composition (2))
6.5 parts by weight of imidazole curing agent (Shikoku Chemicals, 2E4MZ-CN).

D. Solder resist composition DMDG dissolved 60% by weight of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) with 50% epoxy acrylated photosensitizing oligomer (molecular weight 4000) dissolved in methyl ethyl ketone 80% by weight of bisphenol A type epoxy resin (Oka Chemical Shell, Epicoat 1001) 15.0 g, imidazole curing agent (Shikoku Chemicals, 2E4MZ-CN) 1.6 g, polyvalent acrylic monomer (Nippon Kayaku) R604) 3 g, 1.5 g polyvalent acrylic monomer (Kyoeisha Chemical Co., DPE6A), 0.71 g dispersion antifoam (Sannopco, S-65) are mixed, and the photoinitiator is mixed with this mixture. 2 g of benzophenone (manufactured by Kanto Chemical Co., Ltd.) A rudder resist composition was obtained. Viscosity was measured with a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm with rotor No. 4 and at 6 rpm with rotor No. 3.

Next, a method for manufacturing the printed wiring board 10 will be described with reference to FIGS.
E. Manufacture of printed wiring boards
(1) A copper-clad laminate 30A in which 18 μm copper foil 32 is laminated on both surfaces of a substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm was used as a starting material (FIG. 1A )reference). First, this copper-clad laminate 30A was drilled, subjected to electroless plating, and etched into a pattern to form inner layer copper patterns 34 and through holes 36 on both sides of the substrate 30 (FIG. 1B). )).

(2) The substrate 30 on which the inner layer copper pattern 34 and the through hole 36 are formed is washed with water, dried, and then used as an oxidation bath (blackening bath) such as NaOH (10 g / l), NaClO ₂ (40 g / l), Na _3. By the oxidation-reduction treatment using PO ₄ (6 g / l) and NaOH (10 g / l), NaBH ₄ (6 g / l) as a reducing bath, a roughened layer 38 is formed on the surface of the inner layer copper pattern 34 and the through hole 36. (See FIG. 1C).

(3) The raw material composition for preparing the C resin filler was mixed and kneaded to obtain a resin filler.
(4) By applying the resin filler 40 obtained in (3) above to both surfaces of the substrate 30 using a roll coater within 24 hours after preparation, the conductor circuit (inner layer copper pattern) 34 and the conductor circuit 34 And the through holes 36 are filled and dried at 70 ° C. for 20 minutes, and the resin filler 40 is similarly filled between the conductor circuits 34 or in the through holes 36 on the other side, and is filled at 70 ° C. , And dried by heating for 20 minutes (see FIG. 1D).

(5) The surface of the inner layer copper pattern 34 or the land 36a of the through hole 36 is polished on one side of the substrate 30 after the processing of (4) by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Polishing was performed so that the resin filler 40 did not remain on the surface, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate (see FIG. 2E). Next, the resin filler 40 was cured by heat treatment at 100 ° C. for 1 hour, 120 ° C. for 3 hours, 150 ° C. for 1 hour, and 180 ° C. for 7 hours.

In this way, after removing the surface layer portion of the resin filler 40 filled in the through holes 36 and the like and the roughening layer 38 on the upper surface of the inner conductor circuit 34 and smoothing both surfaces of the substrate 30, the resin filler 40 and A wiring substrate was obtained in which the side surface of the inner layer conductor circuit 34 was firmly adhered through the roughened layer 38, and the inner wall surface of the through hole 36 and the resin filler 40 were firmly adhered through the roughened layer 38. . That is, by this step, the surface of the resin filler 40 and the surface of the inner layer copper pattern 34 are flush.

(6) The substrate 30 on which the conductor circuit 34 is formed is alkali degreased and soft etched, and then treated with a catalyst solution composed of paradium chloride and an organic acid to give a Pd catalyst and activate the catalyst. Copper sulfate 3.2 × 10 ⁻² mol / l, nickel sulfate 3.9 × 10 ⁻³ mol / l, complexing agent 5.4 × 10 ⁻² mol / l, sodium hypophosphite 3.3 × An electroless plating solution comprising 10 ⁻¹ mol / l, boric acid 5.0 × 10 ⁻¹ mol / l, surfactant (manufactured by Nissin Chemical Industry, Surfir 465) 0.1 g / l, PH = 9 The needle-like alloy made of Cu—Ni—P is formed on the surface of the land 36a of the conductor circuit 34 and the through hole 36 by oscillating longitudinally and transversely at a rate of once every 4 seconds after 1 minute of immersion. A coating layer and a roughening layer 42 were provided (see FIG. 2F).

Furthermore, a Cu—Sn substitution reaction was carried out under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 35 ° C., PH = 1.2, and a thickness of 0.3 μm Sn was formed on the surface of the roughened layer. A layer (not shown) was provided.

(7) The raw material composition for preparing the interlayer resin insulation B was mixed by stirring and adjusted to a viscosity of 1.5 Pa · s to obtain an interlayer resin insulation (for the lower layer). Next, the raw material composition for preparing an electroless plating adhesive of A was mixed by stirring and adjusted to a viscosity of 7 Pa · s to obtain an electroless plating adhesive solution (for the upper layer).

(8) Apply the interlayer resin insulation (for lower layer) 44 having a viscosity of 1.5 Pa · s obtained in (7) on both sides of the substrate in (6) with a roll coater within 24 hours after preparation. After standing for 20 minutes in the state, drying (prebaking) at 60 ° C. for 30 minutes, and then preparing a photosensitive adhesive solution (for upper layer) 46 having a viscosity of 7 Pa · s obtained in (7) above. The coating was applied within 24 hours and allowed to stand for 20 minutes in a horizontal state, followed by drying (prebaking) at 60 ° C. for 30 minutes to form an adhesive layer 50α having a thickness of 35 μm (see FIG. 2G). .

(9) A photomask film 51 on which a black circle 51a of 85 μmφ is printed as shown in FIG. 2 (H) is adhered to both surfaces of the substrate 30 on which the adhesive layer has been formed in (8), and an ultra high pressure mercury lamp is used. The exposure was performed at 500 mJ / cm ² . The substrate 30 is spray-developed with DMTG solution, and the substrate 30 is exposed at 3000 mJ / cm ² with an ultra-high pressure mercury lamp, followed by heat treatment (post treatment at 100 ° C. for 1 hour, 120 ° C. for 1 hour, and then 150 ° C. for 3 hours. By baking, an interlayer resin insulating layer (two-layer structure) 50 having a thickness of 35 μm and having an opening (via hole forming opening) 48 of 85 μmφ excellent in dimensional accuracy equivalent to a photomask film was formed (FIG. 3 (I)). Note that a tin plating layer (not shown) was partially exposed in the opening 48 serving as a via hole.

(10) The substrate 30 in which the opening 48 is formed is immersed in chromic acid for 19 minutes, and the epoxy resin particles present on the surface of the interlayer resin insulation layer 50 are dissolved and removed, whereby the surface of the interlayer resin insulation layer 50 is removed. After roughening (see FIG. 3 (J)), it was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water. Further, a palladium catalyst (manufactured by Atotech) is applied to the surface of the substrate that has been roughened (roughening depth: 6 μm), whereby a catalyst is formed on the surface of the interlayer resin insulation layer 50 and the inner wall surface of the via hole opening 48. I attached the nucleus.

(11) The substrate was immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film 52 having a thickness of 0.6 μm over the entire rough surface (FIG. 3 (K)).
[Electroless plating aqueous solution]
EDTA 150 g / l
Copper sulfate 20 g / l
HCHO 30 ml / l
NaOH 40 g / l
α, α'-bipyridyl 80 mg / l
PEG 0.1 g / l
[Electroless plating conditions]
30 minutes at a liquid temperature of 70 ° C

(12) A commercially available photosensitive dry film is pasted on the electroless copper plating film 52 formed in the above (11), a mask is placed, exposed at 100 mJ / cm ² , and developed with 0.8% sodium carbonate. A plating resist 54 having a thickness of 15 μm was provided (see FIG. 3L).

(13) Next, electrolytic copper plating was applied to the non-resist forming portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 4M).
(Electrolytic plating aqueous solution)
Sulfuric acid 180 g / l
Copper sulfate 80 g / l
Additive (manufactured by Atotech Japan, Kaparaside GL) 1 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
30 minutes
Temperature room temperature

(14) After stripping and removing the plating resist 54 with 5% KOH, the electroless plating film 52 under the plating resist is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless copper plating film 52 is removed. Then, a conductor circuit 58 and a via hole 60 having a thickness of 18 μm made of the electrolytic copper plating film 56 were formed (FIG. 4 (N)).

(15) The same treatment as in (6) was performed to form a roughened surface 62 made of Cu—Ni—P on the surface of the conductor circuit 58 and the via hole 60, and further Sn substitution was performed on the surface (FIG. 4). (See (O)).
(16) By repeating the steps (7) to (15), the upper interlayer resin insulation layer 150 is further provided, and then the conductor circuit 158 and the via hole 160 are formed to obtain a multilayer wiring board (FIG. 4). (See (P)). However, Sn substitution was not performed on the roughened surface 62 formed on the surfaces of the conductor circuit 158 and the via hole 160.

(17) On the both surfaces of the substrate 30 obtained in (16) above, The solder resist composition 70α described in (1) was applied in a thickness of 45 μm (see FIG. 5 (Q)). Next, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a photomask film (not shown) having a thickness of 5 mm on which a circular pattern (mask pattern) is drawn is placed in close contact. The film was exposed to 1000 mJ / cm ² of ultraviolet rays and developed with DMTG. Further, heat treatment was performed at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, and the solder pad part (including the via hole and its land part) was opened (opened). A solder resist layer (thickness 20 μm) 70 having a diameter (200 μm) 71 was formed (see FIG. 5R).

(18) Next, pH = 4.5 consisting of nickel chloride 2.31 × 10 ⁻¹ mol / l, sodium hypophosphite 2.8 × 10 ⁻¹ mol / l, sodium citrate 1.85 × 10 ⁻¹ mol / l The substrate 30 was immersed in the electroless nickel plating solution for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Further, the substrate was made of potassium gold cyanide 4.1 × 10 ⁻² mol / l, ammonium chloride 1.87 × 10 ⁻¹ mol / l, sodium citrate 1.16 × 10 ⁻¹ mol / l, sodium hypophosphite 1.7 × 10 ^-1 mol / l in an electroless gold plating solution at 80 ° C. for 7 minutes and 20 seconds to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer. Solder pads 75 were formed on the conductor circuit 158 (see FIG. 6S).

(19) Then, solder paste is printed in the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps (solder bodies) 76U and 76D, and the printed wiring board 10 is formed ( (See FIG. 6 (T)).

Such a printed wiring board can peel the solder pad and the solder resist layer even in a heat cycle test of -52 to 125 ° C and a pressure cooker test of 121 ° C, 2 atm and 100% relative humidity. Neither does the insulating layer crack. On the other hand, in the printed wiring board shown in FIG. 12C, a crack occurred in the insulating layer at the boundary between the solder pad and the solder resist, and peeling occurred between the solder pad and the solder resist. .

Next, placement of the IC chip on the printed wiring board 10 and attachment to the daughter board 94 will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Thereafter, a sealing resin that becomes the underfill 88 is filled between the IC chip 90 and the printed wiring board 10. Similarly, the daughter board 94 is attached to the solder bumps 76D of the printed wiring board 10 by reflow, and a sealing resin to be the underfill 88 is filled.

FIG. 10 shows a printed wiring board according to the second embodiment of the present invention. In the printed wiring board according to the second embodiment, a reinforcing layer 98 is formed on the solder resist layer 70. In such a configuration, the peeling of the solder resist layer 70 is completely prevented, and the solder pads 75 are more firmly pressed toward the interlayer resin insulating layer 150, thereby improving connection reliability.

FIG. 1A, FIG. 1B, FIG. 1C, and FIG. 1D are manufacturing process diagrams of a printed wiring board according to the first embodiment of the present invention. 2E, FIG. 2F, FIG. 2G, and FIG. 2H are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. 3 (I), FIG. 3 (J), FIG. 3 (K), and FIG. 3 (L) are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. 4 (M), FIG. 4 (N), FIG. 4 (O), and FIG. 4 (P) are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS. 5Q and 5R are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. 6 (S) and 6 (T) are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. It is sectional drawing of the printed wiring board which concerns on 1st Example of this invention. It is sectional drawing which shows the state which mounted the IC chip in the printed wiring board concerning 1st Example of this invention. FIG. 9A is an enlarged view of a portion G in FIG. 7, and FIG. 9B is a view taken in the direction of arrow H in FIG. 9A. It is sectional drawing of the printed wiring board which concerns on 2nd Example of this invention. It is sectional drawing of the printed wiring board which concerns on a prior art. FIG. 12A is an enlarged view of a portion F in FIG. 11, FIG. 12B is a view taken in the direction of arrow B in FIG. 12A, and FIG. It is sectional drawing of a wiring board. 13A and 13B are cross-sectional views of the solder resist opening of the printed wiring board according to the present invention.

Explanation of symbols

30 Core substrate 50 Interlayer resin insulation layer 58 Conductor circuit 60 Via hole 70 Solder resist 71 Opening 72 Nickel plating layer 74 Gold plating layer 75 Solder pad 150 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole

Claims (3)

Formed on a core substrate, a buildup wiring layer in which an interlayer resin insulation layer and a conductor circuit are alternately laminated on the core substrate, and an interlayer resin insulation layer located on the outermost layer of the buildup wiring layer And a solder resist layer having an opening exposing a part of the conductor circuit on the surface of the interlayer resin insulation layer, and a solder pad for mounting a semiconductor component is provided at a position exposed from the opening in the conductor circuit. In the printed wiring board provided,
The surface of the interlayer resin insulation layer located in the outermost layer of the build-up multilayer wiring board is roughened,
And the said conductor circuit provided with the said solder pad has a roughening surface on the whole surface including the side surface, and has a solder resist layer which comprises the periphery of the said opening with thickness in the peripheral part of the said conductor circuit provided with the said solder pad. A printed wiring board characterized by being formed to overlap. 2. The printed wiring board according to claim 1, wherein an inner layer conductor circuit is formed on the substrate, and the inner layer conductor circuit and the solder pad are connected via a via hole. The printed wiring board according to claim 2, wherein the solder pad is provided on the via hole.

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