JP2000058710A - Printed wiring board - Google Patents

Abstract

(57) [Problem] To provide a printed wiring board capable of improving the connection reliability of a solder pad. SOLUTION: An opening 71 of a solder resist layer 70 is formed.
Since the solder pad 75 is formed so as to overlap the peripheral portion of the solder pad 75 by 5 μm and the thickness of the overlap is 20 μm, the solder pad 75 does not peel off from the interlayer resin insulating layer 150, and the connection reliability is improved. Also, the solder pad 7
5 and the solder resist layer 70 are adhered to each other, so that the lower interlayer resin insulating layer 150 is less likely to crack.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a printed wiring board for forming a package substrate or the like for mounting an integrated circuit chip via solder bumps.

[0002]

2. Description of the Related Art FIG. 11 shows a printed wiring board constituting a package substrate according to the prior art. The printed wiring board 2
In FIG. 10, in order to mount the IC chip 290, solder bumps 276 are formed, and a solder resist layer 270 is provided so that the solder bumps 276 do not fuse with each other.

FIG. 12A is an enlarged view of a portion F in FIG. FIG. 12B is a view taken in the direction of arrow B in FIG. 12A, that is, the surface of the solder resist layer 270. As shown in FIG. 12A, the solder resist layer 270 is provided on the conductor circuit 258,
As shown in FIG. 12B, the opening 271 is
75 are formed so as not to overlap. A nickel plating layer 272 and a gold plating layer 274 are provided on the solder pad 275.
Are provided, and the solder bumps 276U are formed by printing and reflowing a solder paste or the like.

[0004]

However, the solder pad 275 of the prior art has a lower interlayer resin insulation layer 250.
Adhesion is low, so it is easy to peel off and the IC chip 290
Connection reliability was sometimes lacking. Further, if heat shrinkage is repeated during use, cracks C are formed in the lower interlayer resin insulation layer 250 starting from the wall surface of the solder pad 275 as shown in FIG. Of the conductor circuit 358 in some cases.

In order to cope with such a problem, for example, in Japanese Patent Application Laid-Open No. Hei 10-93235, a taper is provided on the side surface of the solder pad 275 as shown in FIG. A technique has been proposed in which the pad 275 is pressed by the solder resist 270. However, in this technique, since the thickness of the solder resist layer 270 and the thickness of the solder pad 275 are the same, the solder resist cannot sufficiently hold down the solder pad,
Peeling occurs between the solder pad 275 and the lower interlayer resin insulation layer 250 during a cooling / heating cycle or moisture absorption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a printed wiring board capable of improving the connection reliability of a solder pad.

[0007]

In order to achieve the above object, the printed wiring board of the present invention is provided with a solder pad for mounting a semiconductor component on a substrate, and an opening for exposing the solder pad. In a printed wiring board on which a solder resist layer is formed, an opening of the solder resist layer is provided on the solder pad, and a solder resist layer constituting a periphery of the opening overlaps a peripheral portion of the solder pad with a thickness. It is a technical feature that it is formed as described above.

[0008] According to a second aspect, in the first aspect,
A technical feature is that the opening of the solder resist layer is formed so as to overlap the peripheral portion of the half pad by 3 μm or more.

A third aspect of the present invention is characterized in that, in the first aspect, the thickness of the overlapping portion of the solder resist layer in the peripheral portion of the solder pad is set to 10 μm or more.

According to a fourth aspect, in the first aspect, the thickness of the solder resist layer is set to 10 to 50 μm.

A fifth aspect of the present invention is characterized in that, in the first aspect, the opening of the solder resist layer has a circular shape with a diameter of 250 μm or less.

According to a sixth aspect of the present invention, in the first aspect, the solder resist layer is made of a novolak epoxy resin or a novolak epoxy acrylate, and contains an imidazole curing agent as a curing agent.

According to the first aspect of the present invention, since the opening of the solder resist layer constituting the periphery of the opening is formed so as to overlap with the peripheral portion of the solder pad with a thickness, the opening of the solder resist layer is disclosed in JP-A-1-93235. No, solder
The resist layer presses the solder pad from above, and the solder pad does not peel from the lower insulating layer, thereby improving connection reliability. Further, since the solder pad and the solder resist layer are brought into close contact with each other, cracks are less likely to occur in the lower insulating layer (interlayer resin insulating layer).

According to the second aspect of the present invention, the opening of the solder resist layer is formed so as to overlap the peripheral portion of the solder pad by 3 μm or more.
Peeling of the solder pad and cracking of the insulating layer at the time of moisture absorption can be completely prevented.

According to the third aspect of the present invention, the thickness of the solder resist layer at the peripheral portion of the solder pad is 10 μm.
As described above, the solder pad does not peel from the lower insulating layer, and the connection reliability is improved.

In the present invention, the thickness of the solder resist layer is set to 10 to 50 μm. If it is less than 10 μm, it will not function as a solder dam for blocking the flow of solder, and if it exceeds 50 μm, it will be difficult to form an opening, and it will come into contact with the solder body constituting the solder bump and cause cracks in the solder body. It is.

According to the present invention, the opening of the solder resist layer has a circular shape with a diameter of 250 μm or less. The smaller the diameter of the solder pad, the easier the peeling occurs, and
The effect is remarkable when a solder pad having a diameter small enough to provide an opening of 0 μm or less is formed.

According to the sixth aspect of the present invention, the solder resist layer is made of a novolak epoxy resin or an acrylate of a novolak epoxy resin, and contains an imidazole curing agent as a curing agent. The solder resist layer having such a configuration has an advantage that migration of lead (a phenomenon in which lead ions diffuse in the solder resist layer) is small. Moreover, this solder resist layer is a resin layer obtained by curing an acrylate of a novolak type epoxy resin with an imidazole curing agent, has excellent heat resistance and alkali resistance, and does not deteriorate even at a temperature at which the solder melts (around 200 ° C.)
It does not decompose with a strongly basic plating solution when performing nickel plating and gold plating.

Various resins can be used for the solder resist layer. For example, bisphenol A type epoxy resin, acrylate of bisphenol A type epoxy resin, novolak type epoxy resin, acrylate of novolak type epoxy resin may be used as an amine curing agent. Or a resin cured with an imidazole curing agent or the like.

On the other hand, such a solder resist layer is
Since it is composed of a resin having a rigid skeleton, peeling may occur. Therefore, the provision of the reinforcing layer can also prevent the solder resist layer from peeling off.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid, methacrylic acid or the like can be used.

The above imidazole curing agent is desirably liquid at 25 ° C. This is because a liquid can be uniformly mixed. As such a liquid imidazole curing agent,
1-benzyl-2-methylimidazole (product name: 1B2MZ),
1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (product name: 2E4MZ) can be used.

The addition amount of the imidazole curing agent is desirably 1 to 10% by weight based on the total solid content of the solder resist composition. The reason for this is that if the added amount is within this range, uniform mixing is easy.

The composition before curing of the solder resist is as follows:
It is desirable to use a glycol ether-based solvent as the solvent. The solder resist layer using such a composition does not generate free acid and does not oxidize the copper pad surface. It is also less harmful to the human body.

As such a glycol ether-based solvent, one having the following structural formula, particularly preferably at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C. CH ₃ O— (CH ₂ CH ₂ O) _n —CH ₃ (n = 1 to 5) The amount of the glycol ether solvent is preferably 10 to 70% by weight based on the total weight of the solder resist composition.

The solder resist composition as described above includes, in addition to the above, various defoaming agents and leveling agents, thermosetting resins for improving heat resistance and base resistance and imparting flexibility.
A photosensitive monomer or the like can be added to improve the resolution. For example, as the leveling agent, one made of a polymer of an acrylate ester is preferable. The initiator is preferably Irgacure I907 manufactured by Ciba-Geigy, and the photosensitizer is DETX-S manufactured by Nippon Kayaku. further,
A dye or pigment may be added to the solder resist composition. This is because the wiring pattern can be hidden. It is desirable to use phthalocyanine green as this dye.

As the thermosetting resin as an additional component, a bisphenol-type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin, and when importance is attached to base resistance, the former is required to reduce viscosity (when importance is attached to coating properties). The latter is better.

As the photosensitive monomer as an additive component, a polyvalent acrylic monomer can be used.
This is because the polyvalent acrylic monomer can improve the resolution. For example, Nippon Kayaku's DPE-6A and Kyoeisha Chemical's R-
604 can be used.

These solder resist compositions may be used at a temperature of 25 ° C. in a range of 0.5 to 10 Pa · s,
-10 Pa · s is preferred. This is because the viscosity is easy to apply with a roll coater.

In the present invention, it is desirable to use an adhesive for electroless plating as the insulating layer or the interlayer insulating layer. The most suitable adhesive for electroless plating is one in which heat-resistant resin particles soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. is there. By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus-shaped anchor can be formed on the surface.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles particularly subjected to the curing treatment include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
Aggregated particles obtained by aggregating the following heat-resistant resin powder, a heat-resistant powder resin powder having an average particle size of 2 to 10 μm and an average particle size of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, and an average particle diameter of 0.1 to
0.8μm heat resistant resin powder and average particle size 0.8μ
m, and a mixture with a heat-resistant resin powder of less than 2 μm,
It is desirable to use a heat-resistant resin powder having an average particle size of 0.1 to 1.0 μm. This is because they can form more complex anchors.

The depth of the roughened surface is Rmax = 0.01 to 2
0 μm is preferred. This is to ensure adhesion. Particularly, in the semi-additive method, the thickness is preferably 0.1 to 5 μm. This is because the electroless plating film can be removed while ensuring adhesion.

The heat-resistant resin which is hardly soluble in an acid or an oxidizing agent includes a “resin composite composed of a thermosetting resin and a thermoplastic resin” or a “resin composite composed of a photosensitive resin and a thermoplastic resin”. It is desirable to become. This is because the former has high heat resistance, and the latter can form an opening for a via hole by photolithography.

As the thermosetting resin, epoxy resin, phenol resin, polyimide resin and the like can be used. In the case of photosensitization, methacrylic acid, acrylic acid, or the like is subjected to an acrylate reaction with a thermosetting group. Particularly, acrylate of epoxy resin is most suitable. As the epoxy resin, a novolak type epoxy resin such as a phenol novolak type and a cresol novolak type, and an alicyclic epoxy resin modified with dicyclopentadiene can be used.

As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PP
E), polyetherimide (PI) and the like can be used.
The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is: thermosetting resin (photosensitive resin) / thermoplastic resin = 95
/ 5 to 50/50 is preferred. This is because a high toughness value can be secured without impairing the heat resistance.

The weight ratio of the heat-resistant resin particles is 5 to 50% by weight based on the solid content of the heat-resistant resin matrix.
Desirably, the content is 10 to 40% by weight. As the heat-resistant resin particles, amino resin (melamine resin, urea resin, guanamine resin), epoxy resin and the like are preferable. The adhesive may be composed of two layers having different compositions.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A printed wiring board according to an embodiment of the present invention and a method of manufacturing the same will be described below with reference to the drawings. First, the configuration of the printed wiring board 10 according to the first embodiment of the present invention will be described with reference to FIGS. FIG.
8 shows a cross section of the printed wiring board (package substrate) 10 before mounting the integrated circuit chip 90 as a semiconductor component.
Shows a cross section of the printed wiring board 10 in a state where the integrated circuit chip 90 is mounted. As shown in FIG. 8, an integrated circuit chip 90 is mounted on the upper surface side of the printed wiring board 10, and the lower surface side is connected to the daughter board 94.

The configuration of the printed wiring board will be described in detail with reference to FIG. In the printed wiring board 10, the build-up wiring layers 80 are formed on the front and back surfaces of the multilayer core substrate 30.
A and 80B are formed. The built-up layer 80A
Is composed of an interlayer resin insulation layer 50 having via holes 60 and conductor circuits 58 formed therein, and an interlayer resin insulation layer 150 having via holes 160 and conductor circuits 158 formed therein.
Further, the build-up wiring layer 80B is
And an interlayer resin insulation layer 50 on which the conductor circuit 58 is formed,
It comprises a via hole 160 and an interlayer resin insulation layer 150 in which a conductor circuit 158 is formed.

On the upper surface side, solder bumps 76U for connection to lands 92 (see FIG. 8) of the integrated circuit chip 90 are provided. The solder bump 76U is in the via hole 16
0 and via hole 60 to through hole 36. On the other hand, on the lower surface side, a solder bump 76D for connection to a land 96 (see FIG. 8) of a daughter board (sub-board) 94 is provided. The solder bump 76D is connected to the through hole 36 via the via hole 160 and the via hole 60. The solder bumps 76U and 76D are formed in the openings 71 of the solder resist 70.
A solder body 77 is disposed on a solder pad 75 having a nickel plating layer 72 and a gold plating layer 74 formed on the conductor circuit 158 and the via hole 160 in the inside.

As shown in FIG. 8, the printed wiring boards 10 and I
An underfill 88 for performing resin sealing is provided between the underfill 88 and the C chip 90. Similarly, an underfill 88 is provided between the printed wiring board 10 and the motherboard 84.

FIG. 9A is an enlarged view of the solder resist layer and the solder pad indicated by G in FIG. FIG.
FIG. 9B is a view taken in the direction of arrow H in FIG. 9A, that is, the surface of the solder resist layer 70. Printed wiring board 10 of the present embodiment
Now, as shown in FIG. 9B, the solder resist layer 70
Is formed so as to overlap the peripheral portion of the solder pad 75 by 3 μm or more (5 μm in the embodiment). For this reason, the solder pad 70 is pressed down by the overlap of the solder resist 70, and the solder pad 75 does not peel off from the lower interlayer resin insulation layer 150, and
The connection reliability between the chip 90 and the daughter board 94 is improved. Also, as shown in FIG.
5 and the solder resist layer 70 are in close contact with each other, unlike the conventional printed wiring board described above with reference to FIG. Cracking is hard to occur in 150.

The opening 7 of the solder-resist layer 70
1 may be provided with a taper as shown in FIG. 9A, or may have a vertical wall surface as shown in FIG. Also, as shown in FIG.
The resist layer 70 may have a slightly raised shape on the solder pad 75.

Further, in the printed wiring board of this embodiment, as shown in FIG. 9A, the thickness of the solder resist layer 70 at the peripheral portion of the solder pad 75 is set to 10 μm or more (20 μm in this embodiment). Therefore, the solder pad 70 is pressed by the overlap of the solder resist 70, and the solder pad 75 is moved to the lower interlayer resin insulation layer 150.
The connection reliability is improved.

Further, in the printed wiring board of this embodiment, as shown in FIG. 9A, the thickness of the solder resist layer 70 is set to 40 μm. Here, the thickness of the solder resist layer 70 is preferably 20 to 50 μm. this is,
If it is less than 20 μm, it will not function as a solder dam for blocking the flow of solder at the time of reflow, and if it is more than 50 μm, it will be difficult to form an opening 70 and solder bumps 76U, 7
This is because it comes into contact with the solder body 77 constituting the 6D and causes a crack on the solder body 77 side.

Subsequently, a method of manufacturing the printed wiring board shown in FIG. 7 will be specifically described by way of an example. First, A. Adhesive for electroless plating, B. Interlayer resin insulation,
C. Resin filler, D.I. The composition of the solder resist will be described.

A. Raw material composition for preparation of adhesive for electroless plating (adhesive for upper layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
35% by weight of a resin solution dissolved in DMDG at a concentration of 3.15% and a photosensitive monomer (Toa Gosei Co., Aronix M315) 3.15
Parts by weight, 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65)
3.6 parts by weight of NMP were obtained by stirring and mixing.

[Resin composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Industries,
After mixing 7.2 parts by weight of a polymer pole having an average particle size of 1.0 μm and 3.09 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, followed by stirring and mixing with a bead mill.

[Curing Agent Composition] 2 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
% Of a resin solution dissolved in DMDG at a concentration of 35%, 4 parts by weight of a photosensitive monomer (Alonix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco), N
3.6 parts by weight of MP were obtained by stirring and mixing.

[Resin composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Industries,
After mixing 14.49 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP were further added,
It was obtained by stirring and mixing with a bead mill.

[Curing agent composition] 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), and a photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight with stirring.

C. Raw material composition for resin filler preparation [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), having an average particle diameter of 1.6 μm coated with a silane coupling agent on the surface SiO ₂ spherical particles (Admatech, CRS 11
01-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ± 1
The temperature was adjusted to 45,000-49,000 cps at ℃. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

D. Solder resist composition 60% by weight of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in DMDG was sensitized with 50% of epoxy groups of acrylated oligomer (molecular weight 4000).
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type).
Rotor No.4 for 60rpm, rotor for 6rpm
No.3.

Next, a method of manufacturing the printed wiring board 10 will be described with reference to FIGS. E. FIG. Manufacture of Printed Wiring Board (1) Both sides of a substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm
copper-clad laminate 30 on which copper foil 32 of μm is laminated
A was used as a starting material (see FIG. 1A). First, the copper-clad laminate 30A is drilled, subjected to an electroless plating process, and etched in a pattern to form a substrate 30A.
An inner copper pattern 34 and a through hole 36 were formed on both surfaces of the substrate (FIG. 1B).

(2) The substrate 30 on which the inner layer copper pattern 34 and the through hole 36 are formed is washed with water and dried, and then used as an oxidation bath (blackening bath) as NaOH (10 g / l) and NaClO.
₂ (40 g / l), Na ₃ PO ₄ (6 g / l), and NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath were subjected to oxidation-reduction treatment to form the inner layer copper pattern 34 and the through-hole. A roughened layer 38 was provided on the surface of the hole 36 (see FIG. 1C).

(3) The raw material composition for preparing the resin filler C was mixed and kneaded to obtain a resin filler. (4) By applying the resin filler 40 obtained in the above (3) to both surfaces of the substrate 30 using a roll coater within 24 hours after the preparation, the conductor circuit (inner layer copper pattern) 34 and the conductor circuit 34 During and between the through holes 36, 70
After drying at 20 ° C. for 20 minutes, a resin filler 40 was similarly filled between the conductor circuits 34 or inside the through holes 36 on the other surface, and dried by heating at 70 ° C. for 20 minutes (FIG. 1).
(D)).

(5) The surface of the inner layer copper pattern 34 and the through holes 36 are polished on one side of the substrate 30 after the treatment of the above (4) by belt sanding using # 600 belt abrasive paper (manufactured by Sankyo Rikagaku). Filler 4 on the surface of land 36a
Polishing was performed so that 0 did not remain, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate (see FIG. 2E). Then at 100 ° C for 1 hour,
The resin filler 40 was cured by performing a heat treatment at 120 ° C. for 3 hours, 150 ° C. for 1 hour, and 180 ° C. for 7 hours.

The surface layer of the resin filler 40 filled in the through holes 36 and the like and the inner conductor circuit 3
4 After removing the roughened layer 38 on the upper surface and smoothing both surfaces of the substrate 30, the resin filler 40 and the side surface of the inner conductor circuit 34 are firmly adhered to each other through the roughened layer 38, and the through hole 3 is formed.
A wiring board in which the inner wall surface of No. 6 and the resin filler 40 were firmly adhered via the roughened layer 38 was obtained. That is, by this process,
The surface of the resin filler 40 and the surface of the inner layer copper pattern 34 are flush with each other.

(6) The substrate 30 on which the conductor circuit 34 is formed is alkali-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to form Pd.
After applying a catalyst and activating the catalyst, copper sulfate 3.2
× 10 ^-2 mol / l, nickel sulfate 3.9 × 10 ^-3 mo
1 / l, complexing agent 5.4 × 10 ^-2 mol / l, sodium hypophosphite 3.3 × 10 ^-1 mol / l, boric acid 5.0 ×
10 ^-1 mol / l, 0.1 g / l of surfactant (Surfir 465, manufactured by Nissin Chemical Co., Ltd.), immersion in an electroless plating solution consisting of PH = 9, 1 minute after immersion, 1 By vibrating vertically and horizontally at times, Cu-Ni- is formed on the surface of the land 36a of the conductor circuit 34 and the through hole 36.
A coating layer of a needle-shaped alloy made of P and a roughened layer 42 were provided (see FIG. 2F).

Further, tin borofluoride 0.1 mol /
1, thiourea 1.0 mol / l, temperature 35 ° C., PH =
A Cu—Sn substitution reaction was performed under the conditions of 1.2, and a 0.3 μm-thick Sn layer (not shown) was provided on the surface of the roughened layer.

(7) The raw material composition for preparing the interlayer resin insulating agent of B was stirred and mixed, and the viscosity was adjusted to 1.5 Pa · s to obtain an interlayer resin insulating agent (for lower layer). Next, the raw material composition for preparing the adhesive for electroless plating of A was stirred and mixed, and the viscosity was adjusted to 7 Pa · s to obtain an adhesive solution for electroless plating (for the upper layer).

(8) The interlayer resin insulating material (for lower layer) having a viscosity of 1.5 Pa · s obtained in (7) is applied to both surfaces of the substrate of (6).
4 was coated with a roll coater within 24 hours after preparation, left in a horizontal state for 20 minutes, dried at 60 ° C. for 30 minutes (prebaked), and then the viscosity of 7 Pa · obtained in the above (7) was obtained. s
Of the photosensitive adhesive solution (for upper layer) 46 is applied within 24 hours after preparation, and left in a horizontal state for 20 minutes.
The adhesive layer 50α having a thickness of 35 μm was formed (see FIG. 2G).

(9) The substrate 3 on which the adhesive layer was formed in the above (8)
0, a black circle 5 of 85 μmφ as shown in FIG.
The photomask film 51 on which 1a was printed was brought into close contact with the photomask film 51, and was exposed at 500 mJ / cm ² using an ultrahigh pressure mercury lamp. This is spray-developed with a DMTG solution.
Exposure to 3,000 mJ / cm ² by ultra-high pressure mercury lamp at 100 ° C
Heat treatment (post-baking) at 120 ° C. for 1 hour and then at 150 ° C. for 3 hours to obtain an 85 μm φ opening (opening for forming a via hole) 48 having excellent dimensional accuracy equivalent to a photomask film. A 35 μm-thick interlayer resin insulating layer (two-layer structure) 50 having a thickness of 50 μm was formed (FIG. 3).
(I)). Note that a tin plating layer (not shown) was partially exposed in the opening 48 serving as a via hole.

(10) The substrate 30 in which the openings 48 are formed is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 50, thereby obtaining the interlayer resin insulation layer 50. Was roughened (see FIG. 3 (J)), and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Furthermore, surface roughening treatment (roughening depth 6 μm)
Palladium catalyst (Atotech) on the surface of the substrate
, A catalyst nucleus was attached to the surface of the interlayer resin insulation layer 50 and the inner wall surface of the via hole opening 48.

(11) The substrate was immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film 52 having a thickness of 0.6 μm on the entire rough surface (FIG. 3 (K)). [Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

(12) A commercially available photosensitive dry film is stuck on the electroless copper plating film 52 formed in the above (11), a mask is placed on the film, exposed at 100 mJ / cm ² , and exposed to 0.8% sodium carbonate. After development, a plating resist 54 having a thickness of 15 μm was provided (see FIG. 3 (L)).

(13) Next, electrolytic copper plating was applied to the non-resist-formed portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 4 (M)). [Aqueous electrolytic plating solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (Captoside GL, manufactured by Atotech Japan) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(14) After peeling off the plating resist 54 with 5% KOH, the electroless plating film 52 under the plating resist is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless copper is removed. Plating film 52 and electrolytic copper plating film 5
An 18 μm-thick conductor circuit 58 and via hole 60 made of 6 were formed (FIG. 4 (N)).

(15) The same processing as in (6) is performed, and the conductor circuit 5
A roughened surface 62 made of Cu-Ni-P was formed on the surfaces of the via holes 60 and the via holes 60, and the surfaces thereof were further substituted with Sn (see FIG. 4 (O)). (16) By repeating the above steps (7) to (15), an upper interlayer resin insulation layer 150 is further provided, and the conductor circuit 1
58 and via holes 160 were formed to obtain a multilayer wiring board (see FIG. 4 (P)). However, in the roughened surface 62 formed on the surface of the conductor circuit 158 and the via hole 160,
No Sn substitution was performed.

(17) On both surfaces of the substrate 30 obtained in the above (16),
The above D. Was applied in a thickness of 45 μm (see FIG. 5 (Q)). Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a thickness 5 on which a circular pattern (mask pattern) is drawn is formed.
A photomask film (not shown) of 1 mm was placed in close contact with the substrate, exposed to ultraviolet light of 1000 mJ / cm ² , and subjected to DMTG development processing. And 1 hour at 80 ° C, 1 hour at 100 ° C,
Heat treatment is performed at 20 ° C. for 1 hour and at 150 ° C. for 3 hours to form a solder resist layer (thickness: 20 μm) 70 having an opening (opening diameter: 200 μm) 71 in a solder pad portion (including a via hole and its land portion). It was formed (see FIG. 5 (R)).

(18) Next, nickel chloride 2.31 × 10 ^-1 mol
/ L, sodium hypophosphite 2.8 × 10 ^-1 mol / l, sodium citrate 1.85 × 10 ^-1 mol / l, pH
= 4.5 of the substrate 30 in an electroless nickel plating solution.
By immersing for 5 minutes, a nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71. Further, the substrate was treated with 4.1 × 10 ^-2 mol / l of potassium gold cyanide and 1.87 mol of ammonium chloride.
× 10 ^-1 mol / l, sodium citrate 1.16 × 10 ^-1 mo
1 / l, sodium hypophosphite 1.7 × 10 ^-1 mol / l, immersed in electroless gold plating solution at 80 ° C. for 7 minutes and 20 seconds, and gold plating 0.03 μm thick on nickel plating layer By forming the layer 74, the solder pads 75 were formed in the via holes 160 and the conductor circuits 158 (see FIG. 6 (S)).

(19) Then, solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C., so that the solder bumps (solder bodies) 76U and 76D
To form a printed wiring board 10 (FIG. 6 (T)).
reference).

Such a printed wiring board has a size of -52 to 1
Heat cycle test at 25 ° C, 121 ° C, 2atm
, 100% relative humidity pressure cooker test (press
Also in the urecooker test), there is no peeling of the solder pad and the solder resist layer, and no cracking of the insulating layer occurs. On the other hand, in the printed wiring board shown in FIG. 12C, cracks occurred in the insulating layer at the boundary between the solder pads and the solder resist, and peeling occurred between the solder pads and the solder resist. .

Subsequently, the IC to the printed wiring board 10
The placement of the chip and the attachment to the daughter board 94 will be described with reference to FIG. The IC chip 90 is mounted such that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is mounted by performing reflow. After that, a sealing resin serving as an underfill 88 is filled between the IC chip 90 and the printed wiring board 10.
Similarly, the daughter board 94 is attached to the solder bumps 76D of the printed wiring board 10 by reflow, and a sealing resin to be the underfill 88 is filled.

FIG. 10 shows a printed wiring board according to a second embodiment of the present invention. In the printed wiring board according to the second embodiment, a reinforcing layer 98 is formed on the solder resist layer 70. With such a configuration, the peeling of the solder resist layer 70 is completely prevented, and the solder pads 75 are more firmly pressed against the interlayer resin insulating layer 150, thereby improving the connection reliability.

[Brief description of the drawings]

1 (A), 1 (B), 1 (C), 1
(D) is a manufacturing process diagram of the printed wiring board according to the first example of the present invention.

FIG. 2 (E), FIG. 2 (F), FIG. 2 (G), FIG.
(H) is a manufacturing process diagram of a printed wiring board according to the first example of the present invention.

FIG. 3 (I), FIG. 3 (J), FIG. 3 (K), FIG.
(L) is a manufacturing process diagram of the printed wiring board according to the first example of the present invention.

FIGS. 4 (M), 4 (N), 4 (O), 4
(P) is a manufacturing process diagram of the printed wiring board according to the first example of the present invention.

FIGS. 5 (Q) and 5 (R) are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 6 (S) and 6 (T) are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the printed wiring board according to the first embodiment of the present invention.

FIG. 8 shows a printed wiring board according to a first embodiment of the present invention;
It is sectional drawing which shows the state in which the C chip was mounted.

FIG. 9A is an enlarged view of a portion G in FIG. 7,
FIG. 9B is a view taken in the direction of the arrow H in FIG. 9A.

FIG. 10 is a sectional view of a printed wiring board according to a second embodiment of the present invention.

FIG. 11 is a sectional view of a printed wiring board according to the related art.

12 (A) is an enlarged view of a portion F in FIG. 11, FIG. 12 (B) is a view on arrow B in FIG. 12 (A), and FIG. It is sectional drawing of the printed wiring board of a prior art.

13 (A) and 13 (B) are cross-sectional views of a solder resist opening of a printed wiring board according to the present invention.

[Explanation of symbols]

 Reference Signs List 30 core substrate 50 interlayer resin insulating layer 58 conductive circuit 60 via hole 70 solder resist 71 opening 72 nickel plating layer 74 gold plating layer 75 solder pad 150 interlayer resin insulating layer 158 conductive circuit 160 via hole

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E314 AA24 BB11 BB12 CC01 FF01 GG09 5E319 AA03 AB05 AC13 BB04 CC12 CC33 GG11

Claims (6)

[Claims] 1. A printed wiring board comprising: a solder pad for mounting a semiconductor component on a substrate; and a solder resist layer provided with an opening through which the solder pad is exposed. And a solder resist layer forming the periphery of the opening is formed on the solder pad so as to overlap the peripheral portion of the solder pad with a thickness. 2. The printed wiring board according to claim 1, wherein an opening of the solder resist layer is formed so as to overlap a peripheral portion of the half pad by 3 μm or more. 3. The printed wiring board according to claim 1, wherein a thickness of an overlapping portion of the solder resist layer in a peripheral portion of the solder pad is set to 10 μm or more. 4. The solder resist layer has a thickness of 10 to 10.
The printed wiring board according to claim 1, wherein the thickness is set to 50 µm. 5. An opening in the solder resist layer has a straight line 2
2. A circular shape having a diameter of 50 μm or less.
A printed wiring board according to claim 1. 6. The printed wiring board according to claim 1, wherein the solder resist layer is made of a novolak epoxy resin or a novolak epoxy acrylate, and contains an imidazole curing agent as a curing agent.