JP2008118037A - Surface emitting laser element and method for manufacturing the same, and surface emitting laser array and method for manufacturing the same - Google Patents

Abstract

A surface-emitting laser element and a surface-emitting laser array with uniform light emission in a light-emitting region and a manufacturing method for manufacturing them with high yield are provided.
A method for manufacturing a surface emitting laser device includes preparing a conductive GaN substrate 10 including a high dislocation density high conductivity region 10a, a low dislocation density high conductivity region 10b, and a low dislocation density low conductivity region 10c. A plurality of group III-V compound semiconductor layers 20 including a light emitting layer 200 is formed on one main surface 10m of the substrate, and a semiconductor layer side electrode 15 is formed on the uppermost layer of the compound semiconductor layer, thereby forming a conductive GaN substrate. Including a step of forming a substrate-side electrode on the other main surface 10n of the substrate, forming a carrier diffusion layer 201 between the conductive GaN substrate 10 and the light emitting layer 200, and emitting light in which carriers flow in the light emitting layer 200 The region 200a is formed so as to be restricted above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c.
[Selection] Figure 1

Description

  The present invention relates to a surface-emitting laser element and a method for manufacturing the same, and a surface-emitting laser array and a method for manufacturing the surface-emitting laser element. Regarding the method.

In order to obtain a semiconductor light emitting device with high emission intensity and high reliability, a GaN substrate that is conductive and has a low dislocation density is required as a substrate for a semiconductor light emitting device. For this reason, a conductive GaN substrate for a semiconductor light emitting device intentionally concentrates dislocations in the crystal of the substrate to form a region having a high dislocation density (hereinafter referred to as a high dislocation density region), and this high dislocation density. A low dislocation density region having a low dislocation density is formed in a region other than the region. By forming a plurality of semiconductor layers including a light emitting layer on the low dislocation density region of the conductive GaN substrate thus formed, and forming an LED (light emitting die auto) structure or a stripe laser structure, the emission intensity and reliability can be improved. It has been proposed to manufacture a high semiconductor light emitting element (for example, Patent Document 1 and Patent Document 2).
JP 2003-124115 A JP 2003-124572 A

  However, the semiconductor light emitting device proposed in Patent Document 1 or Patent Document 2 has the following problems. That is, when forming a semiconductor light emitting device having a stripe laser structure using a conductive GaN substrate, the yield when forming a Fabry-Perot resonator, for example, is low because the cleavage of the GaN substrate is insufficient.

  In addition, when a semiconductor light emitting device having an LED structure is formed using a conductive GaN substrate, light emission in the light emitting region may not be uniform even if the light emitting region in the LED structure is arranged above the low dislocation density region. As a result, the yield of the semiconductor light emitting device is reduced. As a result of investigating the cause, within the low dislocation density region of the conductive GaN substrate, there are a high conductivity region (hereinafter referred to as a low dislocation density high conductivity region) and a low region (hereinafter referred to as a low dislocation density low conductivity region). It was found to be due to inclusion. Note that the high dislocation density region of the conductive GaN substrate is a region having a high dislocation density and a high carrier concentration and high conductivity. Therefore, this high dislocation density region is referred to as a high dislocation density high conductivity region.

  An object of the present invention is to solve the above problems and provide a surface-emitting laser element and a surface-emitting laser array that emit light uniformly in a light-emitting region, and a manufacturing method that manufactures them with a high yield.

  The present invention provides a high dislocation density and high conductivity region having a high dislocation density and carrier concentration, a low dislocation density and a high conductivity region having a low dislocation density as compared with a high dislocation density and a high conductivity region, and a high dislocation density and a high conductivity. A step of preparing a conductive GaN multi-region substrate including a low dislocation density and a low conductive region having a low dislocation density and carrier concentration compared to the conductive region; and a light emitting layer on one main surface of the conductive GaN multi-region substrate Forming a plurality of group III-V compound semiconductor layers, forming a semiconductor layer side electrode on the uppermost layer of the group III-V compound semiconductor layer, and on the other main surface of the conductive GaN multi-region substrate; An electrode forming step of forming a substrate side electrode in the semiconductor layer forming step, and in the semiconductor layer forming step, a carrier diffusion layer that makes the in-plane distribution of carriers flowing into the light emitting layer uniform is formed between the conductive GaN multi-region substrate and the light emitting layer. Shape In at least one of the semiconductor formation step and the electrode formation step, the light emitting region into which carriers flow in at least one of the III-V compound semiconductor layer and the semiconductor side electrode in the light emitting layer is a low dislocation density high conductive region. And a method of manufacturing a surface-emitting laser element, characterized in that it is formed so as to be restricted above in a low dislocation density and low conductive region.

  According to the method of manufacturing a surface emitting laser element according to the present invention, a carrier diffusion layer that makes the in-plane distribution of carriers flowing into the light emitting layer uniform is formed between the conductive GaN multi-region substrate and the light emitting layer, In at least one of the III-V compound semiconductor layer and the semiconductor-side electrode, a light emitting region into which carriers flow in the light emitting layer is restricted above the low dislocation density high conductive region and the low dislocation density low conductive region. By forming the surface emitting laser element, the in-plane distribution of carriers flowing into the light emitting region is uniform, and the light emission in the light emitting region is uniform.

  In the method of manufacturing the surface emitting laser element according to the present invention, the semiconductor-side electrode is lowered so that the light emitting region is restricted above the low dislocation density high conductive region and the low dislocation density low conductive region in the electrode forming step. It can be formed at an upper position in the dislocation density high conductivity region and the low dislocation density low conductivity region. In the semiconductor formation step, a carrier confinement region may be formed in the III-V group compound semiconductor layer so that the light emitting region is restricted above the low dislocation density high conductivity region and the low dislocation density low conductivity region. it can. With this manufacturing method, the light-emitting region can be restricted above the low dislocation density high conductivity region and the low dislocation density low conductivity region.

In the method for manufacturing a surface emitting laser device according to the present invention, the high dislocation density and high conductivity region is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and a low dislocation density. dislocation density high conductivity region is a region carrier concentration of more than 1 × 10 ¹⁸ cm ^-3 in less than a dislocation density of 1 × 10 ⁶ cm ^-2, low dislocation density low conductance region dislocation density 1 × 10 ⁶ cm ^- It may be a region of less than ² and a carrier concentration of less than 1 × 10 ¹⁸ cm ⁻³ . According to this manufacturing method, a surface emitting laser element having a low dislocation density in the light emitting region in the light emitting layer, more uniform light emission in the light emitting region, and higher light emission efficiency can be obtained with a high yield.

In the method for manufacturing a surface emitting laser element according to the present invention, the carrier diffusion layer can have a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. According to such a manufacturing method, the in-plane distribution of carriers flowing into the light emitting region can be made more uniform, and a surface emitting laser element with more uniform light emission in the light emitting region can be obtained with a high yield.

The present invention relates to a conductive GaN substrate, a plurality of III-V compound semiconductor layers including a light emitting layer formed on one main surface of the conductive GaN substrate, and an uppermost layer of the III-V compound semiconductor. The surface emitting laser element includes a semiconductor layer side electrode formed on the substrate and a substrate side electrode formed on the other main surface of the conductive GaN substrate. The conductive GaN substrate has a dislocation density of 1 × 10 ⁶ cm carrier concentration of less than ^-2 1 × 10 ¹⁸ cm and a low dislocation density high conductive region is ^-3 or more regions, dislocation density 1 × 10 ⁶ cm carrier concentration of less than ^-2 1 × 10 ¹⁸ a low dislocation density low-conductivity region that is a region less than cm ⁻³ , and the III-V compound semiconductor layer is formed between the conductive GaN substrate and the light-emitting layer, and in-plane distribution of carriers flowing into the light-emitting layer Including a carrier diffusion layer to make the carrier uniform in the light emitting layer The surface emitting laser element is characterized in that the light emitting region into which the indium flows is located above the low dislocation density high conductive region and the low dislocation density low conductive region.

  In the surface emitting laser device according to the present invention, a carrier diffusion layer that makes the in-plane distribution of carriers flowing into the light emitting layer uniform is formed between the conductive GaN substrate and the light emitting layer, and the light emitting region is conductive. Since the GaN substrate is located above the low dislocation density high conductivity region and the low dislocation density low conductivity region, the in-plane distribution of carriers flowing into the light emitting region is uniform, and the light emission within the light emitting region is uniform. .

  In the surface emitting laser device according to the present invention, the semiconductor-side electrode is located above the low dislocation density high conductive region so that the light emitting region is located above the low dislocation density high conductive region and the low dislocation density low conductive region. Can be formed in place. In addition, a carrier confinement region can be formed in the III-V group compound semiconductor layer so that the light emitting region is located above the low dislocation density high conductivity region and the low dislocation density low conductivity region. In such a surface emitting laser element, the light emitting region in which the in-plane distribution of inflowing carriers is uniform is located above the low dislocation density high conductive region and the low dislocation density low conductive region, so that the light emission in the light emitting region is uniform. become.

In the surface emitting laser element according to the present invention, the carrier diffusion layer can have a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. In such a surface emitting laser element, the in-plane distribution of carriers flowing into the light emitting region becomes more uniform, and the light emission in the light emitting region becomes more uniform.

In the surface emitting laser device according to the present invention, the conductive GaN substrate further includes a high dislocation density and high conductivity region which is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more. Can be included. Such a surface emitting laser element has a low dislocation density in the light emitting region in the light emitting layer even if a part of the conductive GaN substrate includes a high dislocation density and a high conductive region, so that the inflow plane of carriers flowing into the light emitting region Since the distribution is maintained uniformly, the light emission in the light emitting region is maintained uniformly and with high efficiency.

  The present invention relates to a method of manufacturing a surface-emitting laser array including a plurality of surface-emitting laser elements, as a conductive GaN substrate, a high dislocation density and high conductivity region having a high dislocation density and a carrier concentration, and a high dislocation density and high conductivity region. Preparing a conductive GaN multi-region substrate including a low dislocation density and high conductivity region having a low dislocation density compared to the low dislocation density and a low conductivity region having a low dislocation density and a carrier concentration compared to the high dislocation density and high conductivity region A semiconductor layer forming step of forming a plurality of group III-V compound semiconductor layers including a light emitting layer on one main surface of the conductive GaN multi-region substrate, and a semiconductor on the uppermost layer of the group III-V compound semiconductor layer Forming a layer-side electrode and forming a substrate-side electrode on the other main surface of the conductive GaN multi-domain substrate, and in the semiconductor layer forming step, the in-plane distribution of carriers flowing into the light emitting layer Average A carrier diffusion layer is formed between the conductive GaN multi-region substrate and the light emitting layer, and in at least one of the semiconductor formation step and the electrode formation step, at least the group III-V compound semiconductor layer and the semiconductor side electrode Either one is formed so that the light emitting region into which carriers flow in the light emitting layer of each surface emitting laser element included in the laser array is restricted above the low dislocation density high conductive region and the low dislocation density low conductive region. A method of manufacturing a surface-emitting laser array, comprising:

  According to the method of manufacturing the surface emitting laser array according to the present invention, the carrier diffusion layer that makes the in-plane distribution of the carriers flowing into the light emitting layer uniform is formed between the conductive GaN multi-region substrate and the light emitting layer, At least one of the III-V compound semiconductor layer and the semiconductor-side electrode has a light emitting region in which carriers flow in the light emitting layer of each surface emitting laser element in the low dislocation density high conductive region and the low dislocation density low conductive region. By forming it so as to be restricted upward, a surface emitting laser array element in which the in-plane distribution of carriers flowing into the light emitting region is uniform and the light emission in the light emitting region is uniform can be obtained with good yield. It is done.

  In the method of manufacturing the surface emitting laser array according to the present invention, in the electrode forming step, the semiconductor-side electrode is lowered so that the light emitting region is restricted above the low dislocation density high conductive region and the low dislocation density low conductive region. It can be formed in the dislocation density high conductivity region and at a position above the low dislocation density low conductivity region. In the semiconductor layer formation step, a carrier confinement region is formed in the III-V compound semiconductor layer so that the light emitting region is restricted above the low dislocation density high conductivity region and the low dislocation density low conductivity region. Can do. With this manufacturing method, the light emitting region of each surface emitting laser element in the surface emitting laser array can be restricted above the low dislocation density high conductivity region and the low dislocation density low conductivity region.

In the method for manufacturing a surface emitting laser array according to the present invention, the high dislocation density and high conductivity region is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more. The high conductive region is a region having a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density of the low conductive region is a dislocation density of less than 1 × 10 ⁶ cm ^−2. And the carrier concentration may be a region of less than 1 × 10 ¹⁸ cm ⁻³ . According to such a manufacturing method, for each surface emitting laser element, a surface emitting laser array having a low dislocation density in the light emitting region in the light emitting layer, more uniform light emission in the light emitting region, and higher light emission efficiency can be obtained with high yield. .

In the method for manufacturing the surface emitting laser array according to the present invention, the carrier diffusion layer can have a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. According to this manufacturing method, for each surface emitting laser element, the in-plane distribution of carriers flowing into the light emitting region can be made more uniform, and the surface emitting laser array with more uniform light emission in the light emitting region can be obtained. Well obtained.

  The present invention is a surface emitting laser array including a plurality of surface emitting laser elements, the surface emitting laser element comprising a conductive GaN substrate and a light emitting layer formed on one main surface of the conductive GaN substrate. A plurality of group III-V compound semiconductor layers, a semiconductor layer side electrode formed on the uppermost layer of the group III-V compound semiconductor layer, and a substrate formed on the other main surface of the conductive GaN substrate The group III-V compound semiconductor layer includes a carrier diffusion layer that is formed between the conductive GaN substrate and the light emitting layer and uniforms the in-plane distribution of carriers flowing into the light emitting layer. Laser arrays consist of high dislocation density and high conductivity regions with high dislocation density and carrier concentration, low dislocation density and high conductivity regions with low dislocation density compared to high dislocation density and high conductivity regions, and dislocation compared with high dislocation density and high conductivity regions. Density and carry Low dislocation density low dislocation density A conductive GaN multi-region substrate including a low conductive region, and a light emitting region into which carriers flow in a light emitting layer of each surface emitting laser element included in the surface emitting laser array has a low dislocation density. A surface emitting laser array characterized by being located above a high conductive region and a low dislocation density low conductive region.

  In the surface emitting laser array according to the present invention, a carrier diffusion layer that makes the in-plane distribution of carriers flowing into the light emitting layer uniform is formed between the conductive GaN substrate and the light emitting layer, and each surface emitting laser is provided. Since the light emitting region of the element is located above the low dislocation density high conductive region and the low dislocation density low conductive region of the conductive GaN substrate, for each surface emitting laser element, the surface of the carrier flowing into the light emitting region The internal distribution becomes uniform, and the light emission in the light emitting region becomes uniform.

  In the surface emitting laser array according to the present invention, the semiconductor-side electrode has a low dislocation density, a high conductivity region, and a low dislocation density so that the light emitting region is located above the low dislocation density, high conductivity region and the low dislocation density, low conductivity region. It can be formed at an upper position in the low conductive region. In addition, a carrier confinement region can be formed in the III-V group compound semiconductor layer so that the light emitting region is located above the low dislocation density high conductivity region and the low dislocation density low conductivity region. In such a surface emitting laser array, the light emitting region where the in-plane distribution of inflowing carriers in each surface emitting laser element is uniform is located above the low dislocation density high conductive region and the low dislocation density low conductive region. The light emission in the light emitting region becomes uniform.

In the surface emitting laser array according to the present invention, the high dislocation density and high conductivity region is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more. Is a region where the dislocation density is less than 1 × 10 ⁶ cm ⁻² and the carrier concentration is 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density and low conductivity region has a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration. ^{Can be} a region of less than 1 × 10 ¹⁸ cm ⁻³ . In such a surface emitting laser array, the dislocation density of the light emitting region in the light emitting layer is low for each surface emitting laser element, the light emission in the light emitting region becomes more uniform, and the light emission efficiency becomes higher.

In the surface emitting laser array according to the present invention, the carrier diffusion layer can have a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. In such a surface emitting laser array, for each surface emitting laser element, the in-plane distribution of carriers flowing into the light emitting region becomes more uniform, and the light emission in the light emitting region becomes more uniform.

  According to the present invention, it is possible to provide a surface emitting laser element and a surface emitting laser array in which light emission in the light emitting region is uniform, and a manufacturing method for manufacturing them with a high yield.

  The best mode for carrying out the present invention will be described with reference to the drawings. Here, FIGS. 1 (b), 2 (b), 6 (b), 7 (b), 8 (b), 10-15, and 17 (17) showing schematic cross-sectional views of the surface emitting laser element or the surface emitting laser array. In b) and 18 (b), the thicknesses of the conductive GaN substrate and the III-V compound semiconductor layer do not reflect the actual thickness. In order to clarify the layer structure of the group III-V compound semiconductor layer, the thickness of the group III-V compound semiconductor layer is greatly expanded.

(Embodiment 1)
With reference to FIGS. 1 and 2, the manufacturing method of the surface emitting laser device according to the present invention is a conductive GaN substrate 10 having a high dislocation density and high conductivity region 10a having a high dislocation density and carrier concentration, and a high dislocation density. A conductive GaN composite comprising a low dislocation density high conductive region 10b having a low dislocation density compared to the conductive region 10a and a low dislocation density low conductive region 10c having a low dislocation density and carrier concentration compared to the high dislocation density high conductive region 10a. A step of preparing a region substrate, and a step of forming a semiconductor layer that forms a plurality of group III-V compound semiconductor layers 20 including a light emitting layer on one main surface 10m of a conductive GaN multi-region substrate (conductive GaN substrate 10) The semiconductor layer side electrode 15 is formed on the uppermost layer of the III-V compound semiconductor layer 20, and the substrate is formed on the other main surface 10n of the conductive GaN multi-region substrate (conductive GaN substrate 10). An electrode formation step for forming the electrode 11, and in the semiconductor layer formation step, the carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform is formed as a conductive GaN multi-region substrate (conductive GaN substrate 10. ) And the light emitting layer 200, and in at least one of the semiconductor forming step and the electrode forming step, at least one of the group III-V compound semiconductor layer 20 and the semiconductor side electrode 15 is formed in the light emitting layer 200. Thus, the light emitting region 200a into which carriers flow is formed so as to be restricted above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c.

  In the method of manufacturing the surface emitting laser element according to the present embodiment, the carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform is used as the conductive GaN multi-region substrate (conductive GaN substrate 10) and the light emitting layer. 200, and at least one of the group III-V compound semiconductor layer 20 and the semiconductor-side electrode 15 has a light emitting region 200a into which carriers flow in the light emitting layer 200, a low dislocation density high conductive region 10b, and a low conductive region 10b. The surface emitting laser element 1 in which the in-plane distribution of the carriers flowing into the light emitting region 200a is uniform and the light emission in the light emitting region 200a is uniform by forming so as to be restricted above the dislocation density low conductive region 10c. Can be obtained with good yield.

  Here, in any one of the III-V group compound semiconductor layer 20 and the semiconductor-side electrode 15, the light emitting region 200 a in which carriers flow in the light emitting layer 200 is in the low dislocation density high conductive region 10 b and the low dislocation density low conductive region 10 c. The method of forming is not particularly limited so as to be limited above, for example, as shown in FIG. 1, the semiconductor-side electrode 15 is placed in the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. There are a method of forming the carrier confinement region 250 in the III-V compound semiconductor layer 20 as shown in FIG. Details will be described later. In addition, the resonator structure for oscillating the light emission from the light emission area | region 200a from the main surface of an element can use the various structures mentioned later. In FIG. 1 and FIG. 2, such a resonator structure is not shown.

  In the method for manufacturing the surface-emitting laser device of Embodiment 1, as a conductive GaN substrate 10 with reference to FIGS. 3 to 5, a high dislocation density / high conductivity region 10 a having a high dislocation density and carrier concentration, and a high dislocation density / high density. A conductive GaN multi-region substrate including a low dislocation density high conductive region 10b having a low dislocation density compared to the conductive region and a low dislocation density low conductive region 10c having a low dislocation density and carrier concentration compared to the high dislocation density high conductive region The step of preparing is included. Here, the dislocation density in each region is obtained by directly counting the dark spots or etch pits in the fluorescent image per unit area by the CL (cathode luminescence) method or the EPD (etch pit density) method. The carrier concentration in each region can be measured by a CV (capacitance-voltage measurement) method or a Hall measurement method. The carrier is a generic term for holes or electrons that contribute to conduction, and the carrier concentration means the concentration of holes or electrons that contribute to conduction. Such a conductive GaN multi-region substrate concentrates dislocations in the high dislocation density and high conductivity region 10a, so that regions other than the high dislocation density and high conductivity region 10a (low dislocation density and high conductivity region 10b and low dislocation density and low conductivity region 10c). ) Dislocation density is reduced. Therefore, a III-V compound semiconductor layer having a low dislocation density can be formed on the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c, and a surface emitting laser element having high emission intensity and high reliability can be obtained. can get.

  For example, the lifetime of an FP type (general edge emitting type) laser element in which the light emitting region 200a of the light emitting layer 200 is formed above the high dislocation density high conductive region 10a of the conductive GaN multi-region substrate is 100. The light emitting region of the light emitting layer 200 is located above the region other than the high dislocation density high conductive region 10a (low dislocation density high conductive region 10b and low dislocation density low conductive region 10c). The lifetime of the FP type laser element in which 200a is formed becomes very long as 50000 hours or more.

  The method for manufacturing the conductive GaN multi-region substrate used in the present embodiment is not particularly limited. For example, when GaN is crystal-grown on the base substrate, a seed is formed at a place where a high dislocation density high conductivity region is formed. It can be formed in advance. A more specific method for manufacturing such a conductive GaN multi-region substrate is as follows.

  First, a base substrate is prepared. The base substrate is not particularly limited as long as it can grow GaN crystals, and examples thereof include a sapphire substrate and a GaAs substrate. In view of removing the base substrate in a later step, it is preferable to use a GaAs substrate that can be easily removed.

Next, seeds made of, for example, a SiO ₂ film are formed on the base substrate. This type of shape can be, for example, a dot or stripe. A plurality of such species can be regularly formed. More specifically, the seeds are formed in the form of dots or stripes in an arrangement corresponding to the arrangement of the high dislocation density high conductive regions 10a in FIG. 3 (a), FIG. 4 (a) or FIG. 5 (a).

  Next, GaN is crystal-grown on the base substrate on which the above seeds are formed, for example, by HVPE (hydride vapor phase epitaxy). A facet plane corresponding to the pattern shape of the seed is formed on the crystal growth surface of GaN during and after crystal growth. When the seed is a dot-like pattern, pits composed of facet surfaces are regularly formed, and when the seed is a stripe-like pattern, a prism-like facet surface is formed. Here, in crystal growth, conductivity is imparted to GaN by adding a dopant in addition to the GaN raw material.

  Next, the crystal-grown GaN is cut into a predetermined shape and the surface thereof is polished so that the conductive material including the high dislocation density high conductive region 10a, the low dislocation density high conductive region 10b, and the low dislocation density low conductive region 10c is obtained. A conductive GaN multi-region substrate (conductive GaN substrate 10) is obtained.

  Referring to FIGS. 3 to 5, such a conductive GaN multi-region substrate (conductive GaN substrate 10) is formed with a high dislocation density high conductive region 10 a corresponding to the arrangement of seeds of the base substrate. A low dislocation density high conductivity region 10b is formed within a certain range from the dislocation density high conductivity region 10a. Here, referring to FIG. 3A or 4A, when the dot-like high dislocation density high conductive region 10a is formed, the donut-like low dislocation density high conductive region 10b is formed. Has been. Referring to FIG. 5A, when stripe-shaped high dislocation density high conductive region 10a is formed, stripe-shaped low dislocation density high conductive region 10b is formed. Further, a low dislocation density / low conductivity region 10c is formed between the low dislocation density / high conductivity region 10b and the adjacent low dislocation density / high conductivity region 10b. Here, the high dislocation density high conductive region 10a, the low dislocation density high conductive region 10b, and the low dislocation density low conductive region 10c can be observed using a fluorescence microscope.

As described above, the dislocation density is 1 × 10 ⁶ cm ⁻² or more and the carrier concentration is 1 × 10 ¹⁸ cm ⁻³ or more of the high dislocation density and highly conductive region 10a, and the dislocation density is less than 1 × 10 ⁶ cm ^−2. And a low dislocation density high conductive region 10b having a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and a low dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of less than 1 × 10 ¹⁸ cm ^−3. A conductive GaN multi-region substrate including the conductive region 10c is obtained.

  Here, the resistivity of each region in the conductive GaN multi-region substrate is such that the resistivity of the high dislocation density high conductive region 10a and the low dislocation density high conductive region 10b is 0.002 Ω · cm or more and 0.1 Ω · The resistivity of the low dislocation density low conductive region 10c was 0.5 Ω · cm or more and 100,000 Ω · cm or less. In addition, a discontinuous change in resistivity was observed at the boundary between the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10b. Referring to FIG. 19, the spreading resistance values of the low dislocation density high conductivity region 10b and the low dislocation density low conductivity region 10c in the conductive GaN multi-region substrate are measured with an SSRM (scanning spreading resistance microscope). As a result, it was confirmed that they differed by more than one digit.

  In the method for manufacturing the surface-emitting laser device according to the first embodiment, referring to FIGS. 1 and 2, a plurality of III-V group compound semiconductors are formed on the conductive GaN multi-region substrate (conductive GaN substrate 10). A semiconductor layer forming step for forming the layer 20 is included. Here, the group III-V compound semiconductor layer refers to a semiconductor layer formed of a compound of a group IIIb element and a nitrogen that is a group Vb element in the long-period ratio table. In this semiconductor layer forming step, a carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform is formed between the conductive GaN multi-region substrate (conductive GaN substrate 10) and the light emitting layer 200. . By forming the carrier diffusion layer 201, the in-plane distribution of carriers flowing into the light emitting layer 200 can be made uniform.

  In the first embodiment, the stacked structure of the III-V compound semiconductor layer 20 is not particularly limited as long as it is a structure suitable for the object of the present invention. For example, referring to FIG. 1 and FIG. Formed. On the conductive GaN substrate 10, a carrier diffusion layer 201, at least one first conductivity type III-V group compound semiconductor layer 210, a light emitting layer 200, at least one second conductivity type III-V group. The compound semiconductor layer 220 is formed. Here, the first conductivity type and the second conductivity type refer to different conductivity types, n-type and p-type, or p-type and n-type, respectively. Further, the laminated structure of the III-V compound semiconductor 20 includes a resonator structure for causing light emitted from the light emitting region 200a to oscillate from the main surface of the element, as will be described later (illustrated in FIGS. 1 and 2). It has not been).

  In the method for manufacturing the surface-emitting laser device according to the first embodiment, referring to FIGS. 1 and 2, the semiconductor layer side electrode 15 is formed on the uppermost layer of the III-V group compound semiconductor layer 20, and conductive GaN is formed. An electrode forming step of forming the substrate side electrode 11 on the other main surface 10n of the multi-region substrate (conductive GaN substrate 10). By forming such an electrode, a surface emitting laser element can be obtained. Here, referring to FIG. 1A and FIG. 2A, a pad electrode 17 is formed in electrical connection with the semiconductor-side electrode 15. The pad electrode 17 is for electrically connecting a bonding wire.

  In the method for manufacturing the surface-emitting laser element of Embodiment 1, in at least one of the semiconductor layer forming step and the electrode forming step, at least one of the III-V group compound semiconductor layer 20 and the semiconductor-side electrode 15 is used. The light emitting region 200a into which carriers flow in the light emitting layer 200 is formed so as to be restricted above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. Even if the light emitting region 200a is limited above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c, the carrier diffusion layer 201 formed between the conductive GaN substrate 10 and the light emitting layer 200 may be used. The in-plane distribution of carriers flowing into the light emitting region 200a becomes uniform, and the surface emitting laser element 1 with uniform light emission in the light emitting region 200a can be obtained with a high yield. Although there is no restriction | limiting in particular in the formation method of this III-V group compound semiconductor layer 20 and / or the semiconductor side electrode 15, For example, the following methods are used preferably.

(Embodiment 1-1)
Referring to FIG. 1, in the electrode forming step in the method for manufacturing the surface emitting laser element of Embodiment 1, the light emitting region 200a is limited to the upper side in the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. As described above, the semiconductor-side electrode 15 can be formed at an upper position in the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. According to Embodiment 1-1, the substrate-side electrode 11 is formed to extend not only below the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c but also below the high dislocation density high conductive region 10a. Even if the semiconductor-side electrode 15 is formed at a position above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c, the light emitting region 200a into which carriers flow in the light emitting layer 200 is reduced. The high density conductive region 10b and the low dislocation density low conductive region 10c can be restricted upward.

  Referring to FIGS. 1A and 1B, in the surface emitting laser element of Embodiment 1-1, when the semiconductor-side electrode is opaque, the light emission in the light emitting region 200a (diameter D) is the above-described semiconductor. It is taken out only from the main surface of the vicinity of the outer periphery of the side electrode 15 (referred to as the outer region from the outer periphery to about 5 μm, hereinafter the same). Further, by providing one or more openings (not shown) in the semiconductor-side electrode 15, light emission in the light emitting region 200a can be taken out from the openings. Furthermore, by using the semiconductor-side electrode 15 as a transparent electrode, the light emission in the light-emitting region 200a can be extracted from the entire region of the semiconductor-side electrode 15 to the outside. As apparent from FIG. 1B, the light-emitting region 200a of the light-emitting layer 200 substantially coincides with the formation region of the semiconductor-side electrode 15, but in FIG. .

(Embodiment 1-2)
Referring to FIG. 2, in the semiconductor formation step in the method for manufacturing the surface emitting laser element according to the first embodiment, the light emitting region 200 a is restricted above the low dislocation density high conductive region 10 b and the low dislocation density low conductive region 10 c. As described above, the carrier confinement region 250 can be formed in the III-V compound semiconductor layer 20. According to Embodiment 1-2, the semiconductor-side electrode 15 and the substrate-side electrode 11 are not only above or below the low dislocation density and high conductivity region 10b and low dislocation density and low conductivity region 10c, respectively, but also high dislocation density and high conductivity. Even if the region 10a extends to the upper side or the lower side, the carrier confinement region 250 is formed in the III-V group compound semiconductor layer 20, thereby reducing the light emitting region 200a into which carriers flow in the light emitting layer 200. The dislocation density can be restricted above the high conductive region 10b and the low dislocation density low conductive region 10c. Thereby, a surface emitting laser element in which carriers flowing into the light emitting region 200a are uniform and light emission in the light emitting region 200a is uniform can be obtained.

  Here, the method for forming the carrier confinement region 250 is not particularly limited as long as the object of the invention is met. For example, when the region is divided in a mesa shape by mesa etching, the method enters the side surface of the mesa. Due to the etching damage, some of the carriers that have flowed in are recombined. From the viewpoint of preventing such carrier recombination, a method of forming a carrier confinement layer 250a made of an insulator as shown in FIG. 6B and insulation by ion implantation as shown in FIG. A method of forming the insulating region 250b is preferable.

  2A and 2B, in the embodiment 1-2, a ring-shaped electrode having an opening at the center is formed as the semiconductor-side electrode 15. Since the light emitting region 200a is limited within the opening region of the ring-shaped semiconductor side electrode 15 by the carrier confinement region 250, the light emission of the light emitting region 200a is extracted outside from the inside of the opening region of the ring-shaped semiconductor side electrode 15. It is.

  As a method for limiting the light emitting region 200a into which carriers flow in the light emitting layer 200 to the upper side in the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c, in Embodiment 1-A1, the semiconductor side electrode 15 is low dislocation Embodiment 1-A2 shows a method of forming the carrier confinement region 250 in the III-V compound semiconductor layer 20 as a method for forming the high density conductive region 10b and the low dislocation density in the low conductivity region 10c. However, the carrier confinement region 250 is formed in the III-V group compound semiconductor layer 20, and the semiconductor-side electrode 15 is formed at an upper position in the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. It is also preferred to use the method.

  In the first embodiment, the light emitting region 200a is formed above the low dislocation density high conductive region 10b and the low dislocation density conductive region 10c having a low dislocation density due to the carrier confinement region 250 formed in the group III-V compound semiconductor layer 20. Therefore, a surface emitting laser element with low dislocation density in the light emitting region 200a in the light emitting layer 200 and high emission intensity and reliability can be obtained. However, since the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c have a difference in carrier concentration, the light emitting region 200a is located above the low dislocation density conductive region 10b and the low dislocation density low conductive region 10c. In this case, the carriers flowing into the light emitting region 200a are not uniform, and the light emission in the light emitting region is not uniform. Here, by forming the carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform between the conductive GaN substrate 10 and the light emitting layer 200, the light emitting region 200 a in the light emitting layer 200 is formed. The in-plane distribution of the inflowing carriers can be made uniform, and the surface emitting laser element 1 in which the light emission region 200a emits light uniformly can be obtained with high yield.

  Further, in the surface emitting laser element obtained by the manufacturing method of Embodiment 1, there is no particular limitation on the resonator structure of the III-V group compound semiconductor layer 20 that enables surface emission. For example, FIG. ) And n-type layer side DBR 213 as shown in FIG. 7B, and a DBR 213 on the n-type layer side as shown in FIG. A combination structure with the DBR 223 on the p-type layer side, a structure including the photonic crystal layer 233 as shown in FIG.

In the method for manufacturing the surface emitting laser device of this embodiment, the high dislocation density and high conductivity region is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and has a low dislocation density. The high conductive region is a region having a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density of the low conductive region is a dislocation density of less than 1 × 10 ⁶ cm ^−2. And a carrier concentration of less than 1 × 10 ¹⁸ cm ⁻³ is preferred. By limiting the light emitting region 200a in the light emitting layer 200 above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c with low dislocation density, the dislocation density of the light emitting region in the light emitting layer is low, and light emission A surface emitting laser element having more uniform light emission in the region and higher light emission efficiency can be obtained with a high yield.

In the method for manufacturing the surface emitting laser element of this embodiment, the carrier diffusion layer 201 preferably has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. By forming a carrier diffusion layer having a high conductivity of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more between the conductive GaN substrate 10 and the light emitting layer 200, the carrier concentration flows into the light emitting region 200a. The in-plane distribution of carriers to be generated can be made more uniform, and a surface emitting laser element with more uniform emission in the light emitting region can be obtained with good yield.

(Embodiment 2)
1 and 2, the surface emitting laser element according to the present invention includes a conductive GaN substrate 10 and a plurality of light emitting layers 200 formed on one main surface 10m of the conductive GaN substrate 10. The III-V group compound semiconductor layer 20, the semiconductor layer side electrode 15 formed on the uppermost layer of the group III-V compound semiconductor 20, and the other main surface 10 n of the conductive GaN substrate 10 are formed. The conductive GaN substrate 10 has a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more. A low dislocation density high conductivity region 10b and a low dislocation density low conductivity region 10c, which is a region having a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of less than 1 × 10 ¹⁸ cm ⁻³ , III− Group V compound semiconductor layer 20 is made of conductive G A light-emitting region 200a that is formed between the aN substrate 10 and the light-emitting layer 200 and uniforms the in-plane distribution of carriers flowing into the light-emitting layer 200, and into which carriers flow in the light-emitting layer 200 has low dislocations. It is characterized by being located above the high density conductive region 10b and the low dislocation density low conductive region 10c.

  In the surface-emitting laser element according to the second embodiment, a carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light-emitting layer 200 uniform is formed between the conductive GaN substrate 10 and the light-emitting layer 200, and light is emitted. Since the light emitting region 200a into which carriers flow in the layer 200 is located above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c, the in-plane distribution of carriers flowing into the light emitting region is uniform. As a result, the light emission in the light emitting region becomes uniform, and the efficiency is high and the reliability is improved.

  In the surface emitting laser element of Embodiment 2, the carrier diffusion layer 201 is formed between the conductive GaN substrate 10 and the light emitting layer 200, the light emitting region 200a has a low dislocation density, a high conductive region 10b, and a low dislocation density. Although there will be no restriction | limiting in particular if it has the structure located in the upper part in the electroconductive area | region 10c, For example, what has the structure of the following Embodiment 2-1 or Embodiment 2-2 is mentioned.

(Embodiment 2-1)
An example of the surface emitting laser element of Embodiment 2 is as follows with reference to FIG. 1 (a) and (b). That is, a plurality of III-V compound semiconductor layers 20 including a conductive GaN substrate 10, a light emitting layer 200 formed on one main surface 10 m of the conductive GaN substrate 10, and a III-V compound semiconductor layer The surface emitting laser element 1 includes a semiconductor layer side electrode 15 formed on the uppermost layer 20 and a substrate side electrode 11 formed on the other main surface 10 n of the conductive GaN substrate 10. Here, the conductive GaN substrate 10 has a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, a low dislocation density high conductivity region 10b, and a dislocation density of 1 ×. And a low dislocation density low conductive region 10c which is a region of less than 10 ⁶ cm ⁻² and a carrier concentration of less than 1 × 10 ¹⁸ cm ⁻³ . The III-V compound semiconductor layer 20 includes a carrier diffusion layer 201 that is formed between the conductive GaN substrate 10 and the light emitting layer 200 and makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform. Further, the semiconductor-side electrode 15 has a low dislocation density and high conductivity region so that the light emission region 200a into which carriers flow in the light emitting layer 200 is located above the low dislocation density and high conductivity region 10b and the low dislocation density and low conductivity region 10c. 10b and a low dislocation density in the low conductive region 10c.

(Embodiment 2-2)
Other examples of the surface emitting laser element of Embodiment 2 are as follows with reference to FIGS. 2 (a) and 2 (b). That is, a plurality of III-V compound semiconductor layers 20 including a conductive GaN substrate 10, a light emitting layer 200 formed on one main surface 10 m of the conductive GaN substrate 10, and a III-V compound semiconductor layer The surface emitting laser element 1 includes a semiconductor layer side electrode 15 formed on the uppermost layer 20 and a substrate side electrode 11 formed on the other main surface 10 n of the conductive GaN substrate 10. Here, the conductive GaN substrate 10 has a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, a low dislocation density high conductivity region 10b, and a dislocation density of 1 ×. And a low dislocation density low conductive region 10c which is a region of less than 10 ⁶ cm ⁻² and a carrier concentration of less than 1 × 10 ¹⁸ cm ⁻³ . The III-V compound semiconductor layer 20 includes a carrier diffusion layer 201 that is formed between the conductive GaN substrate 10 and the light emitting layer 200 and makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform. Further, in the III-V group compound semiconductor layer 20, the light emitting region 200a into which carriers flow in the light emitting layer 200 is positioned above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. A constriction layer 250 is formed.

  In the surface-emitting laser element of the second embodiment, the resonator structure of the III-V group compound semiconductor layer 20 that enables surface emission is not described in FIGS. 1 and 2, but for example, FIG. A combination structure of a DBR (multilayer distributed Bragg reflector; the same applies hereinafter) 213 and a dielectric mirror 103 as shown in FIG. 7 and a DBR 213 and a p at the n-type layer side as shown in FIG. A combination structure with the DBR 223 on the mold layer side, a structure including the photonic crystal layer 233 as shown in FIG.

In the surface emitting laser element of Embodiment 2, the carrier diffusion layer 201 preferably has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. In this surface emitting laser element, a carrier diffusion layer 201 having a high conductivity of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more is formed between the conductive GaN substrate 10 and the light emitting layer 200. Therefore, the in-plane distribution of the carriers flowing into the light emitting region 200a becomes more uniform, and the light emission in the light emitting region becomes more uniform.

In the surface emitting laser element of the embodiment, the conductive GaN substrate 10 further includes a high dislocation density and high conductivity region which is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more. 10a. In such a surface emitting laser element, even if a part of the conductive GaN substrate 10 includes the high dislocation density high conductive region 10a, the light emitting region 200a in the light emitting layer 200 includes the low dislocation density high conductive region 10b and the low dislocation density. Since it is located above the low-density conductive region 10c, its dislocation density is low and the in-plane distribution of carriers flowing into the light-emitting region is maintained uniformly, so that light emission in the light-emitting region is maintained uniformly and highly efficiently. Is done.

(Embodiment 3)
A specific example of the surface emitting laser element according to the present invention will be described. Referring to FIG. 6, the surface emitting laser element 1 of Embodiment 3 includes a plurality of IIIs including a conductive GaN substrate 10 and a light emitting layer 200 formed on one main surface 10 m of the conductive GaN substrate 10. -V group compound semiconductor layer 20. 6A and 6B, a pad electrode 17 for electrically connecting a bonding wire on the uppermost layer (contact layer 229) of the group III-V compound semiconductor layer 20, A p-type ring-shaped semiconductor side electrode 15 formed so as to be electrically connected to the pad electrode 17 and a dielectric mirror 103 disposed on the inner peripheral side of the ring-shaped semiconductor side electrode 15 are provided. .

  Referring to FIG. 6B, the specific structure of the surface emitting laser element 1 in the cross section is that one main surface 10m (a plurality of III-V group compound semiconductor layers of the n-type conductive GaN substrate 10 is formed). The carrier diffusion layer 201 is formed on the main surface on the side where it is formed (the same applies hereinafter). As a material constituting the carrier diffusion layer 201, for example, n-type GaN (GaN having n-type conductivity type) can be used.

On the carrier diffusion layer 201, an n-type layer-side DBR 213 is formed. The DBR 213 is composed of a multilayer film in which a plurality of layers made of n-type AlGaN and n-type GaN are stacked. An n-type cladding layer 215 is formed on the DBR 213. As a material constituting the cladding layer 215, for example, n-type AlGaN can be used. A light emitting layer 200 is formed on the cladding layer 215. The light emitting layer 200 may be, for example, a multiple quantum well light emitting layer having a multilayer structure in which a Ga _1-x In _x N layer (0 <x <1) and a GaN layer are stacked. A p-type cladding layer 225 is formed on the light emitting layer 200. As a material constituting the clad layer 225, for example, p-type Al _1-x Ga _x N (0 <x <1) can be used. A p-type contact layer 227 is formed on the clad layer 225. As a material constituting the contact layer 227, for example, GaN can be used.

On this contact layer 227, a carrier confinement layer 250a made of an insulator is formed. As a material constituting the carrier confinement layer 250a, for example, an insulating film made of SiO ₂ can be used. The carrier confinement layer 250a is located above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c of the n-type conductive GaN substrate 10 and below the dielectric mirror 103 described later. An opening having a circular planar shape is formed in the region to be processed. This opening becomes a so-called light emitting region 200a. That is, the light emitting region 200a is above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c, and is a region where the dielectric mirror 103 is formed (dielectric mirror formation region 103a). It is formed so as to be located below the inside. The diameter of the opening is a width D (see FIG. 6). A p-type contact layer 229 is formed on the carrier confinement layer 250a. As a material constituting the contact layer 229, for example, GaN can be used. On the contact layer 229, the ring-shaped semiconductor side electrode 15 and the dielectric mirror 103 described above are formed. The dielectric mirror 103 may be a multilayer film made of, for example, ZnS and MgF ₂ . In addition, it is preferable that the thickness T (refer FIG.6 (b)) of DBR213 is 3 micrometers or more and 6 micrometers or less.

  For example, when a DBR 213 having a thickness of 3 μm or more is formed on a sapphire substrate, a large strain is generated due to a difference in lattice constant between the sapphire substrate and the DBR 213. As a result, cracks occur and the characteristics deteriorate. However, when the DBR 213 is formed on the conductive GaN substrate 10, the lattice matching between the conductive GaN substrate 10 and the DBR 213 is remarkably increased, so that the strain is reduced. As a result, generation of cracks can be suppressed. Thus, if the conductive GaN substrate 10 is used, the DBR 213 having a large thickness as described above can be formed. With such a thick DBR 213, a high reflectance can be realized with respect to light having a wavelength emitted as laser light. As a result, laser light can be emitted from the dielectric mirror 103 side.

  The other main surface 10n of the n-type conductive GaN substrate (conductive GaN substrate having an n-type conductivity type) 10 (refers to the main surface on which the plurality of group III-V compound semiconductor layers are not formed). The substrate side electrode 11 (n-side electrode) is formed on the same.

  In the surface emitting laser element according to the third embodiment, the carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform is formed between the conductive GaN substrate 10 and the light emitting layer 200. Even if the light emitting region 200a included in the light emitting layer 200 is located above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c in the conductive GaN substrate 10, the carriers flowing into the light emitting region 200a. The in-plane distribution becomes uniform, and the light emission in the light emitting region 200a becomes uniform.

In the surface emitting laser element of Embodiment 3, the carrier diffusion layer 201 preferably has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. A carrier diffusion layer 201 having a high conductivity of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more is formed between the conductive GaN substrate 10 and the light emitting layer 200, so that the inside of the light emitting region 200 a The in-plane distribution of the carriers flowing into the light becomes more uniform, and the light emission in the light emitting region becomes more uniform.

Further, the low dislocation density and high conductive region 10b is a region having a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density and low conductive region 10c has a dislocation density of 1 × 10 ^6. When the region is less than cm ⁻² and the carrier concentration is less than 1 × 10 ¹⁸ cm ⁻³ , dislocations in the light emitting region in the light emitting layer are lowered, and the light emission efficiency is further increased.

(Embodiment 4)
Another specific example of the surface emitting laser element according to the present invention will be described. Referring to FIG. 7, the surface emitting laser element 1 of the fourth embodiment basically has the same planar structure as the surface emitting laser element of the third embodiment shown in FIG. The difference is that the dielectric mirror 103 as shown in FIG. 6 is not disposed on the inner peripheral side of the semiconductor-side electrode 15. Referring to FIG. 7B, the cross-sectional structure of the carrier diffusion layer 201, the DBR 213 on the n-type layer side, the n-type cladding is formed on one main surface 10m of the n-type conductive GaN substrate 10. The layer 215 and the light emitting layer 200 are disposed, and the substrate-side electrode 11 (n-side electrode) is formed on the other main surface 10 n of the n-type conductive GaN substrate 10. In the surface emitting laser element shown in FIG. 7B, the structure below the light emitting layer 200 is the same as that of the surface emitting laser element of the third embodiment shown in FIG. 6B. However, the surface emitting laser element shown in FIG. 7B is different from the surface emitting laser element of the third embodiment shown in FIG.

As shown in FIG. 7B, specifically, the surface emitting laser element 1 of the present embodiment has a p-type cladding layer 225 formed on the light emitting layer 200. A DBR 223 on the p-type layer side is formed on the cladding layer 215. The DBR 223 has a multilayer structure in which a plurality of types of nitride epitaxial layers are alternately stacked. For example, as the DBR 223, a multilayer film in which Al _1-x Ga _x N (0 <x <1) and GaN are alternately stacked, or Al _1-x Ga _x N (0 <x <1) and Ga _{1-y is used.} A multilayer film structure in which In _y N (0 <y <1) is alternately stacked can be used. Then, a p-type contact layer 229 is formed on the DBR 223. On the contact layer 229, the ring-shaped semiconductor-side electrode 15 described above is formed. Then, an insulating region 250 b that is insulated by implanting ions is formed in the DBR 223 and the cladding layer 225. The clad layer 225 is a portion located just below the inner circumference side of the ring-shaped semiconductor-side electrode 15, and has a low dislocation density and high conductivity region 10 b and a low dislocation density and low conductivity of the n-type conductive GaN substrate 10. A region having a circular planar shape in which the insulating region 250b is not formed is formed above the region 10c. This region becomes the light emitting region 200a. The width D (diameter) of this region can be set to 5 μm, for example. The thickness T of the DBRs 213 and 223 can be set to 3 μm or more and 6 μm or less, for example.

  In such a structure, the DBRs 213 and 223 made of a nitride semiconductor layer can be formed on the conductive GaN substrate 10 with a relatively thick film thickness (a film thickness of 3 μm or more and 6 μm or less). Can be sufficiently reflected between the two DBRs 213 and 223. As a result, a sufficient amount of laser light can be oscillated.

  Further, in the surface emitting laser element of Embodiment 4, the carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer uniform is formed between the conductive GaN substrate 10 and the light emitting layer 200. Even if the light emitting region 200a in the light emitting layer 200 is located above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c in the conductive GaN substrate 10, the carriers flowing into the light emitting region 200a The in-plane distribution is uniform, and the light emission in the light emitting region 200a is uniform.

In the surface emitting laser element of Embodiment 4, the carrier diffusion layer 201 preferably has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. A carrier diffusion layer 201 having a high conductivity at a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more is formed between the conductive GaN substrate 10 and the light emitting layer 200, so that the light emitting region 200 a The in-plane distribution of the carriers flowing in becomes more uniform, and the light emission in the light emitting region becomes more uniform.

Further, the low dislocation density and high conductive region 10b is a region having a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density and low conductive region 10c has a dislocation density of 1 × 10 ^6. When the region is less than cm ⁻² and the carrier concentration is less than 1 × 10 ¹⁸ cm ⁻³ , dislocations in the light emitting region in the light emitting layer are lowered, and the light emission efficiency is further increased.

(Embodiment 5)
Still another specific example of the surface emitting laser element according to the present invention will be described. With respect to the planar structure of the surface emitting laser element 1 of Embodiment 5, as shown in FIG. 8A, the semiconductor-side electrode 15 is formed on the uppermost layer (contact layer 229) of the III-V compound semiconductor layer 20. And a pad electrode 17 electrically connected thereto. As for the cross-sectional structure, as shown in FIG. 8B, a carrier diffusion layer is formed as a III-V group compound semiconductor layer 20 on one main surface 10m of the n-type conductive GaN substrate 10. 201, an n-type cladding layer 215, a light emitting layer 200, a p-type cladding layer 225, a photonic crystal layer 233, a p-type cladding layer 226, and a contact layer 229 are formed. A semiconductor side electrode 15 is formed on the contact layer 229. A substrate-side electrode 11 (n-side electrode) is formed on the other main surface 10 n of the n-type conductive GaN substrate 10.

  In the surface emitting laser element of Embodiment 5 shown in FIG. 8B, the DBR 213 and the dielectric mirror 103 of the surface emitting laser element of Embodiment 3 shown in FIG. 6B, or FIG. 7B. There is no complicated resonator structure like the pair of DBRs 213 and 223 of the surface emitting laser element of the fourth embodiment shown in FIG. 2, and the two-dimensional diffraction grating formed between the two p-type cladding layers 225 and 226 is used. The photonic crystal layer 233 enables surface light emission.

  Further, in the surface emitting laser element of Embodiment 5 shown in FIG. 8B, the low dislocation density of the conductive GaN substrate 10 on the contact layer 229 which is the uppermost layer of the III-V group compound layer 20. A semiconductor-side electrode 15 is formed above the high conductive region 10b and the low dislocation density low conductive region 10c. Since the semiconductor-side electrode 15 is formed in this way, the light emitting region 200a is located above the low dislocation density high conductive region 10b. The width D (diameter) of the light emitting region 200a can be, for example, about 50 μm to 200 μm.

  With reference to FIGS. 8A and 8B, the surface-emitting laser element of Embodiment 5 includes a carrier diffusion layer 201, an n-type cladding layer 215, on one main surface 10 m of the conductive GaN substrate 10. The light emitting layer 200, the p-type cladding layer 225, the photonic crystal layer 233, the p-type cladding layer 226, and the contact layer 229 are stacked in this order. A semiconductor side electrode 15 is provided on the contact layer 229. A substrate-side electrode 11 (n-side electrode) is provided on the other main surface 10 n of the conductive GaN substrate 10. The semiconductor side electrode 15 and the substrate side electrode 11 are made of, for example, Au (gold).

The light emitting layer 200 is composed of a multiple quantum well made of, for example, Al _x Ga _{1 -xy} In _y N (0 ≦ x, y ≦ 1, 0 ≦ x + y ≦ 1). Moreover, you may consist of a single semiconductor material. The light emitting layer 200 can be formed as a plurality of quantum wires provided along the photonic crystal layer 233 and extending in a predetermined direction, and can be formed as a plurality of quantum boxes provided along the photonic crystal layer 233. Can be done. Each quantum wire has a dimension (for example, about several tens of nanometers) that makes the energy level of electrons discrete in two directions orthogonal to the longitudinal direction. Each quantum box has dimensions (for example, about several tens of nanometers) such that the energy levels of electrons are discrete in three directions orthogonal to each other. With such a quantum structure, the density of states increases, so that the light emission efficiency is increased and the emission spectrum is sharpened.

  Here, the photonic crystal layer 233 will be described with reference to FIG. The photonic crystal layer 233 includes a crystal layer 233a and a plurality of diffraction grating holes 233b having a lower refractive index than the crystal layer 233a. The crystal layer 233a is made of GaN, and the holes formed in the crystal layer 233a are diffraction grating holes 233b. That is, the diffraction grating hole 233b is made of air.

In the photonic crystal layer 233, a plurality of diffraction grating holes 233b are provided on one surface of the crystal layer 233a so as to form a triangular lattice or a square lattice. Each diffraction grating hole 223b is provided as a columnar (for example, columnar) space. The distance P _P between the center of each diffraction grating hole 233b and the center of the diffraction grating hole 233b adjacent thereto is an equal value, for example, 0.16 μm. The diameter D _P of the diffraction grating hole 233b is, for example, 0.06 μm.

In the photonic crystal layer 233, the crystal layer 233a has a first refractive index (2.54 in the case of GaN), and the periodically formed diffraction grating hole 233b has a second refractive index (in the case of air 1). Have A material different from that of the crystal layer 233a can be embedded in the diffraction grating hole 233b. However, in order to increase the difference between the first refractive index and the second refractive index, the diffraction grating hole 233b is preferably in a state where nothing is buried (a state where gas, for example, air exists). When the difference in refractive index is thus increased, light can be confined in the medium having the first refractive index. A silicon nitride film (SiN _x ) or the like can be used as a material for filling the diffraction grating hole 233b, that is, a low refractive index dielectric material.

The photonic crystal layer 233 is a diffraction grating having an equal period (a value corresponding to a lattice constant) with respect to a first direction and a second direction that forms a predetermined angle with this direction. Various selections are possible for the photonic crystal layer 233 with respect to the above-described two directions and the period of those directions. Further, by setting the dislocation density of the conductive GaN substrate 10 and the crystal layer 233a existing in at least the light emitting region 200a to 1 × 10 ⁶ cm ⁻² or less, the crystal layer 223a existing in the light emitting region 200a has a diffraction grating hole. In the etching process for forming 233b, an assembly of defects due to dislocations does not occur.

  Here, the surface emission of the surface emitting laser element according to the fifth embodiment will be described. Referring to FIG. 8B, when a positive voltage is applied to the semiconductor-side electrode 15, holes are injected from the p-type cladding layers 225 and 226 into the light-emitting layer 200, and the n-type cladding layer 215 to the light-emitting layer 200. Electrons are injected into. When holes and electrons (holes and electrons are collectively referred to as carriers) are injected into the light-emitting layer 200, carrier recombination occurs and light is generated. The wavelength of the generated light is defined by the band gap of the semiconductor layer included in the light emitting layer 200.

  Light generated in the light emitting layer 200 is confined in the light emitting layer 200 by the n-type cladding layer 215 and the p-type cladding layer 225, but part of the light reaches the photonic crystal layer 233 as evanescent light. When the wavelength of the evanescent light reaching the photonic crystal layer 233 matches the predetermined period of the photonic crystal layer 233, the light repeats diffraction at the wavelength corresponding to the period, and a standing wave is generated. And phase conditions are defined. The light whose phase is defined by the photonic crystal layer 233 is fed back to the light in the light emitting layer 200 to generate a standing wave. This standing wave satisfies the light wavelength and phase conditions defined in the photonic crystal layer 233.

  Such a phenomenon can occur in the light emitting region 233a because the light emitting layer 200 and the photonic crystal layer 233 are two-dimensionally spread. When a sufficient amount of light is accumulated in this state, light having a uniform wavelength and phase condition is in the direction perpendicular to the main surface 233m of the photonic crystal layer 233 (upward direction in FIG. 9) in the III-V group. Stimulated emission is performed from the main surface of the uppermost layer of the compound semiconductor layer 20.

  Further, in the surface emitting laser element of Embodiment 5, the carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer uniform is formed between the conductive GaN substrate 10 and the light emitting layer 200. Even if the light emitting region 200a in the light emitting layer 200 is located above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c in the conductive GaN substrate 10, the carriers flowing into the light emitting region 200a The in-plane distribution is uniform, and the light emission in the light emitting region 200a is uniform.

In the surface emitting laser element of Embodiment 5, the carrier diffusion layer 201 preferably has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. A carrier diffusion layer 201 having a high conductivity of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more is formed between the conductive GaN substrate 10 and the light emitting layer 200, so that the inside of the light emitting region 200 a The in-plane distribution of the carriers flowing into the light becomes more uniform, and the light emission in the light emitting region becomes more uniform.

Further, the low dislocation density and high conductive region 10b is a region having a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density and low conductive region 10c has a dislocation density of 1 × 10 ^6. When the region is less than cm ⁻² and the carrier concentration is less than 1 × 10 ¹⁸ cm ⁻³ , dislocations in the light emitting region in the light emitting layer are lowered, and the light emission efficiency is further increased.

  The dimensions of the respective parts of the semiconductor laser device 1 of the fifth embodiment are enumerated below by way of example. The thickness of the conductive GaN substrate 10 is, for example, 100 μm, and the thickness of the photonic crystal layer 223 is, for example, 0. The thickness of each of the n-type cladding layer 215 and the p-type cladding layer 226 is, for example, 0.5 μm, and each of the light-emitting layer 200 and the p-type cladding layer 225 is, for example, 0.1 μm. .

  In the third to fifth embodiments, as illustrated in FIGS. 6, 7, and 8, the element having one light emitting region 200 a for one surface emitting laser element 1 is illustrated. However, the light emitting region is not limited to one for one surface emitting laser element. For example, an element having a plurality of light emitting regions 200a for one surface emitting laser element 1 as shown in FIG. 16 is preferable from the viewpoint of increasing the emission intensity per element.

(Embodiment 6)
A method of manufacturing a surface emitting laser array according to the present invention is a method of manufacturing a surface emitting laser array 2 including a plurality of surface emitting laser elements 1 with reference to FIGS. High dislocation density and high conductivity region 10a having high dislocation density and carrier concentration, low dislocation density and high conductivity region 10b having low dislocation density compared to high dislocation density and high conductivity region 10a, and high dislocation density and high conductivity region 10a A step of preparing a conductive GaN multi-region substrate including a low dislocation density low-conductivity region 10c having a low dislocation density and a carrier concentration; and a plurality of light-emitting layers 200 on one main surface 10m of the conductive GaN multi-region substrate. A semiconductor layer forming step for forming the group III-V compound semiconductor layer 20, and a semiconductor layer side electrode 15 is formed on the uppermost layer of the group III-V compound semiconductor layer 20, thereby forming a conductive GaN composite. An electrode forming step of forming the substrate-side electrode 11 on the other main surface 10n of the area substrate, and in the semiconductor layer forming step, a carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform Formed between the conductive GaN multi-region substrate (conductive GaN substrate 10) and the light emitting layer 200, and at least one of the semiconductor formation step and the electrode formation step, the III-V group compound semiconductor layer 20 and the semiconductor side The light emitting region 200a into which carriers flow in the light emitting layer 200 of each surface emitting laser element 1 included in the surface emitting laser array 2 includes at least one of the electrodes 15 as a low dislocation density high conductive region 10b and a low dislocation density low conductivity. It is characterized by being formed so as to be restricted to the upper side in the region 10c.

  In the method of manufacturing the surface emitting laser array according to the sixth embodiment, the carrier diffusion layer 201 that makes the in-plane distribution of the carriers flowing into the light emitting layer 200 uniform is used as the conductive GaN multi-region substrate (conductive GaN substrate 10) and the light emitting layer. And at least one of the group III-V compound semiconductor layer 20 and the semiconductor-side electrode 15 in the light emitting layer 200 of each surface emitting laser element 1 included in the surface emitting laser array 2. Is formed so as to be restricted above the low dislocation density high conductivity region 10b and the low dislocation density low conductivity region 10c, so that the light emission region 200a of each surface light emitting element laser 1 can be uniformly formed. Since the carriers flow into the surface emitting laser array 2, the surface emitting laser array 2 with uniform light emission in the light emitting region 200 a is obtained.

  In the method for manufacturing a surface emitting laser array according to the sixth embodiment, at least one of the group III-V compound semiconductor layer 20 and the semiconductor side electrode 15 is used as the light emitting layer of each surface emitting laser element 1 included in the surface emitting laser array 2. There is no particular limitation on the method of forming the light emitting region 200a into which carriers flow in 200 so as to be restricted above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. The method is preferably used.

(Embodiment 6-1)
Referring to FIG. 17, in the electrode formation step in the method of manufacturing the surface emitting laser array according to the sixth embodiment, the light emitting region 200 a is limited to the upper side in the low dislocation density high conductive region 10 b and the low dislocation density low conductive region 10 c. As described above, the semiconductor-side electrode 15 can be formed at an upper position in the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. According to the embodiment 6-1, the substrate-side electrode 11 is formed not only below the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c but also below the high dislocation density high conductive region 10a. Even if the semiconductor side electrode 15 is formed at a position above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c, carriers are generated in the light emitting layer 200 of each surface emitting laser element 1. The inflowing light emitting region 200a can be restricted above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c.

  Referring to FIGS. 17A and 17B, in the surface emitting laser element of Embodiment 6-1, when the semiconductor-side electrode 15 is opaque, the light emission in the light emitting region 200a (diameter D) is as described above. The semiconductor-side electrode 15 is extracted outside only from the main surface in the vicinity of the outer periphery of the semiconductor-side electrode 15 (referred to as an outer region from the outer periphery to about 5 μm, hereinafter the same). Further, by providing one or more openings (not shown) in the semiconductor-side electrode 15, light emission in the light emitting region 200a can be taken out from the openings. Furthermore, by using the semiconductor-side electrode 15 as a transparent electrode, the light emission in the light-emitting region 200a can be extracted from the entire region of the semiconductor-side electrode 15 to the outside. As apparent from FIG. 17B, the light-emitting region 200a of the light-emitting layer 200 substantially coincides with the formation region of the semiconductor-side electrode 15, but in FIG. .

Embodiment 6-2
Referring to FIG. 18, in the semiconductor formation step in the method of manufacturing the surface emitting laser array according to the sixth embodiment, the light emitting region 200 a is limited to the upper side in the low dislocation density high conductive region 10 b and the low dislocation density low conductive region 10 c. As described above, the carrier confinement region 250 can be formed in the III-V compound semiconductor layer 20. According to Embodiment 6-2, the semiconductor-side electrode 15 and the substrate-side electrode 11 are not only above or below the low dislocation density and high conductivity region 10b and low dislocation density and low conductivity region 10c, respectively, but also high dislocation density and high conductivity. Even if it is formed to extend to the upper side or the lower side of the region 10a, the carrier confinement region 250 is formed in the group III-V compound semiconductor layer 20 to thereby generate carriers in the light emitting layer 200 of each surface emitting laser element 1. The light-emitting region 200a into which the light flows can be restricted above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c.

  Here, the method for forming the carrier confinement region 250 is not particularly limited as long as the object of the invention is met. For example, when the region is divided in a mesa shape by mesa etching, the method enters the side surface of the mesa. Due to the etching damage, some of the carriers that have flowed in are recombined. From the viewpoint of preventing such carrier recombination, a method of forming a carrier confinement layer 250a made of an insulator as shown in FIG. 6B and insulation by ion implantation as shown in FIG. A method of forming the insulating region 250b is preferable.

  18A and 18B, in the embodiment 6-2, the semiconductor-side electrode 15 of each surface-emitting laser element 1 has a low dislocation density and high conductivity region 10b in the conductive GaN substrate 10. A ring-shaped semiconductor-side electrode 15 having an opening in which an opening region is located is formed above. Since the light-emitting region 200a is limited within the opening region of the ring-shaped semiconductor-side electrode 15 by the carrier confinement region 250, the light-emitting region 200a of each surface-emitting laser element 1 emits light on the ring-shaped semiconductor side. The electrode 15 is taken out from the opening region.

  As a method for limiting the light emitting region 200a into which carriers flow in the light emitting layer 200 of each surface emitting laser element above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c, Embodiment 6-1 The method for forming the semiconductor side electrode 15 at an upper position in the low dislocation density high conductive region 10b, and the method for forming the carrier confinement region 250 in the group III-V compound semiconductor layer 20 are described in the embodiment 6-2. Is a method of forming the carrier confinement region 250 in the III-V compound semiconductor layer 20 and forming the semiconductor side electrode 15 at an upper position in the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. It is also preferable to use.

  Further, in each surface emitting laser element obtained by the method of manufacturing the surface emitting laser array of Embodiment 6, there is no particular limitation on the laminated structure of the III-V group compound semiconductor layer 20 that enables surface emission, For example, an n-type layer-side DBR (multilayer distributed Bragg reflector; the same applies hereinafter) 213 and a dielectric mirror 103 as shown in FIG. 6B, and an n-type layer as shown in FIG. Preferred examples include a combined structure of the DBR 213 on the mold layer side and the DBR 223 on the p-type layer side, a structure including the photonic crystal layer 233 as shown in FIG.

In the method for manufacturing the surface emitting laser array of Embodiment 6, the high dislocation density and high conductivity region is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and has a low dislocation density. The high conductive region is a region having a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density of the low conductive region is a dislocation density of less than 1 × 10 ⁶ cm ^−2. And a carrier concentration of less than 1 × 10 ¹⁸ cm ⁻³ is preferred.
According to this manufacturing method, for each surface emitting laser element 1, a surface emitting laser array in which the dislocation density of the light emitting region 200a in the light emitting layer 200 is low, light emission in the light emitting region 200a is more uniform, and light emission efficiency is higher. Good yield.

In the method for manufacturing the surface emitting laser array of Embodiment 6, the carrier diffusion layer 201 preferably has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. According to this manufacturing method, for each surface emitting laser element 1, the in-plane distribution of carriers flowing into the light emitting region 200a can be made more uniform, and the surface emitting laser in which light emission in the light emitting region 200a is more uniform. Arrays can be obtained with good yield.

(Embodiment 7)
The surface-emitting laser array according to the present invention is a surface-emitting laser array 2 including a plurality of surface-emitting laser elements 1 with reference to FIGS. 17 and 18, and the surface-emitting laser element 1 includes a conductive GaN substrate 10. And a plurality of group III-V compound semiconductor layers 20 including the light emitting layer 200 formed on one main surface 10 m of the conductive GaN substrate 10, and the uppermost layer of the group III-V compound semiconductor layer 20. A semiconductor layer side electrode 15 and a substrate side electrode 11 formed on the other main surface 10 n of the conductive GaN substrate 10, and the III-V group compound semiconductor layer 20 includes the conductive GaN substrate 10. The surface emitting laser array 2 includes a carrier diffusion layer 201 that is formed between the light emitting layer 200 and makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform. Low dislocation density high conductive region 10b having a low dislocation density compared to high dislocation density high conductive region 10a, and low dislocation density and low carrier concentration compared to high dislocation density high conductive region 10a Including a conductive GaN multi-region substrate (conductive GaN substrate 10) including a low-dislocation density conductive region 10c, and carriers flow in the light emitting layer 200 of each surface emitting laser element 1 included in the surface emitting laser array 2. The light emitting region 200a is located above the low dislocation density high conductive region 10b.

  In the surface emitting laser array 2 of the seventh embodiment, a carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform is formed between the conductive GaN substrate 10 and the light emitting layer 200, The light emitting region 200a into which carriers flow in the light emitting layer 200 of each surface emitting laser element 1 is located above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. In the laser element 1, the in-plane distribution of carriers flowing into the light emitting region 200a becomes uniform, and the light emission in the light emitting region 200a becomes uniform.

  In the surface emitting laser array 2 of the seventh embodiment, the carrier diffusion layer 201 is formed between the conductive GaN substrate 10 and the light emitting layer 200, and the light emitting region 200a of each surface emitting laser element 1 has a low dislocation density. The structure is not particularly limited as long as it has a structure located above the high conductive region 10b and the low dislocation density low conductive region 10c. For example, it has the structure of Embodiment 7-1 or Embodiment 7-2 below. Things.

(Embodiment 7-1)
An example of the surface emitting laser array of Embodiment 7 is as follows with reference to FIGS. 17 (a) and 17 (b). That is, the surface emitting laser array 2 includes a plurality of surface emitting laser elements 1. Here, the surface emitting laser element 1 includes a conductive GaN substrate 10 and a plurality of III-V group compound semiconductor layers 20 including a light emitting layer 200 formed on one main surface 10 m of the conductive GaN substrate 10. The semiconductor layer side electrode 15 formed on the uppermost layer of the III-V group compound semiconductor layer 20 and the substrate side electrode 11 formed on the other main surface 10n of the conductive GaN substrate 10 are included. The III-V compound semiconductor layer 20 includes a carrier diffusion layer 201 that is formed between the conductive GaN substrate 10 and the light emitting layer 200 and makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform. Further, the surface emitting laser array 2 includes a high dislocation density and high conductivity region 10a having a high dislocation density and a carrier concentration, a low dislocation density and high conductivity region 10b having a low dislocation density compared to the high dislocation density and high conductivity region 10a, and a high dislocation. A conductive GaN multi-region substrate (conductive GaN substrate 10) including a low dislocation density and low conductive region 10c having a low dislocation density and carrier concentration compared to the high density conductive region 10a is included. The light emitting region 200a into which carriers flow in the light emitting layer 200 of each surface emitting laser element 1 included in the surface emitting laser array 2 is located above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. Is located.

(Embodiment 7-2)
Another example of the surface emitting laser array of the seventh embodiment is as follows with reference to FIGS. 18 (a) and 18 (b). That is, the surface emitting laser array 2 includes a plurality of surface emitting laser elements 1. Here, the surface emitting laser element 1 includes a conductive GaN substrate 10 and a plurality of III-V group compound semiconductor layers 20 including a light emitting layer 200 formed on one main surface 10 m of the conductive GaN substrate 10. The semiconductor layer side electrode 15 formed on the uppermost layer of the III-V group compound semiconductor layer 20 and the substrate side electrode 11 formed on the other main surface 10n of the conductive GaN substrate 10 are included. The III-V compound semiconductor layer 20 includes a carrier diffusion layer 201 that is formed between the conductive GaN substrate 10 and the light emitting layer 200 and makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform. Further, the surface emitting laser array 2 includes a high dislocation density and carrier concentration, a high dislocation density and high conductivity region 10a, a low dislocation density and a high conductivity region 10b having a low dislocation density compared to the high dislocation density and high conductivity region 10a, and a high dislocation. A conductive GaN multi-region substrate (conductive GaN substrate 10) including a low dislocation density and low conductive region 10c having a low dislocation density and carrier concentration compared to the high density conductive region 10a is included. The light emitting region 200a into which carriers flow in the light emitting layer 200 of each surface emitting laser element 1 included in the surface emitting laser array 2 is located above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. Is located.

  In the surface emitting laser array of the seventh embodiment, the stacked structure of the III-V group compound semiconductor layer 20 that enables the surface emitting of each surface emitting laser element is shown in FIGS. 17 (b) and 18 (b). Although not described in FIG. 7, for example, a combination structure of an n-type layer side DBR (multilayer distributed Bragg reflector; the same applies hereinafter) 203 and a dielectric mirror 103 as shown in FIG. A combination structure of the DBR 213 on the n-type layer side and the DBR 223 on the p-type layer side as shown in FIG. 8B, a structure including the photonic crystal layer 233 as shown in FIG.

In the conductive GaN multi-region substrate (conductive GaN substrate 10) of the surface emitting laser array of the seventh embodiment, the high dislocation density high conductive region 10a has a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10. The region of ¹⁸ cm ⁻³ or higher and the low dislocation density / high conductivity region 10b have a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and a low dislocation density / low conductivity region. 10c can be a region having a dislocation density of less than 1 × 10 ⁶ cm ⁻² and a carrier concentration of less than 1 × 10 ¹⁸ cm ⁻³ . In the surface emitting laser array 2, the carrier diffusion layer 201 is formed between the conductive GaN substrate 10 and the light emitting layer 200, the dislocation density is less than 1 × 10 ⁶ cm ⁻² , and the carrier concentration is 1 × 10. ^Since the light emitting region 200a of each surface emitting laser element 1 is located above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c which are regions of ¹⁸ cm ⁻³ or more, The in-plane distribution of the carriers flowing into the light is uniform, the light emission in the light emitting region 200a is uniform, and the light emission efficiency is increased.

In the surface emitting laser array 2 of the seventh embodiment, the carrier diffusion layer 201 can have a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. In the surface emitting laser array 2, for each surface emitting laser element 1, the in-plane distribution of carriers flowing into the light emitting region 200 a becomes more uniform, and light emission in the light emitting region becomes more uniform.

  With reference to FIGS. 17 and 18, the surface-emitting laser array 2 of Embodiment 7 emits light on, for example, a single stacked body of a single conductive GaN substrate 10 and a group III-V compound semiconductor layer 20. A plurality of unit elements of the laser element 1 are arranged (a plurality of unit elements are formed using one laminated body). FIG. 17 shows an arrangement in which the surface emitting laser elements shown in FIG. 1 are arranged in two rows as unit elements. In FIG. 18, the surface emitting laser elements shown in FIG. 2 as unit elements are arranged in two rows. Bonding wires 70 made of gold are connected and fixed to the pad electrodes 17 in the unit elements. A sufficient laser beam output can be obtained by such a surface emitting laser array.

(Example 1)
Specific examples of the surface emitting laser element according to Embodiment 3 will be described below. First, on a GaAs substrate (underlying substrate) on which dot-like seeds made of SiO ₂ film are formed at intervals of 400 μm, facet growth is performed using Si as a dopant by the HVPE method, thereby forming a conductive GaN substrate 10. A high dislocation density and high conductivity region 10a having a dislocation density of 5 × 10 ⁶ cm ⁻² and a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ , a dislocation density of 1 × 10 ⁵ cm ⁻² and a carrier concentration of 3 × 10 N-type conductivity including a low dislocation density and high conductivity region 10b of ¹⁸ cm ^{−3 and} a low dislocation density and low conductivity region 10c of a dislocation density of 2 × 10 ⁴ cm ⁻² and a carrier concentration of 3 × 10 ¹⁵ cm ^−3. GaN multi-region substrate was fabricated. Here, the dislocation density in each region was measured by the EPD method, and the carrier concentration in each region was measured by the CV method and the Hall measurement method.

  Next, referring to FIG. 6B, a plurality of III-V group compound semiconductors including a light emitting layer 200 on one main surface 10m of an n-type conductive GaN multi-region substrate (conductive GaN substrate 10). The layer 20 is formed, the ring-shaped semiconductor layer side electrode 15 is formed on the uppermost layer of the III-V compound semiconductor layer, and the other of the n-type conductive GaN multi-region substrate (conductive GaN substrate 10) is formed. Substrate side electrode 11 was formed on main surface 10n.

  Here, the plurality of group III-V compound semiconductor layers 20 were formed by MOCVD (metal organic chemical vapor deposition). Specifically, a plurality of III-V group compound layers 20 were formed as follows.

First, an n-type GaN layer having a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ and a thickness of 5 μm was formed as a carrier diffusion layer 201 on an n-type conductive GaN multi-region substrate (conductive GaN substrate 10). . On this carrier diffusion layer 201, the DBR 213 on the n-type layer side was formed. As this DBR 213, an Al _0.3 Ga _0.7 N / GaN multilayer structure (a laminated structure in which Al _0.3 Ga _0.7 N layers and GaN layers are alternately laminated) was adopted. Here, the total thickness per pair (one pair) of the Al _0.3 Ga _0.7 N layer and the GaN layer was approximately 86 nm, and a multilayer structure of 60 pairs was formed. The average carrier concentration of this DBR 213 was 5 × 10 ¹⁶ cm ⁻³ . An n-type cladding layer 215 was formed on the DBR 213. A Ga _0.9 In _0.1 N / GaN multiple quantum well structure was formed on the cladding layer 215 as the light emitting layer 200. Specifically, a multilayer structure in which Ga _0.9 In _0.1 N layers and GaN layers were alternately stacked was formed. A p-type cladding layer 225 was formed on the light emitting layer 200. Here, the n-type cladding layer 215 is an n-type Al _0.15 Ga _0.85 N cladding layer, and the p-type cladding layer 225 is a p-type Al _0.15 Ga _0.85 N cladding layer.

Next, a p-type contact layer 227 was formed on the p-type cladding layer 225. Here, the p-type contact layer 227 is a p ⁺ -type GaN contact layer. On this p-type contact layer 227, a current confinement layer 250a made of a SiO ₂ insulator was formed. Here, the light emitting region (region in which the planar shape formed by the current confinement layer 250a is defined by the circular opening) designated by the current confinement layer 250a is a low dislocation density high conductivity region of the conductive GaN substrate 10. The current confinement layer 250a is formed so as to be located above the low conductivity region 10c and the low dislocation density low conductivity region 10c. Further, the diameter D of the light emitting region 200a was 5 μm. The area ratio of the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c located below the light emitting region 200a was 2: 1. A p-type contact layer 229 having the same chemical composition as the p-type contact layer 227 was formed on the current confinement layer 250a.

Next, a ring-shaped semiconductor-side electrode 15 (p-side electrode) and a dielectric mirror 103 are formed on the p-type contact layer 229, and the substrate-side electrode 11 (n (Side electrode) was formed to obtain the surface emitting laser element of this example. Here, as the dielectric mirror 103, a ZnS / MgF ₂ multilayer film (12 pairs) having a reflectivity of 99% with respect to light having a wavelength near 420 nm was employed. Here, the dielectric mirror 103 is formed so that the formation region 103a of the dielectric mirror 103 includes the entire region of the light emitting region 200a. The ring-shaped semiconductor-side electrode 15 disposed so as to surround the dielectric mirror 103 is for injecting a current into the light emitting region described above.

When a current was injected into the obtained surface emitting laser element, laser oscillation was observed at a current density of ⁴ kA / cm ² or more, and the light emission was uniform.

(Comparative Example 1)
A surface-emitting laser device was fabricated in the same manner as in Example 1 except that the n-type layer-side DBR 213 was directly formed on one main surface of the conductive GaN substrate 10 without forming the carrier diffusion layer 201. Obtained. When a current was injected into the obtained surface emitting laser element, laser oscillation was observed at a current density of 8 kA / cm ² or more, and the light emission was not uniform.

(Example 2)
Specific examples of the surface emitting laser element according to Embodiment 4 will be described below. First, a conductive GaN multi-region substrate (conductive GaN substrate 10) having the same characteristics as in Example 1 was produced. Next, referring to FIG. 7B, a plurality of group III-V compound semiconductors including a light emitting layer 200 on one main surface 10m of an n-type conductive GaN multi-region substrate (conductive GaN substrate 10). The layer 20 is formed, the ring-shaped semiconductor layer side electrode 15 is formed on the uppermost layer of the III-V compound semiconductor layer, and the other of the n-type conductive GaN multi-region substrate (conductive GaN substrate 10) is formed. The substrate-side electrode 11 was formed on the main surface 10n so that the light emitting region 200a of the light emitting layer 200 was positioned above the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c.

  Here, the plurality of group III-V compound semiconductor layers 20 were formed by MOCVD (metal organic chemical vapor deposition). Specifically, a plurality of III-V group compound layers 20 were formed as follows.

Similarly to Example 1, a carrier diffusion layer 201 (n-type GaN layer) and DBR 213 (60 pairs of Al _0.3 on the n-type layer side) are formed on an n-type conductive GaN multi-region substrate (conductive GaN substrate 10). Ga _0.7 N / GaN multilayer structure, where the total thickness per pair of Al _0.3 Ga _0.7 N layer and GaN layer was about 80 nm, and the average carrier concentration was 5 × 10 ¹⁶ cm ⁻³ . ), N-type cladding layer 215 (n-type Al _0.15 Ga _0.85 N cladding layer), light-emitting layer 200 (Ga _0.9 In _0.1 N / GaN multiple quantum well structure) and p-type cladding layer 225 (p-type Al _0.15 Ga) _0.85 N clad layer) was sequentially formed.

Next, the DBR 223 on the p-type layer side was formed on the p-type cladding layer 225. Here, the DBR 223 employs 60 pairs of Al _0.3 Ga _0.7 N / GaN multilayer structure (laminated structure in which Al _0.3 Ga _0.7 N layers and GaN layers are alternately stacked), that is, the same structure as the DBR 213. The total thickness per pair of the Al _0.3 Ga _0.7 N layer and the GaN layer was about 80 nm. The average carrier concentration of this DBR 223 was 3 × 10 ¹⁶ cm ⁻³ . On this DBR 223, a p ⁺ -type GaN contact layer was formed as a p-type contact layer 229.

  Next, an insulating region 250b was formed in part of the p-type grad layer 225 and the DBR 223 by selective partial insulation by mesa etching and ion implantation. A light emitting region (region in which the planar shape formed by the insulating region 250b is defined by the circular opening) 200a specified by the insulating region 250b is a low dislocation density high conductive region included in the conductive GaN substrate 10. The insulating region 250b was formed so as to be located above the low conductivity region 10c and the low dislocation density low conductive region 10c. Further, the diameter D of the light emitting region 200a was 5 μm.

  Next, a ring-shaped semiconductor-side electrode 15 (p-side electrode) is formed on the p-type contact layer 229, and a substrate-side electrode 11 (n-side electrode) is formed on the other main surface 10n of the conductive GaN substrate 10. Thus, the surface emitting laser element of this example was obtained.

When a current was injected into the obtained surface emitting laser element, laser oscillation was observed at a current density of 3.2 kA / cm ² or more, and the light emission was uniform.

(Example 3)
Specific examples of the surface emitting laser element according to Embodiment 5 will be described below. First, a conductive GaN multi-region substrate (conductive GaN substrate 10) having the same characteristics as in Example 1 was produced. Next, referring to FIG. 8B, a plurality of III-V group compound semiconductors including a light emitting layer 200 on one main surface 10m of an n-type conductive GaN multi-region substrate (conductive GaN substrate 10). The layer 20 is formed, the semiconductor layer side electrode 15 is formed on the uppermost layer of the III-V compound semiconductor layer, and the other main surface 10n of the n-type conductive GaN multi-region substrate (conductive GaN substrate 10) is formed. The substrate-side electrode 11 was formed thereon so that the light emitting region 200a of the light emitting layer 200 was positioned above the low dislocation density high conductive region 10b.

  Here, the plurality of group III-V compound semiconductor layers 20 were formed by MOCVD (metal organic chemical vapor deposition). Specifically, a plurality of III-V group compound layers 20 were formed as follows.

Referring to FIG. 10, on a conductive GaN multi-region substrate (conductive GaN substrate 10),
Carrier diffusion layer 201 (n-type GaN layer), n-type cladding layer 215 (n-type Al _0.15 Ga _0.85 N cladding layer), light-emitting layer 200 (Ga _0.9 In _0.1 N / GaN multiple quantum well structure), p-type grad A layer 225 (p-type Al _0.15 Ga _0.85 N clad layer) and a crystal layer 233a (GaN layer) for forming a photonic crystal were sequentially formed.

  Next, referring to FIG. 11, resist 30 having a predetermined pattern was formed on crystal layer 233a by electron beam exposure. That is, a photoresist for electron beam exposure (ZEP520 manufactured by Nippon Zeon Co., Ltd.) was applied, and a fine hole resist pattern was drawn using an electron beam exposure machine. The pattern of the resist 30 was a square lattice, and fine holes having a diameter of 0.06 μm were spaced at intervals of 0.16 μm.

  Next, referring to FIG. 12, the crystal layer 233a is etched by using an ICP (Inductively coupled plasma) -RIE (Reactive Ion Etching) method using the resist 30 as a mask, and a depth of 0 is formed at a predetermined position of the crystal layer 233a. A 1 μm diffraction grating hole 233b was formed, and a photonic crystal layer 233 was formed. In this way, the 1st laminated body 21 was obtained. Etching was performed in a high vacuum of about 0.4 Pa using a mixed gas of chlorine gas and a small amount of rare gas as an etching gas. For this reason, etching with high flatness and verticality was achieved.

On the other hand, referring to FIG. 13, apart from the first stacked body 21 of FIG. 12, a peeling layer 41 (In _0.4 Ga _0.6 N layer), p-type is formed on a base substrate 40 (sapphire substrate) by MOCVD. Contact layer 229 (p ⁺ -type GaN contact layer) and p-type grad layer 226 (p-type Al _0.15 Ga _0.85 N clad layer) were formed to obtain a second stacked body 22.

  Next, referring to FIG. 14, the first stacked body 21 so that the photonic crystal layer 233 of the first stacked body 21 and the p-type cladding layer 226 of the second stacked body 22 face each other. And the second laminated body 22 were fused and pasted. This fusion bonding was performed at a temperature of 700 ° C. in a nitrogen atmosphere.

  Next, referring to FIG. 15, the release layer 41 was selectively removed by etching the release layer 41 from the lateral direction while irradiating the laser beam. As a result, the p-type contact layer 229 that is the uppermost layer of the III-V group compound semiconductor layer 20 was separated from the base substrate 40, and the upper surface of the contact layer 229 was exposed as a light emission surface.

  Next, referring to FIG. 8B, the p-type contact is made such that the light emitting region 200 a of the light emitting layer 200 is located above the low dislocation density high conductive region 10 b included in the conductive GaN substrate 10. On the layer 229, the semiconductor-side electrode 15 (p-side electrode) was formed at an upper position in the low dislocation density high conductive region 10b and the low dislocation density low conductive region 10c. The area ratio between the low dislocation density high conductivity region 10b and the low dislocation density low conductivity region 10c located below the light emitting region 200a formed almost coincident with the formation region below the semiconductor side electrode 15 is 2 : 1. Next, a substrate side electrode 11 (n side electrode) was formed on the other main surface 10 of the conductive GaN substrate 10n to obtain a surface emitting laser element of this example.

When a current was injected into the obtained surface emitting laser element, laser oscillation was observed at a current density of ⁴ kA / cm ² or more, and the light emission was uniform.

  As described above, with reference to FIGS. 6, 7 and 8, in the manufacture of the surface emitting laser element 1, as the conductive GaN substrate 10, a high dislocation density and high conductivity region 10 a having a high dislocation density and carrier concentration, and a high dislocation A conductive GaN composite comprising a low dislocation density high conductive region 10b having a low dislocation density compared to a high density conductive region and a low dislocation density low conductive region 10c having a low dislocation density and carrier concentration compared to a high dislocation density high conductive region. A semiconductor layer forming step of preparing a region substrate and forming a plurality of group III-V compound semiconductor layers 20 including a light emitting layer on one main surface 10m of the conductive GaN multi-region substrate, and a group III-V compound semiconductor layer An electrode forming step of forming a semiconductor layer side electrode 15 on the uppermost layer 20 and forming a substrate side electrode 11 on the other main surface 10n of the conductive GaN multi-region substrate. Then, a carrier diffusion layer 201 that makes the in-plane distribution of carriers flowing into the light emitting layer 200 uniform is formed between the conductive GaN multi-region substrate (conductive GaN substrate 10) and the light emitting layer 200, and a semiconductor forming step, In at least one of the electrode forming steps, the light emitting region 200a in which carriers flow into at least one of the III-V compound semiconductor layer 20 and the semiconductor side electrode 15 in the light emitting layer 200 is a low dislocation density high conductive region 10b and By forming the low dislocation density so as to be restricted above the low conductive region 10c, the surface emitting laser element 1 in which the current uniformly flows into the light emitting region and the light emission in the light emitting region is uniform can be obtained. Good yield was obtained.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic diagram which shows an example of the surface emitting laser element concerning this invention. (A) is a schematic top view, (b) is a schematic cross section in line segment IB-IB of (a). It is a schematic diagram which shows the other example of the surface emitting laser element concerning this invention. (A) is a schematic top view, (b) is a schematic cross section in line segment IIB-IIB of (a). It is a schematic diagram which shows one specific example of the electroconductive GaN substrate used for this invention. (A) is a schematic top view, (b) is a schematic cross section in line segment IIIB-IIIB of (a). It is a schematic diagram which shows the other specific example of the electroconductive GaN board | substrate used for this invention. (A) is a schematic top view, (b) is a schematic cross section in line segment IVB-IVB of (a). It is a schematic plan view which shows the other specific example of the electroconductive GaN board | substrate used for this invention. (A) is a schematic top view, (b) is a schematic cross section in line segment VB-VB of (a). It is a schematic diagram which shows one specific example of the surface emitting laser element concerning this invention. (A) is a schematic plan view, (b) is a schematic cross section in line segment VIB-VIB of (a). It is a schematic diagram which shows the other specific example of the surface emitting laser element concerning this invention. (A) is a schematic top view, (b) is a schematic cross section in line segment VIIB-VIIB of (a). It is a schematic diagram which shows the other specific example of the surface emitting laser element concerning this invention. (A) is a schematic top view, (b) is a schematic cross section in line segment VIIIB-VIIIB of (a). It is a model perspective view which shows the photonic crystal layer used for this invention. It is a schematic cross section which shows the 1st process of the manufacturing method of the surface emitting element shown in FIG. It is a schematic cross section which shows the 2nd process of the manufacturing method of the surface emitting element shown in FIG. It is a schematic cross section which shows the 3rd process of the manufacturing method of the surface emitting element shown in FIG. It is a schematic cross section which shows the 4th process of the manufacturing method of the surface emitting element shown in FIG. It is a schematic cross section which shows the 5th process of the manufacturing method of the surface emitting element shown in FIG. It is a schematic cross section which shows the 6th process of the manufacturing method of the surface emitting element shown in FIG. It is a schematic plan view which shows the further another example of the surface emitting laser element concerning this invention. It is a schematic diagram which shows an example of the surface emitting laser array concerning this invention. (A) is a schematic top view, (b) is a schematic cross section in line segment XVIIB-XVIIB of (a). It is a schematic diagram which shows the other example of the surface emitting laser array concerning this invention. (A) is a schematic top view, (b) is a schematic cross section in line segment XVIIIB-XVIIIB of (a). It is a figure which shows the spreading resistance of the low dislocation density high conductive area | region of a conductive GaN substrate, and a low dislocation density low conductive area | region.

Explanation of symbols

  1 surface emitting laser element, 2 surface emitting laser array, 10 conductive GaN substrate, 10a high dislocation density high conductive region, 10b low dislocation density high conductive region, 10c low dislocation density low conductive region, 10m, 10n, 233m main surface, 11 substrate side electrode, 15 semiconductor side electrode, 17 pad electrode, 20, 210, 220 III-V group compound semiconductor layer, 21 first laminated body, 22 second laminated body, 30 resist, 40 base substrate, 41 peeling Layer, 70 bonding wire, 103 dielectric mirror, 103a formation region, 200 light emitting layer, 200a light emitting region, 201 carrier diffusion layer, 213, 223 DBR, 215, 225, 226 clad layer, 227, 229 contact layer, 233 photonic Crystal layer, 233a Crystal layer, 233b Diffraction grating hole, 250 carriers Constriction region, 250a Carrier confinement layer, 250b Insulating region.

Claims (20)

A method of manufacturing a surface emitting laser element,
As a conductive GaN substrate, a high dislocation density and high conductivity region with high dislocation density and carrier concentration, a low dislocation density and high conductivity region with a lower dislocation density than the high dislocation density and high conductivity region, and the high dislocation density and high conductivity region A step of preparing a conductive GaN multi-region substrate including a low dislocation density and low conductivity region having a low dislocation density and carrier concentration compared to
A semiconductor layer forming step of forming a plurality of III-V compound semiconductor layers including a light emitting layer on one main surface of the conductive GaN multi-region substrate;
Forming a semiconductor layer side electrode on the uppermost layer of the III-V compound semiconductor layer, and forming a substrate side electrode on the other main surface of the conductive GaN multi-region substrate,
In the semiconductor layer forming step, a carrier diffusion layer that makes the in-plane distribution of carriers flowing into the light emitting layer uniform is formed between the conductive GaN multi-region substrate and the light emitting layer,
In at least one of the semiconductor formation step and the electrode formation step, a light emitting region into which carriers flow in at least one of the III-V compound semiconductor layer and the semiconductor side electrode in the light emitting layer is the low dislocation. A method of manufacturing a surface-emitting laser element, characterized by being formed so as to be restricted above the high density conductive region and the low dislocation density low conductive region.   In the electrode formation step, the semiconductor-side electrode is formed in the low dislocation density high conductive region and the low dislocation density so that the light emitting region is restricted above the low dislocation density high conductive region and the low dislocation density low conductive region. 2. The method of manufacturing a surface emitting laser element according to claim 1, wherein the dislocation density is formed at an upper position in the low conductive region.   In the semiconductor formation step, a carrier confinement region is formed in the III-V group compound semiconductor layer so that the light emitting region is restricted above the low dislocation density high conductivity region and the low dislocation density low conductivity region. The method of manufacturing a surface emitting laser element according to claim 1. The high dislocation density and high conductivity region is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density and high conductivity region has a dislocation density of 1 × 10 ^6. cm carrier concentration of less than ^-2 is 1 × 10 ¹⁸ cm ^-3 or more regions, the low dislocation density low conductance region dislocation density 1 × 10 ⁶ cm carrier concentration of less than ^-2 1 × 10 ¹⁸ cm ^{- The} method for manufacturing a surface emitting laser element according to any one of claims 1 to ^{3, wherein} the area is less than ³ . 5. The method for manufacturing a surface emitting laser element according to claim 1, wherein the carrier diffusion layer has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. Formed on a conductive GaN substrate, a plurality of III-V compound semiconductor layers including a light emitting layer formed on one main surface of the conductive GaN substrate, and an uppermost layer of the III-V compound semiconductor A surface emitting laser element including a semiconductor layer side electrode that is formed and a substrate side electrode formed on the other main surface of the conductive GaN substrate,
The conductive GaN substrate has a low dislocation density high conductivity region in which a dislocation density is less than 1 × 10 ⁶ cm ⁻² and a carrier concentration is 1 × 10 ¹⁸ cm ⁻³ or more, and a dislocation density is 1 × 10 ⁶ cm. ^A low dislocation density low conductivity region that is a region of less than ⁻² and a carrier concentration of less than 1 × 10 ¹⁸ cm ⁻³ ,
The III-V compound semiconductor layer includes a carrier diffusion layer that is formed between the conductive GaN substrate and the light emitting layer and uniforms an in-plane distribution of carriers flowing into the light emitting layer,
A surface-emitting laser element, wherein a light-emitting region into which carriers flow in the light-emitting layer is located above the low dislocation density and high conductivity region and the low dislocation density and low conductivity region.   The semiconductor-side electrode is located in the low dislocation density high conductivity region and the low dislocation density high conductivity region so that the light emitting region is located above the low dislocation density high conductivity region and the low dislocation density low conductivity region. The surface emitting laser element according to claim 6, wherein the surface emitting laser element is formed at an upper position.   A carrier confinement region is formed in the group III-V compound semiconductor layer so that the light emitting region is located above the low dislocation density high conductive region and the low dislocation density low conductive region. The surface emitting laser element according to claim 6. 9. The surface emitting laser element according to claim 6, wherein the carrier diffusion layer has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. The conductive GaN substrate further includes a high dislocation density and high conductivity region, which is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more. The surface emitting laser element according to any one of the above. A method of manufacturing a surface emitting laser array including a plurality of surface emitting laser elements,
As the conductive GaN substrate, a high dislocation density and high conductivity region having a high dislocation density and a carrier concentration, a low dislocation density and high conductivity region having a dislocation density lower than that of the high dislocation density and high conductivity region, and the high dislocation density and high conductivity. Preparing a conductive GaN multi-region substrate including a low dislocation density and low conductivity region having a low dislocation density and carrier concentration compared to the region;
A semiconductor layer forming step of forming a plurality of III-V compound semiconductor layers including a light emitting layer on one main surface of the conductive GaN multi-region substrate;
Forming a semiconductor layer side electrode on the uppermost layer of the III-V compound semiconductor layer, and forming a substrate side electrode on the other main surface of the conductive GaN multi-region substrate,
In the semiconductor layer forming step, a carrier diffusion layer that makes the in-plane distribution of carriers flowing into the light emitting layer uniform is formed between the conductive GaN multi-region substrate and the light emitting layer,
Each surface emitting laser included in the surface emitting laser array includes at least one of the III-V compound semiconductor layer and the semiconductor side electrode in at least one of the semiconductor forming step and the electrode forming step. A surface-emitting laser array, characterized in that a light-emitting region into which carriers flow in the light-emitting layer of the element is restricted above the low dislocation density and high conductivity region and the low dislocation density and low conductivity region. Production method.   In the electrode formation step, the semiconductor-side electrode is formed in the low dislocation density high conductive region and the low dislocation density so that the light emitting region is restricted above the low dislocation density high conductive region and the low dislocation density low conductive region. 12. The method of manufacturing a surface emitting laser array according to claim 11, wherein the dislocation density is formed at an upper position in the low conductive region.   In the semiconductor layer forming step, a carrier confinement region is formed in the III-V group compound semiconductor layer so that the light emitting region is restricted above the low dislocation density high conductivity region and the low dislocation density low conductivity region. The method of manufacturing a surface emitting laser array according to claim 11, wherein the surface emitting laser array is formed. The high dislocation density and high conductivity region is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density and high conductivity region has a dislocation density of 1 × 10 ^6. cm carrier concentration of less than ^-2 is 1 × 10 ¹⁸ cm ^-3 or more regions, the low dislocation density low conductance region dislocation density 1 × 10 ⁶ cm carrier concentration of less than ^-2 1 × 10 ¹⁸ cm ^{- The} method of manufacturing a surface emitting laser array according to any one of claims 11 to 13, wherein the area is less than ³ . The method of manufacturing a surface emitting laser array according to claim 11, wherein the carrier diffusion layer has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more. A surface emitting laser array including a plurality of surface emitting laser elements,
The surface-emitting laser element includes a conductive GaN substrate, a plurality of III-V compound semiconductor layers including a light-emitting layer formed on one main surface of the conductive GaN substrate, and the III-V compound A semiconductor layer side electrode formed on the uppermost layer of the semiconductor layer, and a substrate side electrode formed on the other main surface of the conductive GaN substrate, the III-V group compound semiconductor layer, A carrier diffusion layer that is formed between the conductive GaN substrate and the light emitting layer and makes the in-plane distribution of carriers flowing into the light emitting layer uniform;
The surface emitting laser array includes a high dislocation density and high conductivity region having a high dislocation density and a carrier concentration, a low dislocation density and high conductivity region having a dislocation density lower than that of the high dislocation density and high conductivity region, and the high dislocation density and high conductivity. A conductive GaN multi-region substrate including a low dislocation density and a low conductive region having a low dislocation density and carrier concentration compared to the region;
A light emitting region into which carriers flow in the light emitting layer of each of the surface emitting laser elements included in the surface emitting laser array is located above the low dislocation density high conductive region and the low dislocation density low conductive region. A surface emitting laser array characterized by comprising:   The semiconductor-side electrode is located in the low dislocation density high conductivity region and the low dislocation density high conductivity region so that the light emitting region is located above the low dislocation density high conductivity region and the low dislocation density low conductivity region. The surface emitting laser array according to claim 16, wherein the surface emitting laser array is formed at an upper position. A carrier confinement region is formed in the group III-V compound semiconductor layer so that the light emitting region is located above the low dislocation density high conductive region and the low dislocation density low conductive region. The surface emitting laser array according to claim 16.
The high dislocation density and high conductivity region is a region having a dislocation density of 1 × 10 ⁶ cm ⁻² or more and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and the low dislocation density and high conductivity region has a dislocation density of 1 × 10 ^6. cm carrier concentration of less than ^-2 is 1 × 10 ¹⁸ cm ^-3 or more regions, the low dislocation density low conductance region dislocation density 1 × 10 ⁶ cm carrier concentration of less than ^-2 1 × 10 ¹⁸ cm ^- The surface emitting laser array according to any one of claims 16 to 18, wherein the surface emitting laser array is an area of less than ³ . 20. The surface emitting laser array according to claim 16, wherein the carrier diffusion layer has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ or more and a thickness of 4 μm or more.

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