JP2008117834A - Fuse cutting method, semiconductor device provided with fuse, and method for manufacturing the same device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fuse cutting method for controlling shape of processing when a thick film Cu fuse is cut with irradiation of laser. <P>SOLUTION: The fuse cutting method is capable of switching circuits by cutting the Cu fuse provided in the semiconductor device with irradiation of laser from an external side. Film thickness at a part of the Cu fuse to be cut is 0.9 μm or more, wavelength of laser to be irradiated is within the range from 0.6 μm to 1.3 μm, and pulse irradiation time of laser is in a range from 9 ns to 50 ns. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of cutting a thick film Cu fuse by laser irradiation, a semiconductor device including such a Cu fuse in a wiring layer, and a method of manufacturing the same.

  With the increase in speed and integration of semiconductor devices, miniaturization of wiring and multilayer wiring are being promoted. In a logic device having such a multilayer wiring, a signal delay in the wiring is becoming one of the dominant factors of the signal delay in the device. In recent years, Cu wiring having lower wiring resistance than conventional Al wiring has been adopted as a solution. In particular, a method has been adopted in which a thick Cu wiring is used in a global wiring layer that greatly affects the signal delay in the wiring, thereby reducing the electrical resistance in the wiring and reducing the signal delay.

  On the other hand, in the logic device, the mounted memory capacity is also increasing, and fuses are used for device adjustment for relieving defective bits in the memory and increasing the functionality of the device. As a fuse method, there are a cut-off method for changing from a conductive state to a non-conductive state and a conductive method for changing from a non-conductive state to a conductive state. Further, as one of the cutting type methods, there is a laser trimming method in which a fuse is cut by laser irradiation. In the laser trimming method, a circuit is switched by cutting a fuse provided in advance in a semiconductor device by laser irradiation from the outside.

  A fuse uses a wiring layer in the device from the viewpoint of process reduction, and in a semiconductor device using Cu wiring, the fuse is often used as a material. And since the thick Cu wiring is used for the global wiring in the upper layer of the multilayer wiring device, the thick Cu wiring is used as a fuse, and it is necessary to cut the thick Cu fuse. Due to the increased film thickness of the Cu fuse, it is difficult to cut the fuse.

As a method for cutting a thick Cu fuse, for example, a light absorbing material is used as a barrier member for covering the bottom and side surfaces of a fusible member in the Cu fuse, and the thickness of the light absorbing member is changed to a laser used for fusing. A method of adjusting the thickness to 50% to 300% of the thickness showing the maximum absorption efficiency is known, and tantalum nitride, tungsten nitride, titanium nitride, or the like is introduced as a light absorbing member (see Patent Document 1). However, in this method, it is difficult to control the processed shape of the fuse after cutting.
JP 2004-96064 A

  A plan view of the fuse box of the semiconductor device is shown in FIG. In the example shown in FIG. 10, 38 fuses 201 are arranged, and two dummy fuses 201a are arranged at both ends. The dummy fuse 201a is disposed to align the fuse shape. As shown in FIG. 10, a guard ring layer 202 is disposed around the fuse 201. The guard ring layer 202 is disposed so that moisture from the fuse opening 204 does not affect the internal circuit. A determination circuit 203 is disposed adjacent to the fuse 201, and the determination circuit 203 determines cutting information of the fuse 201.

  FIG. 9A shows a cross-sectional view of a conventional semiconductor device, including the fuse box, cut in the IXA-IXA direction shown in FIG. The IXA-IXA direction in FIG. 10 is a direction perpendicular to the substrate 205 in FIG. In the example of the semiconductor device shown in FIG. 9A, there are nine wiring layers (M1 to M9), and a Cu wiring 206 is formed. The Cu fuse 201 is formed in the uppermost global wiring layer (M9). A p-TEOS (tetraethoxysilane) layer 208, a passivation layer 209, and a polyimide layer 210 are formed on the uppermost global wiring layer (M9). In this specification, the uppermost global wiring layer refers to the global wiring layer located at the uppermost position when having a plurality of global wiring layers. Further, when the global wiring layer is a single layer, it indicates the global wiring layer located at the top.

  FIG. 9B shows an enlarged view of the main part of the Cu fuse 201 portion in FIG. As shown in FIG. 9B, the Cu fuse 201 includes a Cu portion 211 of the fuse body and a barrier layer 212 for preventing diffusion of Cu to the interlayer insulating film 207 around the Cu portion. An SiCN layer 208 is provided immediately below the Cu fuse 201 as an etching stopper when forming the Cu fuse. As shown in FIG. 9B, the laser 213 irradiates the Cu fuse 201 in the direction of the arrow from above the device.

  FIG. 11 shows the state of the Cu fuse after being cut by laser irradiation. 11 (a) and 11 (c) show examples in which the shape after cutting is abnormal, and FIGS. 11 (b) and 11 (d) show examples in which the shape after cutting is normal. Comparing FIG. 11 (a) and FIG. 11 (b), in the normal example shown in FIG. 11 (b), the fuse is cut into a rectangle along the shape of the Cu fuse 201. There is no influence. On the other hand, in the example in which the shape after cutting shown in FIG. 11A is abnormal, the hole 214 of the cut portion by laser irradiation spreads in the lateral direction of the Cu fuse 201, and the spread of the hole 214 is adjacent. The Cu fuse is reached and the adjacent Cu fuse is damaged.

  FIG.11 (d) is sectional drawing of XID-XID in FIG.11 (b). As shown in FIG. 11D, the Cu fuse is melted in a rectangular shape in the cross-sectional direction, and the shape after cutting is normal. FIG.11 (c) is sectional drawing of XIC-XIC in Fig.11 (a). In the example shown in FIG. 11C, an explosion is caused by laser irradiation, a hole 214 is generated, and no trace of the fuse is recognized in the portion 215 where the Cu fuse is present, and the SiCN layer under the Cu fuse is affected by the explosion. The interface between 208 and the interlayer insulating film 207 is peeled off, and the shape after laser cutting is abnormal.

  FIG. 8 is a diagram showing the relationship between the film thickness of the Cu fuse and the rate of occurrence of shape abnormality when the Cu fuse is cut by a laser having a laser wavelength of 1.342 μm and a pulse width of 10 nsec. As shown in FIG. 8, as the thickness of the Cu fuse increases, the occurrence rate of the shape abnormality tends to increase. When the thickness of the Cu fuse becomes 0.9 μm or more, particularly 1.0 μm or more, the shape abnormality occurs. The incidence of is increasing rapidly.

  The subject of this invention is providing the cutting method of the fuse which can control the process shape at the time of cutting a thick film Cu fuse by laser irradiation. It is another object of the present invention to provide a semiconductor device including such a fuse and a manufacturing method thereof.

  The present invention relates to a fuse cutting method for switching a circuit by cutting a Cu fuse provided in a semiconductor device by external laser irradiation, and the film thickness of a portion to be cut of the Cu fuse is 0.9 μm or more. Yes, the wavelength of the laser to be irradiated is 0.6 μm to 1.3 μm, and the pulse irradiation time of the laser is 9 nsec to 50 nsec. In the Cu fuse, an aspect in which the width of the part to be cut is 0.6 μm to 1.2 μm is preferable, and an aspect in which the film thickness of the part to be cut is 1.0 μm to 1.4 μm is preferable.

  The present invention relates to a semiconductor element formed on a main surface of a semiconductor substrate, one or more lower wiring layers formed on the semiconductor element, and one or more layers having a Cu wiring formed on the lower wiring layer. A semiconductor device comprising a global wiring layer. The global wiring layer includes a via layer and a wiring layer formed on the via layer with an etching stopper layer interposed therebetween, and the wiring layer in the uppermost global wiring layer in the global wiring layer having Cu wiring is a laser from the outside. A Cu fuse for switching circuits by cutting by irradiation is provided, and the film thickness of the cut portion of the Cu fuse is 0.9 μm or more. The etching stopper layer in the uppermost global wiring layer has a one-layer structure of SiN, a two-layer structure of SiCO and SiCN, or a two-layer structure of tetraethoxysilane and SiCN. The global wiring layer preferably has an interlayer insulating film containing fluorinated silicate glass. In a semiconductor device having a plurality of global wiring layers, the material of the etching stopper layer in the uppermost global wiring layer is the material of the etching stopper layer in the global wiring layer disposed below the uppermost global wiring layer, and the lower layer. It is possible to adopt a mode different from the material of the etching stopper layer in the wiring layer. Also, a plurality of global wiring layers may be provided, and the etching stopper layer in the uppermost global wiring layer may have a different material from the etching stopper layer in the global wiring layer disposed below the uppermost global wiring layer. it can.

  In the present invention, a step of forming a semiconductor element on a main surface of a semiconductor substrate, a step of forming a lower wiring layer on the semiconductor element, and one or more layers having a lower wiring layer and a barrier insulating layer are formed. And a step of forming one or more global wiring layers having Cu wiring. The step of forming a global wiring layer includes a step of forming a via layer and a step of forming a wiring layer on the via layer with an etching stopper layer interposed therebetween, and the innermost wiring layer in the global wiring layer having Cu wiring The wiring layer is provided with a Cu fuse that is switched by switching the circuit by laser irradiation from the outside. The thickness of the cut portion of the Cu fuse is 0.9 μm or more, and the etching stopper layer in the uppermost global wiring layer is a single layer structure of SiN, a two layer structure of SiCO and SiCN, or tetraethoxy It has a two-layer structure of silane and SiCN.

  According to another aspect of the method for manufacturing a semiconductor device of the present invention, a step of forming a semiconductor element on a main surface of a semiconductor substrate, a lower wiring layer on the semiconductor element, a lower wiring layer, a barrier insulating layer, Forming one or a plurality of layers each having Cu, and then forming one or a plurality of global wiring layers having a Cu wiring. The step of forming the uppermost layer of the global wiring layer includes a step of forming a via layer having an etching stopper layer on the uppermost portion, a step of plasma processing the etching stopper layer in a He atmosphere, and a wiring layer on the via layer. Forming. The wiring layer in the uppermost global wiring layer in the global wiring layer having Cu wiring is provided with a Cu fuse that is cut by laser irradiation from the outside to switch the circuit, and the thickness of the cut portion of the Cu fuse is 0. The etching stopper layer in the uppermost global wiring layer has a single-layer structure of SiCN.

  The processed shape after cutting the Cu fuse by laser irradiation can be precisely controlled, and as a result, the area where the Cu fuse is disposed can be reduced and the chip can be reduced. Moreover, since the influence on the Cu fuse periphery at the time of Cu fuse cutting | disconnection can be made small, the reliability of a semiconductor device can be improved.

(Semiconductor device)
FIG. 1 is a diagram showing the structure of a semiconductor device of the present invention. As shown in FIG. 1, this semiconductor device has a wiring region and a fuse region, and an opening 15 is formed in the fuse region. In addition, a semiconductor device 1 formed on the main surface of the semiconductor substrate 2, a plurality of lower wiring layers M1 to M7 formed on the semiconductor device 1, and a plurality of global wirings having a Cu wiring formed on the lower wiring layer Layers M8 and M9. Further, a global wiring layer M10 in which an aluminum wiring or an aluminum alloy is formed is provided on the global wiring layer M9. The example shown in FIG. 1 shows an example in which seven lower wiring layers M1 to M7 and three global wiring layers M8 to M10 are formed. In addition to the example shown in FIG. The configuration of the present invention is effective even for a semiconductor device composed of one global wiring layer.

  The global wiring layers M8 and M9 include the via layer 3 and the wiring layers 5 and 5a formed on the via layer 3 with the etching stopper layers 4 and 4a sandwiched therebetween. The wiring layer 5a in the layer M9 is provided with a Cu fuse 6 that is cut by external laser irradiation to switch circuits. Further, the thickness of the cut portion of the Cu fuse 6 is 0.9 μm or more, and the etching stopper layer 4a in the uppermost global wiring layer M9 has a single layer structure of SiN or a two layer structure of SiCO and SiCN. Or a two-layer structure of tetraethoxysilane (TEOS) and SiCN. Since the semiconductor device of the present invention having such a structure can precisely control the processed shape when the Cu fuse is cut by laser irradiation, the area where the Cu fuse is disposed can be reduced and the chip can be reduced. Further, since the influence on the periphery of the Cu fuse when cutting the Cu fuse is small, the reliability of the semiconductor device can be improved.

  In order to normalize the processed shape when the Cu fuse is cut by laser irradiation, the fuse structure is first examined. The reason why the processed shape becomes abnormal is that the adhesion of the interface between the etching stopper layer made of SiCN and the interlayer insulating film layer containing fluorinated silicate glass (FSG) in the uppermost global wiring layer. Small things can be mentioned. Therefore, there is a method of eliminating SiCN that has been used as an etching stopper layer from the past, and this can fundamentally suppress abnormal shapes. However, if the SiCN layer is omitted, thick-film wiring becomes difficult, and processing control when forming vias becomes difficult.

  Therefore, it is preferable that the etching stopper layer in the uppermost global wiring layer has a single-layer structure of SiN, a two-layer structure of SiCO and SiCN, or a two-layer structure of TEOS and SiCN instead of the SiCN layer. . According to such an embodiment, the adhesion between the interlayer insulating film containing FSG and the etching stopper layer can be improved, so that the interlayer insulating film containing FSG can be formed in the global wiring layer. FIG. 2 is an enlarged view of a main part of the Cu fuse 16 in FIG. 1. For example, as shown in FIG. 2A, a mode in which a SiN layer 21 is used as an etching stopper layer is preferable. Further, as shown in FIG. 2B, a two-layer structure of SiCO / SiCN having a SiCO layer 23 sandwiched between the FSG layer 24 and the SiCN layer 22 is preferable. Furthermore, as shown in FIG. 2C, a structure in which the TEOS layer 26 is sandwiched between the FSG layer 24 and the SiCN layer 25 is preferable for improving the adhesion. Further, as shown in FIG. 2 (d), the adhesion between the FSG layer and the etching stopper layer can be improved by an interface treatment such as performing a plasma treatment in a He gas atmosphere after only the SiCN layer 26 is formed. Can do.

  These etching stopper layer changes and interface treatments need only be performed on the etching stopper layer in the uppermost global wiring layer used as the fuse layer, and the etching stopper layer of the wiring layer used other than the fuse layer may be used. May not be implemented. For example, in FIG. 1, there is no etching stopper layer in the lower wiring layers M1 to M7, and the global wiring layer M8 immediately below the uppermost global wiring layer M9 which is a fuse layer has a wiring film thickness. Since it is thick, a SiCN layer is used as the etching stopper layer 4. A plurality of global wiring layers M8 and M9 are provided, and the etching stopper layer 4a in the uppermost global wiring layer M9 is made of the same material as the etching stopper layer 4 in the global wiring layer M8 disposed under the uppermost global wiring layer M9. Different embodiments can be used. FIG. 20 is a diagram showing the structure of a semiconductor device according to another embodiment of the present invention. In FIG. 20, as in FIG. 1, there is no etching stopper layer in the lower wiring layers M1 to M5, but M6 and M7 whose wiring film thickness is thicker than M1 to M5 have a wiring groove depth control. In order to improve the performance, etching stopper layers 4d and 4e are present. As in FIG. 1, the etching stopper layers 4 and 4a exist in the global wirings M8 and M9 having a wiring thickness larger than that of M6 and M7. In this case, the etching stopper layers 4d and 4e in the lower wiring layers M6 to M7 may be made of a material having a material different from that of the etching stopper layer 4a in the uppermost global wiring layer.

  As shown in FIG. 2A, when the film thickness t becomes too large, the Cu fuse requires a large amount of energy for cutting, and accordingly, damage to the underlying Si substrate by the laser increases. Therefore, the thickness t of the part to be cut is preferably 2.0 μm or less, and more preferably 1.4 μm or less. On the other hand, an object of the present invention is to cut a thick film Cu fuse in a good shape. Specifically, a Cu fuse having a film thickness t of 0.9 μm or more can be cut, and the film thickness t is 1 Thick film fuses of 0.0 μm or more can be easily cut. Further, the width w of the Cu fuse is preferably 0.6 μm or more, and more preferably 0.7 μm or more, from the viewpoint of improving the reliability of the fuse wiring. On the other hand, it is possible to cut a fuse having a width w of the cut portion of preferably 1.2 μm or less, more preferably 1.0 μm or less, and the shape after cutting is also normal.

(Semiconductor device manufacturing method)
The method for manufacturing a semiconductor device of the present invention includes a step of forming a semiconductor element on a main surface of a semiconductor substrate, a lower wiring layer formed on the semiconductor element, and a single layer having a lower wiring layer and a barrier insulating layer. Forming a single or multiple global wiring layer having Cu wiring after forming the plurality of layers. The step of forming a global wiring layer includes a step of forming a via layer and a step of forming a wiring layer on the via layer with an etching stopper layer interposed therebetween, and the innermost wiring layer in the global wiring layer having Cu wiring The wiring layer is provided with a Cu fuse that is switched by switching the circuit by laser irradiation from the outside, and the thickness of the cut portion of the Cu fuse is 0.9 μm or more. The etching stopper layer in the uppermost global wiring layer has a one-layer structure of SiN, a two-layer structure of SiCO and SiCN, or a two-layer structure of TEOS and SiCN. With this method, it is possible to manufacture a semiconductor device including a fuse capable of controlling a processing shape when a thick film Cu fuse is cut by laser irradiation.

  Another aspect of the method for manufacturing a semiconductor device of the present invention includes a step of forming a semiconductor element on a main surface of a semiconductor substrate, a lower wiring layer formed on the semiconductor element, and a layer having a lower wiring layer and a barrier insulating layer Forming one or more global wiring layers, and then forming one or more global wiring layers having Cu wiring. The step of forming the uppermost layer of the global wiring layer includes a step of forming a via layer having an etching stopper layer on the uppermost portion, a step of plasma processing the etching stopper layer in a He atmosphere, and a wiring layer on the via layer. Forming. The wiring layer in the uppermost global wiring layer in the global wiring layer having Cu wiring is provided with a Cu fuse that is cut by laser irradiation from the outside to switch the circuit, and the thickness of the cut portion of the Cu fuse is 0. The etching stopper layer in the uppermost global wiring layer has a single-layer structure of SiCN. After forming the etching stopper layer, the He plasma treatment is performed, whereby the adhesion between the etching stopper layer and the wiring layer containing FSG can be improved.

  As an embodiment, a method for manufacturing a semiconductor device having nine Cu wiring layers and a Cu fuse composed of a lower wiring layer and a global wiring layer will be described with reference to FIG. Various forms conventionally known can be applied to the formation of the lower wiring layer, the formation of the global wiring layer, and the like. Also, the number of layers of the lower wiring layer and the global wiring layer can be arbitrarily set according to the purpose.

  First, the semiconductor element 1 such as MISFET and the element isolation film 7 are formed on the main surface of the semiconductor substrate 2 made of single crystal silicon or the like, and the insulating film 8 made of silicon oxide or the like is deposited by the CVD method. Next, the insulating film 8 is etched to form a contact hole, and a plug 9 made of TiN, W or the like is formed inside the contact hole. Then, after depositing an etching stopper film 10 such as SiCN and an insulating film 11 such as TEOS by a CVD method, dry etching is performed using a photoresist film (not shown) as a mask to form a wiring groove, When the Cu wiring layer 16 is deposited inside the wiring groove by sputtering or plating and the Cu film outside the wiring groove is removed by chemical mechanical polishing (CMP), the first lower wiring layer M1 is formed. .

  Next, a barrier insulating layer 12 and an interlayer insulating film 13 are deposited on the insulating film 11 of the first wiring layer M1 by a CVD method. The barrier insulating layer 12 is an insulating film for preventing Cu, which is a material of the insulating film 11, from diffusing into the interlayer insulating film 13, and is made of SiCN or the like. After forming the barrier insulating layer 12, it is preferable to perform plasma treatment in a He gas atmosphere because the adhesion between the layers is increased. The interlayer insulating film 13 is made of SiCO or the like. Subsequently, an antireflection film (BARC) is formed, and after photolithography, the antireflection film and the interlayer insulating film 13 are sequentially dry-etched to form via holes on the Cu wiring layer 16, The resist film and the antireflection film are removed. After filling the via hole with a filling agent, an antireflection film is formed, photolithography is performed, and then the interlayer insulating film 13 is partially removed by dry etching to form a wiring groove, a photoresist film, an antireflection film When the film, the filling agent in the via hole, and the barrier insulating layer 12 are dry-etched, the surface of the Cu wiring layer 16 is exposed at the bottom of the via hole. Thereafter, when the Cu wiring layer 14 is deposited in the wiring trench and the via hole, a second lower wiring layer M2 is formed. The lower wiring layers M3 to M7 can be formed by the same method as that for the lower wiring layer M2. In this example, in the lower wiring layers M2 to M5, the via layer and the wiring layer are both made of SiCO, and in the lower wiring layers M6 and M7, the via layer is made of TEOS and the wiring layer is made of FSG.

  The global wiring layer M8 formed on the lower wiring layer M7 can also be manufactured by forming a via layer and forming a wiring layer on the via layer in the same manner as the lower wiring layers M2 to M7. As described above, when the thickness of the interlayer insulating film is increased, it becomes difficult to etch the interlayer insulating film halfway through time control and to control the depth of the wiring trench with high accuracy. Therefore, the depth of the wiring trench is controlled by forming the etching stopper layer 4 in the middle of the interlayer insulating film. In the present embodiment, as the etching stopper layer 4, a SiCN layer and a TEOS layer are formed by a plasma CVD method. Further, FSG is deposited as interlayer insulation of the global wiring layer M8.

  12 to 19 are cross-sectional views of relevant parts showing the manufacturing process of the semiconductor device of the present invention. First, as shown in FIG. 19A, an interlayer insulating film 45 and a stopper film 46 are sequentially stacked on the interlayer insulating film 35 and the barrier insulating layer 44 of the global wiring layer M8. When the formed stopper film 46 is a single layer of SiCN, the surface is subjected to plasma treatment in a He atmosphere. The plasma treatment under the He atmosphere improves the adhesion between the stopper film 46 and an interlayer insulating film 45 laminated on the stopper film 46, which will be described later, and precisely forms the fuse shape after laser irradiation. can do. When the formed stopper film 46 is a SiN film, when it has a two-layer structure of a SiCN film and a SiCO film formed thereon, and when it is a SiCN film and a TEOS film formed thereon, Plasma treatment under a He atmosphere may be omitted. Even in the case of these stopper films, the adhesion between the stopper film 46 and an interlayer insulating film 45 laminated on the stopper film 46 described later is improved by plasma treatment in a He atmosphere, and after laser irradiation. It is possible to make the shape of the fuse processing precise. Next, as shown in FIG. 19B, an interlayer insulating film 45 is formed on the stopper film 46.

  Thereafter, as shown in FIG. 12A, a global wiring layer M9 is formed. After the formation of the antireflection film 47 and the photoresist film, a photoresist film 48 is obtained by lithography. Using the photoresist film 48 as a mask, the antireflection film 47, the interlayer insulating film 45, the stopper film 46, and the interlayer insulating film 45 are sequentially formed. By dry etching, a via hole 49 is formed on the Cu wiring layer 43 of the eighth layer. Next, after removing the photoresist film 48 and the antireflection film 47, as shown in FIG. 12B, a filling agent 50 is filled in the via hole 49. Thereafter, a photoresist film is directly formed on the interlayer insulating film 45 without using an antireflection film.

  The photoresist film is exposed by using a photomask (not shown) in which a wiring groove pattern and a fuse pattern are formed, and then developed, so that a wiring is formed as shown in FIG. A photoresist film 51 having a pattern in which the groove forming region and the fuse forming region are opened is formed. As described above, the etching stopper film 46 having a low light reflectance is formed in the middle of the interlayer insulating film 45. Next, as shown in FIG. 13B, the interlayer insulating film 45 is dry-etched using the photoresist film 51 as a mask, and the etching is stopped on the surface of the stopper film 46. As a result, wiring grooves 52 and 53 are formed in the interlayer insulating film 45 on the upper layer of the stopper film 46.

  Next, after removing the photoresist film 51, as shown in FIG. 14A, the filling agent 50 filled in the via hole 49 is removed by dry etching, so that an eighth layer of Cu is formed at the bottom of the via hole 49. The surface of the wiring layer 43 is exposed. Next, as shown in FIG. 14B, a ninth-layer Cu wiring layer 54 is formed inside the wiring groove 52 and the via hole 49, and a Cu fuse 55 is formed inside the wiring groove 53. Although not shown, the Cu fuse 55 is connected to the resistance element through the lower layer wiring. When a defect is found by a probe test described later, the resistance value of the resistance element is changed by cutting the Cu fuse 55 using a laser beam, and the defective element is replaced with a redundant element.

  In order to form the Cu wiring layer 54 and the fuse 55, a barrier metal film made of thin TiN or the like is deposited on the interlayer insulating film 45 including the inside of the wiring trenches 52 and 53 and the via hole 49 by a sputtering method. After a thick Cu film is deposited on the TiN film by sputtering or plating, the Cu film and the barrier metal film outside the wiring grooves 52 and 53 are removed by chemical mechanical polishing. Although the etching stopper film 46 remains in the interlayer insulating film 45, the upper eighth wiring layer is laid out so that the distance between the wirings is larger than that of the first to seventh wiring layers. Since the interlayer insulating film 45 is formed thick, the increase in inter-wiring capacitance and wiring inter-layer capacitance is almost negligible.

  Next, as shown in FIG. 15, a barrier insulating layer 56 and an interlayer insulating film 57 are deposited on the Cu wiring layer 54 and the fuse 55. The barrier insulating layer 56 is an insulating layer for preventing diffusion of Cu, and SiCN is deposited by the plasma CVD method as in the lower barrier insulating layer 44. The interlayer insulating film 57 is made of FSG or the like and has a thickness of about 900 nm. In FIG. 15 and the following drawings, the portion below the Cu wiring layer 54 is omitted. Over the Cu wiring layer 54 and the fuse 55, an interlayer insulating film and a surface protective film are formed. In addition, an opening for irradiating the fuse 55 with a laser beam is formed in the interlayer insulating film and the surface protective film above the fuse 55. Therefore, when external moisture enters the circuit through this opening, the fuse 55 may be corroded. Therefore, the film thickness of the barrier insulating layer 56 is made larger than the film thickness of the lower barrier insulating layer 44 to improve the moisture resistance of the fuse 55.

  Next, as shown in FIG. 16, the uppermost layer wiring 60 is formed on the interlayer insulating film 57, and then the surface protective film 61 is formed on the uppermost layer wiring 60. In order to form the uppermost layer wiring 60, first, the interlayer insulating film 57 on the upper layer of the Cu wiring layer 54 is dry-etched using a photoresist film (not shown) as a mask, and then the barrier insulating layer 56 on the lower layer is formed. After the through hole 58 is formed by dry etching, a plug 59 is formed inside the through hole 58. The plug 59 is composed of a laminated film of a TiN film and a W film, like the lower plug. Next, a TiN film having a thickness of about 50 nm to 100 nm, an Al alloy film having a thickness of about 1 μm, and a TiN film having a thickness of about 50 nm to 100 nm are deposited on the interlayer insulating film 57 by a sputtering method, and a photoresist film (FIG. The uppermost layer wiring 60 is formed by etching these conductive films using (not shown) as a mask. Further, the surface protective film 61 on the uppermost wiring 60 is formed by a laminated film of a silicon oxide film having a thickness of about 200 nm and a SiN film having a thickness of about 600 nm deposited by plasma CVD.

Next, as shown in FIG. 17, the surface protection film 61 is dry-etched using a photoresist film (not shown) as a mask to expose a part of the uppermost layer wiring 60, thereby forming a bonding pad 60B. To do. Further, the opening 62 is formed by dry etching the surface protective film 61 and the interlayer insulating film 57 which are the upper layers of the fuse 55. At this time, etching is stopped on the barrier insulating layer 56 covering the fuse 55, and the barrier insulating layer 56 is left on the fuse 55. As shown in FIG. 18, a polyimide resin film 63 is deposited on the surface protective film 61. Thereafter, a probe (not shown) is applied to the surface of the bonding pad, and an electrical test of the circuit is performed. In this test, when a defect of a semiconductor element is found, switching to a redundant element provided in advance in the chip is performed. Switching is performed by cutting a fuse with a laser beam. At present, a semiconductor laser having a wavelength in the near infrared region of about 1.0 μm to 1.4 μm is used as a laser widely used for laser trimming. For example, a YLF (lithium yttrium fluoride; LiYF ₄ ) laser is used. Vanadate-based solid-state lasers are also used.

(Fuse cutting method)
In the fuse cutting method of the present invention, the film thickness of the cut portion of the Cu fuse is 0.9 μm or more, the wavelength of the laser to be irradiated is 0.6 μm to 1.3 μm, and the laser pulse irradiation time is 9 n. Seconds to 50n seconds. Under such conditions, the Cu fuse provided in the semiconductor device can be cut by laser irradiation from the outside to switch the circuit, and the processed shape after cutting the fuse can be controlled.

  First, the cutting process of the Cu fuse will be described. FIG. 2 is a view showing the structure of the Cu fuse of the present invention. As shown in FIG. 2A, the Cu fuse 27 includes a Cu body 27a and a barrier layer 27b for preventing Cu diffusion to the surrounding interlayer insulating film 24. A material such as Ta or TaN is used for the barrier layer 27b. On the other hand, laser trimming lasers that are widely used nowadays are lasers with wavelengths near and below the band gap of Si in order to suppress damage to the Si substrate placed under the fuse. Specifically, a laser in the near infrared region (wavelength of about 1.0 μm to 1.4 μm) is used. FIG. 3 shows the light reflectance of Cu and TaN with respect to a laser having a wavelength in the near infrared region. As shown in FIG. 3, the near infrared region laser reflects 98% or more with respect to Cu and reflects about 60% to 70% with respect to TaN. Since there is almost no amount of penetration into Cu, when the laser is irradiated to the Cu fuse, the laser is absorbed by the barrier layers (TaN) on the side and bottom surfaces instead of Cu having high reflectivity. As a result, heat generated by light absorption from the side and bottom surfaces of the fuse heats the entire fuse, and after liquefaction and vaporization, when the pressure exceeds a certain level, the insulating layer on the fuse is destroyed and cut.

  Next, the place where light absorption is performed on the side and bottom of the fuse will be described. The laser irradiated from above the fuse is diffracted at the interface between the device surface and each insulating layer due to the difference in refractive index, and the light component that has traveled to the side surface and bottom surface of the fuse is absorbed. FIG. 5 is a view showing a distribution of light absorption on the side surface of the fuse when the laser is irradiated. FIG. 5A shows a case where a laser having a wavelength of 1.3 μm is irradiated, and an arrow indicates a point of light absorption. Similarly, FIG. 5B is a diagram showing a distribution of light absorption on the side surface of the fuse when a laser with a wavelength of 1.0 μm is irradiated, and an arrow indicates a point of light absorption. As shown in FIG. 5, the point of light absorption on the side surface of the fuse is periodically generated depending on the laser wavelength, and the point is denser in the short wavelength laser.

  FIG. 4 is a cross-sectional view of the fuse when there is an indication that a processing abnormality has occurred. FIG. 4 shows an example in which an FSG interlayer insulating film 142 and a Cu fuse 143 are formed on an etching stopper layer 141 made of SiCN, and the lower portion 143a of the Cu fuse 143 is melted and vaporized with heating. . As the thickness of the fuse increases, non-uniformity is likely to occur in the heating at the upper and lower portions of the fuse due to the effect of periodic light absorption on the side surfaces of the fuse, as described above. Particularly when the laser is focused on the Si substrate side from the device surface, only the lower part of the fuse is heated. If only the lower part of the fuse is heated while the upper part of the fuse remains in a solid state, only the lower part of the fuse is liquefied and vaporized, leading to an explosion, peeling off at a mechanically weak interface, and the explosion progresses from that part.

  As shown in FIG. 3, if the laser wavelength is 0.6 μm or more, the reflectivity to Cu is 90% or more and the reflectivity to TaN is about 50% or more. Absorption becomes dominant and, as described above, the fuse can be melted and cut. On the other hand, as shown in FIG. 5, light absorption into the fuse occurs periodically on the side surface of the fuse, and the point of light absorption depends on the wavelength of the laser due to the wave nature of the light, and periodically as the laser wavelength is shorter. The interval between the light absorption points generated is narrow, uniform light absorption is performed, the fuse can be heated uniformly, the light absorption non-uniformity at the top and bottom of the fuse is alleviated, and the shape of the fuse at the time of cutting is reduced Control becomes easy. From such a point, for cutting the Cu fuse, a laser having a wavelength of 1.3 μm or less is used, and a laser having a wavelength of 1.1 μm or less is preferable.

  However, by using a laser having a short wavelength, uniform light absorption can be performed and the shape abnormality can be effectively suppressed. However, when the laser wavelength is shortened, damage to the Si substrate under the fuse increases. From this viewpoint, the laser has a wavelength of 0.6 μm or more, and a laser with a wavelength of 1.0 μm or more is preferable. For example, if a fuse having a fuse width of 0.7 μm to 1.0 μm and a fuse film thickness of 1.0 μm to 1.4 μm is cut using a laser having a wavelength of 1.065 μm, the abnormal shape after cutting and under the fuse Damage to the Si substrate can be avoided. However, this value is only an example value, and appropriate processing can be performed by selecting the laser wavelength according to the Cu fuse width, fuse film thickness, fuse upper and lower insulation layer thickness, and material. Conditions can be obtained.

  FIG. 6 is a diagram showing the correlation between the laser light intensity and the irradiation time at the same output. FIG. 6 illustrates the case where the laser pulse irradiation time is 9 nsec and 21 nsec. The output is obtained by integrating the light intensity per unit time over time, so when the same output laser is irradiated, it is possible to heat for a long time with low light intensity by extending the pulse irradiation time. is there. As described above, the processing abnormality at the time of cutting the fuse is due to non-uniformity of heat. Therefore, by using a laser with a pulse width with a long irradiation time, heat non-uniformity during heating of the fuse can be avoided, and even if non-uniform heating occurs due to light absorption, non-uniformity due to heat conduction occurs. Uniformity can be relaxed.

  FIG. 7 is a graph showing the relationship between the incidence of shape abnormality during laser irradiation and the pulse irradiation time. FIG. 7 shows an example in which a fuse having a cut portion thickness of 1.0 μm to 1.4 μm and a cut portion width of 0.7 μm to 1.0 μm is cut. Under this condition, as shown in FIG. 7, by setting the pulse irradiation time to 9 nsec or longer, processing abnormality during laser irradiation can be suppressed. As a result of the same examination under other conditions, it is easy to cause damage to the underlying Si substrate when laser irradiation is performed for a long time with high intensity. Therefore, the laser pulse irradiation time is set to 9 nsec or more, and 15 n Seconds or more are preferred. On the other hand, if the pulse irradiation time is increased under the same output, the light intensity decreases and the fuse cutting time becomes longer. Therefore, the pulse irradiation time is set to 50 nsec or less, and preferably 25 nsec or less.

  Since the width of the laser to be used is preferably 0.6 μm to 1.2 μm at the cutting site of the fuse to be cut, a mode in which a laser having a beam diameter of 2.0 μm to 3.0 μm at the time of laser irradiation is narrowed down is used. Is preferred. In addition, when the distance between the fuses in parallel is 2 μm, it is preferable to use a laser irradiation apparatus having an alignment accuracy of about 0.2 μm.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  It can be widely used for semiconductor devices including a Cu fuse that is cut by laser irradiation.

It is a figure which shows the structure of the semiconductor device of this invention. It is a figure which shows the structure of Cu fuse of this invention. It is a figure which shows the light reflectivity of Cu and TaN. It is sectional drawing of a fuse when there exists an indication that a processing abnormality occurs. It is a figure which shows distribution of the light absorption to the fuse side surface when irradiated with a laser. It is a figure which shows the correlation with the light intensity of a laser and irradiation time with the same output. It is a figure which shows the relationship between the incidence rate of the shape abnormality at the time of laser irradiation, and pulse irradiation time. It is a figure which shows the relationship between the film thickness of Cu fuse, and the incidence rate of a shape abnormality. It is sectional drawing when the conventional semiconductor device is cut | disconnected. It is a top view of the fuse box of a semiconductor device. It is a figure which shows the state of Cu fuse after the cutting | disconnection by laser irradiation. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of this invention. FIG. 13 is a fragmentary cross-sectional view showing the manufacturing process following FIG. 12. FIG. 14 is a main part cross-sectional view showing the manufacturing process following FIG. 13; FIG. 15 is a main part cross-sectional view showing the manufacturing process following FIG. 14; FIG. 16 is a main part cross-sectional view showing the manufacturing process following FIG. 15; FIG. 17 is a main part cross-sectional view showing the manufacturing process following FIG. 16; FIG. 18 is an essential part cross-sectional view showing the manufacturing process following FIG. 17; It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of this invention. It is a figure which shows the structure of the semiconductor device of the other aspect of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor element, 2 Semiconductor substrate, 3 Via layer, 4, 4a Etching stopper layer, 5, 5a Wiring layer, 6 Cu fuse, 21 SiN layer, 22, 25 SiCN layer, 23 SiCO layer, 24 FSG layer, 26 TEOS layer 27a Cu body, 27b barrier layer.

Claims (9)

  A fuse cutting method for switching a circuit by cutting a Cu fuse provided in a semiconductor device by external laser irradiation, wherein the film thickness of the cut portion of the Cu fuse is 0.9 μm or more and is irradiated A fuse cutting method in which the laser wavelength is 0.6 μm to 1.3 μm, and the laser pulse irradiation time is 9 nsec to 50 nsec.   The method for cutting a fuse according to claim 1, wherein a width of a portion to be cut of the Cu fuse is 0.6 μm to 1.2 μm.   2. The method for cutting a fuse according to claim 1, wherein the Cu fuse has a thickness of a cut portion of 1.0 μm to 1.4 μm. One or more layers of global wiring having a semiconductor element formed on the main surface of the semiconductor substrate, one or more lower wiring layers formed on the semiconductor element, and Cu wiring formed on the lower wiring layer A semiconductor device comprising a layer,
The global wiring layer includes a via layer and a wiring layer formed on the via layer with an etching stopper layer interposed therebetween,
The wiring layer in the uppermost global wiring layer in the global wiring layer having the Cu wiring includes a Cu fuse that is cut by laser irradiation from the outside to switch a circuit, and a film of a portion where the Cu fuse is cut The thickness is 0.9 μm or more,
The etching stopper layer in the uppermost global wiring layer is a semiconductor device having a one-layer structure of SiN, a two-layer structure of SiCO and SiCN, or a two-layer structure of tetraethoxysilane and SiCN.   The semiconductor device according to claim 4, wherein the global wiring layer has an interlayer insulating film containing fluorinated silicate glass. A semiconductor device comprising a plurality of global wiring layers,
The material of the etching stopper layer in the top global wiring layer is
The semiconductor device according to claim 4, wherein the material of the etching stopper layer in the global wiring layer disposed under the uppermost global wiring layer and the material of the etching stopper layer in the lower wiring layer are different.   5. The etching stopper layer in the uppermost global wiring layer is provided with a plurality of global wiring layers, and the material of the etching stopper layer in the global wiring layer disposed below the uppermost global wiring layer is different. Semiconductor devices. Forming a semiconductor element on the main surface of the semiconductor substrate;
Forming a lower wiring layer on the semiconductor element;
Forming a single layer or a plurality of layers having a lower wiring layer and a barrier insulating layer, and then forming a one or a plurality of global wiring layers having a Cu wiring. ,
The step of forming the global wiring layer includes:
Forming a via layer;
Forming a wiring layer on the via layer with an etching stopper layer interposed therebetween,
The wiring layer in the uppermost global wiring layer in the global wiring layer having the Cu wiring is provided with a Cu fuse that is cut by laser irradiation from the outside to switch the circuit, and the film thickness of the portion where the Cu fuse is cut Is 0.9 μm or more,
The method of manufacturing a semiconductor device, wherein the etching stopper layer in the uppermost global wiring layer has a one-layer structure of SiN, a two-layer structure of SiCO and SiCN, or a two-layer structure of tetraethoxysilane and SiCN. Forming a semiconductor element on the main surface of the semiconductor substrate;
A lower wiring layer is formed on the semiconductor element, one or more layers having the lower wiring layer and the barrier insulating layer are formed, and then one or more global wiring layers having Cu wiring are formed. A method of manufacturing a semiconductor device comprising:
The step of forming the uppermost layer of the global wiring layer includes:
Forming a via layer having an etching stopper layer at the top;
Plasma treatment of the etching stopper layer in a He atmosphere;
Forming a wiring layer on the via layer,
The wiring layer in the uppermost global wiring layer in the global wiring layer having the Cu wiring is provided with a Cu fuse that is cut by laser irradiation from the outside to switch the circuit, and the film thickness of the portion where the Cu fuse is cut Is 0.9 μm or more,
The method of manufacturing a semiconductor device, wherein the etching stopper layer in the uppermost global wiring layer has a single-layer structure of SiCN.

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