JP2008108048A - Computer and method for updating firmware therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a computer in which firmware can be updated even if the computer does not support hardware for changing over a memory address allocated to a flash ROM, necessary for updating the firmware, and to provide an update method for the firmware. <P>SOLUTION: This computer has a primary ROM and a secondary ROM storing the firmware. In updating the firmware, new firmware supplied from the outside is temporarily written in the secondary ROM. When write of the new firmware into the secondary ROM is completed, the firmware held by the secondary ROM is copied to the primary ROM to change over the memory addresses allocated to the primary ROM and the secondary ROM. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a computer incorporating firmware and a method for updating the firmware.

  For example, a server device, which is a computer used in a backbone system, incorporates firmware, which is a program for controlling various types of installed hardware. The firmware is stored in a flash ROM (flash memory) or the like, which is a rewritable nonvolatile memory, and the contents are retained even when the server device is powered off.

  Usually, a flash ROM in which firmware is stored cannot be accessed from an operating system (OS) that operates on the server device. Therefore, the user of the server device cannot rewrite the firmware stored in the flash ROM using the operating system. Rewriting firmware is a dangerous task, and if the rewriting operation fails, the server device may become unbootable.

  In view of this, the above-described server apparatus and the like improve availability by providing a plurality of flash ROMs in which firmware is stored in order to avoid inability to start due to firmware update work. In such a configuration, when power is turned on or when a processor (CPU: Central Processing Unit) is reset, the firmware stored in any one of the plurality of flash ROMs is read and operated. When updating the firmware, for example, new firmware supplied from the outside via a network is stored in another flash ROM, and the flash ROM is accessed when the power is turned on or reset. Thus, the memory address assigned to each flash ROM is switched.

  FIG. 3 is a block diagram showing a configuration of a conventional server device.

  As shown in FIG. 3, the conventional server device includes a processor 301, a primary ROM 302 and a secondary ROM 303 in which firmware is stored, and a switching control circuit 304 for switching the allocation of memory addresses to the primary ROM 302 and the secondary ROM 303. It is a configuration. The server apparatus shown in FIG. 3 shows a configuration example including two flash ROMs (a primary ROM 302 and a secondary ROM 303) as flash ROMs for storing firmware. The primary ROM 302, the secondary ROM 303, and the processor 301 are connected via, for example, a bus.

  The conventional server apparatus shown in FIG. 3 operates with firmware stored in the flash ROM by assigning a 0 MB address to either the primary ROM 302 or the secondary ROM 303 by the switching control circuit 304. The 0 MB address indicates a memory address that the processor 301 accesses first when the server apparatus is powered on or when the processor 301 is reset.

  For example, when the memory capacity of the primary ROM 302 and the secondary ROM 303 is 2 M (mega) bytes, when the server device is turned on or the processor 301 is reset, the processor 301 first accesses the 2 MB memory area from the 0 MB address. Thus, the firmware stored in the primary ROM 302 or the secondary ROM 303 to which the 0 MB address is assigned is read, and the processing by the firmware is executed.

  For example, when the server device is operating with firmware stored in the primary ROM 302, the switching control circuit 304 assigns a 0 MB address to the primary ROM 302.

  On the other hand, when updating the firmware, the processor 301 stores new firmware supplied from outside via a network or the like in the secondary ROM 303, and switches the assignment of the 0 MB address from the primary ROM 302 to the secondary ROM 303 using the switching control circuit 304. That is, the switching control circuit 304 assigns a 0 MB address to the secondary ROM 303. At this time, the switching control circuit 304 does not assign a 0 MB address to the primary ROM 302 and the secondary ROM 303 at the same time.

  Thereafter, by resetting the processor 301, the processor 301 reads the firmware stored in the secondary ROM 303 and executes processing by the firmware.

  Patent Document 1 discloses a non-volatile memory composed of a plurality of banks for storing programs and data received from a host computer, and a bank for switching between the non-volatile memory banks for storing the received programs and data. A configuration including a switching control unit is described.

  Further, Patent Document 2 includes a configuration including two flash ROMs that store the BIOS of the computer and a BIOS selection module that selects one of the BIOSs stored in the two flash ROMs when the computer is started up. Are listed.

In the configurations described in Patent Document 1 and Patent Document 2, the memory area that is accessed by the processor when the apparatus is activated is switched by hardware (a bank switching control unit and a BIOS selection module).
JP 2001-334056 A JP 2003-316582 A

  As described above, in the conventional server device, hardware for switching memory addresses assigned to a plurality of flash ROMs in which firmware is stored is necessary to update the firmware.

  However, some server devices do not support such hardware for reasons such as cost reduction. In that case, the server device cannot operate with the new firmware.

  The present invention has been made to solve the above-described problems of the prior art, and even when the hardware for switching the memory address assigned to the flash ROM necessary for firmware update is not supported. An object of the present invention is to provide a computer capable of updating firmware and a method for updating the firmware.

To achieve the above object, a computer according to the present invention includes a processor that executes processing according to a program,
A primary ROM, which is a rewritable nonvolatile memory, storing firmware executed by the processor;
A secondary ROM that is a rewritable nonvolatile memory that temporarily holds new firmware supplied from the outside when the firmware is updated,
Have
The processor is
At the time of updating the firmware, when writing of the new firmware to the secondary ROM is completed, the firmware held in the secondary ROM is copied to the primary ROM.

On the other hand, the firmware update method of the present invention is an update method for updating the firmware of a computer having a primary ROM and a secondary ROM which are rewritable nonvolatile memories in which the firmware is stored,
Processor
When the firmware is updated, new firmware supplied from the outside is temporarily written in the secondary ROM,
When the writing of the new firmware to the secondary ROM is completed, the firmware held in the secondary ROM is copied to the primary ROM,
In this method, processing is executed in accordance with firmware stored in the primary ROM.

  The above-described computer and its firmware update method include a primary ROM and a secondary ROM in which firmware is stored. When updating the firmware, new firmware supplied from the outside is temporarily written in the secondary ROM, and the secondary ROM is updated. When the writing of the new firmware is completed, the firmware stored in the secondary ROM is copied to the primary ROM, so that the firmware can be downloaded even if the hardware for switching the memory address assigned to the primary ROM and the secondary ROM is not supported. It becomes possible to update.

  In addition, since the first storage destination of new firmware supplied from the outside is the secondary ROM, when new firmware is supplied from the outside via a network or the like, even if a network failure or the like occurs during storage, the primary ROM The content is not affected at all.

  According to the present invention, it is possible to update firmware even in a configuration in which hardware for switching memory addresses assigned to a primary ROM and a secondary ROM is not supported.

  In addition, since the first storage destination of new firmware supplied from the outside is the secondary ROM, when new firmware is supplied from the outside via a network or the like, even if a network failure or the like occurs during storage, the primary ROM The content is not affected at all. Therefore, the availability of firmware update work for network failures and the like is improved.

  Next, the present invention will be described with reference to the drawings.

  In the following description, a server device, which is a computer used in a backbone system, will be described as an example. However, the present invention includes two flash ROMs in which firmware is stored, and hardware for switching memory addresses assigned to them. If it is a structure which does not have PC, it is applicable also to various apparatuses provided with a processor like a personal computer, a mobile telephone, or PDA (Personal Digital Assistants).

  FIG. 1 is a block diagram showing an example of the configuration of the server device of the present invention.

  As shown in FIG. 1, the server device of the present invention includes a processor 101 and a primary ROM 102 and a secondary ROM 103 in which firmware is stored. A flash ROM is used as the primary ROM 102 and the secondary ROM 103. The server device according to the present invention has a configuration that does not have the switching control circuit 304 for switching the memory address assigned to the primary ROM 302 and the secondary ROM 303 shown in FIG. The primary ROM 102, the secondary ROM 103, and the processor 101 are connected via, for example, a bus.

  In the server apparatus of the present invention, when the power is turned on or the processor 101 is reset, the processor 101 always operates with the firmware stored in the primary ROM 102 by accessing the primary ROM 102 first. When updating the firmware, the new firmware is temporarily stored in the secondary ROM 103, and then the firmware is copied to the primary ROM 102. That is, in the server device of the present invention, the secondary ROM 103 is used as a buffer for temporarily storing new firmware.

  As shown in FIG. 1, the primary ROM 102 includes a boot loader unit 104 and a main body unit 105, and the secondary ROM 103 includes a boot loader unit 106 and a main body unit 107.

  The boot loader unit 104 included in the primary ROM 102 and the boot loader unit 106 included in the secondary ROM 103 store instruction code groups (programs) that are executed first when the server apparatus is powered on or when the processor 101 is reset. The programs of the boot loader units 104 and 106 are written at the time of factory shipment, for example, and are not rewritten thereafter. It should be noted that different programs may be written in the boot loader units 104 and 106 according to differences in firmware update processing to be described later, or the same program that implements all the update processing may be written.

  The main body 105 provided in the primary ROM 102 and the main body 107 provided in the secondary ROM 103 store a firmware main body that is a program for actually controlling various hardware (not shown) provided in the server device. Here, the programs stored in the boot loader unit 104 and the main unit 105 are collectively referred to as firmware. Similarly, the programs stored in the boot loader unit 106 and the main unit 107 are collectively referred to as firmware.

  For example, when the memory capacity of the primary ROM 102 and the secondary ROM 103 is 2 Mbytes, in the present invention, the above-described 0 MB address is assigned in advance to the primary ROM 102, and the 4 MB address is assigned in advance to the secondary ROM 103. Here, the 4 MB address assigned to the secondary ROM 103 indicates a memory address that is 4 M bytes away from the 0 MB address. The memory address assigned to the secondary ROM 103 does not need to be a 4 MB address, and may be any value as long as it is sufficiently away from the memory area assigned to the primary ROM 102.

  As described above, the server device of the present invention always operates with the firmware stored in the primary ROM 102 when the processor 101 accesses the 2 MB memory area from the 0 MB address when the power is turned on or reset. For example, since the 4 MB address is assigned to the secondary ROM 103, the processor 101 is not operated by the firmware held in the secondary ROM 103.

  Next, the operation of the server apparatus of the present invention shown in FIG. 1 will be described with reference to FIG.

  FIG. 2 is a flowchart showing a firmware update process by the server device of the present invention.

  As described above, in the server device of the present invention, since the 0 MB address is assigned to the primary ROM 102, the processor 101 first accesses the boot loader unit 104 of the primary ROM 102 when the server device is turned on or the processor 101 is reset. Then, it operates according to the program stored in the boot loader unit 104.

  During normal operation, the processor 101 reads the firmware body from the main body unit 105 according to a program stored in the boot loader unit 104 of the primary ROM 102, and executes processing according to the read firmware body. At this time, the processor 101 does not operate with the firmware stored in the secondary ROM 103.

  When updating the firmware stored in the primary ROM 102, the processor 101 uses the function of the firmware main body stored in the main body portion 105 of the primary ROM 102, for example, to update the new firmware supplied from the outside via the network or the like to the secondary ROM 103. (Step S1). At this time, the processor 101 rewrites only the content of the main body 107 of the secondary ROM 103 and does not rewrite the content of the boot loader unit 106. Note that the new firmware body is different in version from the existing firmware body that has been executed so far.

  When the writing of new firmware to the main body 107 of the secondary ROM 103 is completed, the processor 101 performs a soft reset using the function of the firmware main body stored in the main body 105 of the primary ROM 102 (step S2).

  After the soft reset, the processor 101 executes the program stored in the boot loader unit 104 of the primary ROM 102 (step S3), and is stored in the firmware main unit stored in the main unit 105 of the primary ROM 102 and the main unit 107 of the secondary ROM 103. The firmware main body versions are compared (step S4).

  Here, since the versions of the two firmware main bodies do not match, the processor 101 reads the program stored in the boot loader unit 106 of the secondary ROM 103 (step S5), and the contents of the main unit 107 of the secondary ROM 103 are primary according to the program. Copy to the main body 105 of the ROM 102 (step S6).

  When the firmware duplication work is completed, the processor 101 performs a soft reset using the function of the firmware main body stored in the main body 105 of the primary ROM 102 (step S2).

  After the soft reset, the processor 101 executes the program stored in the boot loader unit 104 of the primary ROM 102 again (step S3), and is stored in the firmware main unit stored in the main unit 104 of the primary ROM 102 and the main unit 107 of the secondary ROM 103. The firmware main body versions are compared (step S4).

  Here, since the versions of the two firmware bodies match, the processor 101 reads the firmware body stored in the body unit 105 of the primary ROM 102 (step S7), and executes processing according to the firmware body. With the above processing procedure, the firmware can be updated without the hardware for switching the memory addresses assigned to the primary ROM 102 and the secondary ROM 103.

  According to the present invention, the hardware for switching the memory addresses assigned to the primary ROM 102 and the secondary ROM 103 by using the secondary ROM 103 as a buffer for temporarily holding new firmware supplied from outside via, for example, a network or the like. The firmware can be updated even in configurations where the hardware is not supported.

  In addition, since the first storage destination of new firmware supplied from the outside is the secondary ROM 103, when new firmware is supplied from the outside via a network or the like, even if a network failure or the like occurs during storage, the primary ROM The content is not affected at all. Therefore, the availability of firmware update work for network failures and the like is improved.

  Further, when updating the firmware, only the firmware main body held in the main body portion of the secondary ROM 103 is copied to the main body portion 105 of the primary ROM 102. Therefore, even if a power failure or the like occurs in the server device during the copying, Since the boot loader unit 104 of the primary ROM 102 is not subject to replication, the contents of the boot loader unit 104 are not affected. Therefore, the processor 101 starts processing again from the program of the boot loader unit 104 of the primary ROM 102, and copies new firmware from the secondary ROM 103 to the primary ROM 102 in the above-described procedure. Therefore, the availability of firmware update work for a power failure or the like is improved.

  Furthermore, in the present invention, since the processor 101 always operates with the firmware stored in the primary ROM 102, it is not necessary to hold different firmware in a plurality of flash ROMs as in the prior art.

It is a block diagram which shows one structural example of the server apparatus of this invention. It is a flowchart which shows the update operation | movement of the firmware by the server apparatus of this invention. It is a block diagram which shows the structure of the conventional server apparatus.

Explanation of symbols

101 Processor 102 Primary ROM
103 Secondary ROM
104, 106 Boot loader unit 105, 107 Main unit

Claims (6)

A processor that executes processing according to a program;
A primary ROM, which is a rewritable nonvolatile memory, storing firmware executed by the processor;
A secondary ROM that is a rewritable nonvolatile memory that temporarily holds new firmware supplied from the outside when the firmware is updated,
Have
The processor is
A computer that copies the firmware held in the secondary ROM to the primary ROM when writing of new firmware to the secondary ROM is completed when the firmware is updated. The primary ROM and the secondary ROM are:
A boot loader unit that stores a program that is first executed by the processor when the computer is turned on or the processor is reset, and a firmware main body that is a program for actually controlling various hardware installed in the computer It has a main body to be stored,
The processor is
The computer according to claim 1, wherein when updating the firmware, only the firmware main body held in the main body of the secondary ROM is copied to the main body of the primary ROM.   The computer according to claim 2, further comprising a program for copying the firmware held in the secondary ROM to the primary ROM when the firmware is updated. An update method for updating the firmware of a computer having a primary ROM and a secondary ROM which are rewritable nonvolatile memories in which firmware is stored,
Processor
When the firmware is updated, new firmware supplied from the outside is temporarily written in the secondary ROM,
When the writing of the new firmware to the secondary ROM is completed, the firmware held in the secondary ROM is copied to the primary ROM,
A firmware update method for executing processing according to firmware stored in the primary ROM. In the primary ROM and the secondary ROM,
A boot loader unit that stores a program that is first executed by the processor when the computer is turned on or the processor is reset, and firmware that is a program for actually controlling various hardware installed in the computer It has a main body that stores the main body,
The processor is
5. The firmware updating method according to claim 4, wherein when updating the firmware, only the firmware main body held in the main body of the secondary ROM is copied to the main body of the primary ROM.   The firmware update method according to claim 5, wherein a program for copying firmware held in the secondary ROM to the primary ROM is held in the boot loader unit.

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