JP2008103394A - Electronic substrate manufacturing method, electronic substrate, and electronic device - Google Patents

Abstract

A semiconductor chip manufacturing method capable of easily manufacturing an inductor element in which a closed magnetic circuit is formed is provided.
A redistribution wiring of a connection terminal of an electronic circuit and an inductor element having a ring-shaped core and a spiral winding are formed. The core comprises a second magnetic layer, and the winding is wound. 41. A method of manufacturing a semiconductor chip 1 in which resin layers 37 and 38 are formed in a gap 41, and the periphery of the inductor element 40 is covered with magnetic layers 35, 31, and 36. Desirably, at least a portion of the line 41 is formed.
[Selection] Figure 2

Description

  The present invention relates to an electronic substrate manufacturing method, an electronic substrate, and an electronic device.

Electronic devices such as mobile phones and personal computers are equipped with semiconductor chips (electronic substrates) on which electronic circuits are formed. This semiconductor chip may be used together with passive elements such as resistors, inductors and capacitors. Thus, a technique for forming a spiral inductor on a semiconductor chip has been proposed (see, for example, Patent Document 1 or Patent Document 2). A spiral inductor has a spiral winding formed on an active surface.
JP 2002-164468 A JP 2003-347410 A Ermolov et al, “Microreplicated RF Toroidal Inductor”, IEEE Transactions on Microwave Theory and Techniques, Vol. 52, no. 1, January 2004, p29-36

  However, in a spiral inductor, leakage current is generated due to magnetic flux interference with silicon constituting a semiconductor chip, and thus there is a limit to improvement in Q value (ratio of inductance and resistance value).

  In order to solve this problem, a technique for forming a toroidal inductor element on a semiconductor chip has been proposed (see, for example, Non-Patent Document 1). In the toroidal inductor element, a spiral winding is formed around a ring-shaped core disposed in parallel with an active surface. However, in this technique, since the toroidal inductor element is formed using a MEMS (Micro Electro Mechanical Systems) technique or a transfer technique, there is a problem that a special process using a mold or the like is required.

  The present invention has been made in order to solve the above-described problems, and it is possible to easily manufacture an inductor element and to secure a Q value of the inductor, and to form an electronic substrate. The purpose is to provide an electronic substrate. It is another object of the present invention to provide an electronic device having excellent electrical characteristics at low cost.

In order to achieve the above object, an electronic substrate manufacturing method according to the present invention includes a rearrangement wiring of a connection terminal of an electronic circuit, a toroidal inductor element including a ring-shaped core and a spiral winding, A method for manufacturing an electronic substrate, wherein a core is made of a magnetic material, a gap between the windings is filled with a non-magnetic material, and a periphery of the toroidal inductor element is covered with a magnetic material, wherein the relocation wiring is formed And forming at least a part of the winding.
A method of manufacturing an electronic substrate, wherein a rearrangement wiring of a connection terminal of an electronic circuit and a toroidal inductor element having a ring-shaped core and a spiral winding are formed on a surface, Forming a first magnetic layer made of a magnetic material, a step of forming a plurality of first wirings on the first magnetic layer, and a first non-magnetic material made of a nonmagnetic material in a gap between the adjacent first wirings. A step of forming a magnetic layer, a step of forming a second magnetic layer made of a magnetic material so as to cover the central portions of the plurality of first wirings, and a plurality of first layers crossing the surface of the second magnetic layer. A step of forming two wirings, a step of forming a second nonmagnetic layer made of a nonmagnetic material in a gap between the adjacent second wirings, and a third magnetic material made of a magnetic material so as to cover the plurality of second wirings Forming a layer, and including the second wiring In the forming step, the rearrangement wiring is formed at the same time as the second wiring, and the second wiring is connected in order to sequentially connect the end of one first wiring and the end of the other first wiring. It is desirable to form the toroidal inductor element provided with the spiral winding composed of the first wiring and the second wiring.
According to this configuration, a toroidal inductor element having a closed time path can be formed easily and at a low cost without extremely increasing the number of processes and without requiring special equipment such as a mold.

It is desirable to have a step of forming a nonmagnetic layer made of a nonmagnetic material around the central axis of the ring-shaped core.
According to this configuration, the magnetic lines of force can be concentrated on each of the magnetic layers covering the toroidal inductor element outside the nonmagnetic layer, so that a toroidal inductor element having a high inductance value and Q value can be formed.

The electronic substrate includes a stress relaxation layer for relaxing a stress difference between the electronic substrate and the counterpart member between the connection terminal used for connection with the counterpart member and the electronic substrate, and the stress relaxation. In the step of forming the layer, it is desirable to form the nonmagnetic layer.
According to this configuration, by simultaneously forming the stress relaxation layer and the nonmagnetic layer, the manufacturing process can be simplified and the manufacturing cost can be reduced.

It is desirable to have a step of trimming a part of the winding to adjust the characteristics of the toroidal inductor element.
According to this configuration, a toroidal inductor element having desired characteristics can be formed.

On the other hand, an electronic substrate according to the present invention is manufactured using the above-described electronic substrate manufacturing method.
According to this configuration, it is possible to provide an electronic substrate on which a low-cost, high-Q-value toroidal inductor element is formed.

On the other hand, a relocation wiring of a connection terminal of an electronic circuit, a toroidal inductor element having a ring-shaped core and a spiral winding, the core is made of a magnetic material, and a non-magnetic material is formed in a gap between the windings In which the periphery of the toroidal inductor element is covered with a magnetic material, and at least part of the winding is made of the same material as the relocation wiring. And
According to this configuration, the magnetic core is filled with the magnetic material around the core and the periphery of the toroidal inductor element, so that the magnetic flux density can be increased, and the inductance value and Q value of the toroidal inductor element are improved. Can be made. Therefore, the electrical characteristics of the electronic substrate can be improved.
Further, since the non-magnetic material is filled in the gap between the adjacent windings of the toroidal inductor element, it is possible to suppress the lines of magnetic force from being canceled by the gap between the windings, and to concentrate the lines of magnetic force inside the magnetic material.
Furthermore, since at least a part of the winding is made of the same material as the rearrangement wiring, the winding and the rearrangement wiring can be formed at the same time, thereby simplifying the manufacturing process and reducing the manufacturing cost. it can.

The ring in the toroidal inductor element includes a stress relaxation layer that relaxes a stress difference between the electronic substrate and the counterpart member between a connection terminal used for connection with the counterpart member and the electronic substrate. Preferably, a nonmagnetic layer made of a nonmagnetic material is formed around the central axis of the core, and the nonmagnetic layer is made of the same material as the stress relaxation layer.
According to this configuration, the magnetic lines of force can be more concentrated on each magnetic layer covering the toroidal inductor element outside the nonmagnetic layer. Further, since the nonmagnetic layer is made of the same material as the stress relaxation layer, the nonmagnetic layer and the stress relaxation layer can be formed at the same time, and the manufacturing process can be simplified and the manufacturing cost can be reduced.

The space between the windings is preferably formed to have a substantially constant width.
According to this configuration, the ratio of L / S (Line and Space) of the winding increases, and the wiring resistance can be reduced.

Further, it is desirable that a conductive layer is formed between the electronic circuit and the toroidal inductor element.
According to this configuration, the influence (coupling) of the magnetic field of the inductor on the electronic circuit can be reduced due to the electromagnetic shielding effect.

On the other hand, an electronic apparatus according to the present invention includes the above-described electronic substrate.
According to this configuration, since the electronic substrate on which the low-cost and high-Q-value toroidal inductor elements are formed is provided, it is possible to provide an electronic device having excellent electrical characteristics at low cost.

Embodiments of the present invention will be described below with reference to the drawings. In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.
(First embodiment)
In the semiconductor chip (electronic substrate) according to the first embodiment, an inductor element (toroidal inductor element) is formed by using a rearrangement wiring and a process of forming a stress relaxation layer. First, the rearrangement wiring of the connection terminals and the stress relaxation layer will be described. Hereinafter, the electronic substrate will be described by taking an example of an inductor element formed on a semiconductor chip (particularly on the active element forming surface side), but the electronic substrate may be the side opposite to the active element forming surface of the semiconductor chip, or the semiconductor Any substrate may be used as long as it is at least a surface insulating substrate such as a silicon substrate, a glass substrate, a quartz substrate, or a quartz substrate on which no element is formed.

(Relocation wiring)
FIG. 1 is an explanatory diagram of rearrangement wiring, FIG. 1 (a) is a plan view of a semiconductor chip, and FIG. 1 (b) is a side sectional view taken along line BB in FIG. 1 (a). In FIG. 1, descriptions of a solder resist and a heat radiating member, each resin layer, a central resin layer, a first magnetic layer, and a third magnetic layer which will be described later are omitted. As shown in FIG. 1B, a passivation film 8 for protecting the electronic circuit is formed on the surface of the semiconductor chip 1 on which the electronic circuit is formed. An electrode 62 for electrically connecting the electronic circuit to the outside is formed on the surface of the semiconductor chip 1. An opening of the passivation film 8 is formed on the surface of the electrode 62.

  As shown in FIG. 1A, a plurality of electrodes 62 are aligned along the peripheral edge of the semiconductor chip 1. Due to the recent miniaturization of the semiconductor chip 1, the pitch between the adjacent electrodes 62 has become very narrow. When this semiconductor chip 1 is mounted on the counterpart substrate, a short circuit may occur between the adjacent electrodes 62. Therefore, in order to widen the pitch between the electrodes 62, a rearrangement wiring 64 for the electrodes 62 is formed.

  Specifically, a plurality of connection terminals 63 are arranged in a matrix at the center of the surface of the semiconductor chip 1. A rearrangement wiring 64 drawn from the electrode 62 is connected to the connection terminal 63. As a result, the narrow-pitch electrodes 62 are drawn out to the central portion to widen the pitch. For the formation of such a semiconductor chip 1, W-CSP (Wafer Level Chip Scale Package) technology in which rearrangement wiring and resin sealing are collectively performed in a wafer state and then separated into individual semiconductor chips 1 is performed. It's being used.

  When forming the semiconductor chip 1 using this W-CSP technology, it is necessary to relieve the stress caused by the difference in thermal expansion coefficient between the counterpart substrate on which the semiconductor chip 1 is mounted and the semiconductor chip 1. Therefore, as shown in FIG. 1B, a stress relaxation layer 30 made of a photosensitive resin such as photosensitive polyimide, BCB (benzocyclobutene), or phenol novolac resin is formed in a region where an inductor element 40 described later of the semiconductor chip 1 is formed. It is formed on the surface other than. The connection terminal 63 described above is formed on the surface of the stress relaxation layer 30.

  Bumps 78 are formed on the surface of the connection terminal 63. The bumps 78 are, for example, solder bumps, and are formed by a printing method or the like. The bumps 78 are mounted on the connection terminals of the counterpart substrate by reflow, FCB (Flip Chip Bonding), or the like. It is also possible to mount the connection terminal 63 of the semiconductor chip 1 on the connection terminal of the counterpart substrate via an anisotropic conductive film or the like.

(Toroidal inductor element)
A semiconductor chip 1 shown in FIG. 1A includes an inductor element 40 (toroidal inductor element) on the surface.
FIG. 2 is an explanatory diagram of the inductor element, FIG. 2 (a) is a plan view, and FIG. 2 (b) is a side cross-sectional view taken along line CC in FIG. 2 (a). In FIG. 2A, descriptions of a solder resist and a heat radiating member, which will be described later, are omitted. As shown in FIG. 2A, the inductor element 40 includes a ring-shaped core 42 formed by the second magnetic layer 31, and a spiral winding 41 formed around the core 42. ing. The winding 41 is constituted by the first wiring 12 disposed on the back surface of the second magnetic layer 31 and the second wiring 22 disposed on the surface of the second magnetic layer 31.

As shown in FIG. 2B, a first magnetic layer 35 made of a magnetic material is formed in the vicinity of the region where the inductor element 40 is formed.
By adopting ferrite as the magnetic material, the magnetic material can be introduced at a low cost. Ferrite is a general term for complex oxides composed mainly of Fe2O3 and divalent metal oxides. As will be described later, ferrite can be obtained by oxidizing Fe, which is a first metal, and Mn, Co, Ni, etc., which are second metals. Spinel type ferrite (MFe2O4) is a soft magnetic material, magnetoplumbite type ferrite (MFe12O19) is a permanent magnet, and garnet type ferrite (MFe5O12; M = Y, Sm, Gd, Dy, Ho, Er, Yb) is a micro material. Used as a wave material for circulators, isolators and the like. Since ferrite is an oxide and has an insulating surface, a coil pattern to be described later can be formed immediately above. When the first magnetic layer 35 is formed of a magnetic metal layer such as iron, it is preferable to perform an insulating process such as oxidizing the surface or depositing an insulating resin. Further, the magnetic layer may be an amorphous metal layer having a high magnetic permeability represented by an Fe-based material.

A first wiring 12 is formed on the first magnetic layer 35.
The first wiring 12 includes copper (Cu), gold (Au), silver (Ag), titanium (Ti), tungsten (W), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), nickel It is made of a conductive material such as vanadium (NiV), chromium (Cr), aluminum (Al), or palladium (Pd). It should be noted that the constituent material of the first wiring 12 can be appropriately selected according to characteristics such as a resistance range necessary for the winding of the inductor element and an allowable current value. In the case where the first wiring 12 is formed by electrolytic plating, the first wiring 12 is formed on the surface of the underlayer, but the description of the underlayer is omitted in FIG.

  As shown in FIG. 2A, the first wiring 12 is patterned in a substantially trapezoidal shape, and a plurality of first wirings 12 are arranged radially on the same circumference. The space between the adjacent first wirings 12 is desirably formed with a constant width near the resolution limit of photolithography. Thereby, the ratio of L / S (Line and Space) of the first wiring 12 is increased, and the wiring resistance can be reduced. One of the plurality of first wirings 12 is connected to the electrode 11 via the connection wiring 12a.

  Here, a nonmagnetic material layer is formed in the space between the adjacent first wirings 12. As the nonmagnetic material layer, a first resin layer 37 made of a photosensitive resin such as acrylic resin, photosensitive polyimide, BCB (benzocyclobutene), or phenol novolac resin is formed. The first resin layer 37 is patterned by photolithography, and is formed in the same thickness as the first wiring 12 in the space between the adjacent first wirings 12 on the surface of the first magnetic layer 35.

A second magnetic layer 31 made of the same magnetic material as that of the first magnetic layer 35 is formed in substantially the same shape as the first magnetic layer 35 in plan view so as to cover the first wiring 12. An inner through hole (via) 33 and an outer through hole 34 are formed in the second magnetic layer 31. The inner through hole 33 is formed so that the inner end portion of the first wiring 12 is exposed, and a plurality of inner through holes 33 are arranged on the same circumference. The outer through hole 34 is formed so that the outer end of the first wiring 12 is exposed, and a plurality of outer through holes 34 are arranged on the same circumference. Thus, the second magnetic layer 31 is continuously formed so as to cover the central portion of the plurality of first wirings 12.
In addition, what is necessary is just to form the opening shape of the inner side through-hole 33 and the outer side through-hole 34 in a fan shape, a rectangle, an ellipse, an ellipse etc. Alternatively, a plurality of inner through holes 33 and / or a plurality of outer through holes 34 may be connected to form a ring-shaped through hole.

  As shown in FIG. 2B, the second wiring 22 is formed on the surface of the second magnetic layer 31. The second wiring 22 is also formed of the same conductive material as the first wiring 12. The second wiring 22 is also filled inside the inner through hole 33 and the outer through hole 34 and is connected to the first wiring 12.

  As shown in FIG. 2A, the second wiring 22 is formed on the inner through hole 33 formed on one of the adjacent first wirings 12 and on the other first wiring. The outer through-hole 34 is patterned. That is, the second wiring 22 is formed so as to cross the second magnetic layer 31. As in the case of the first wiring 12, it is desirable that the space between the adjacent second wirings 22 is formed to have a constant width near the resolution limit of photolithography. One of the plurality of second wirings 22 is connected to another electrode 21 through a connection wiring 22a. In the present embodiment, the example in which the inductor element 40 is inserted between the electrodes 11 and 21 has been described. However, the insertion place is between the electrode and the external terminal, between the external terminal and the external terminal, or on other electronic substrates. Various modifications can be made to the connection destination such as between built-in passive components. This is the same in all embodiments described later.

  In this way, the first wiring 12 and the second wiring 22 are sequentially connected to form a spiral winding 41. Since ferrite is an electrically insulating material having a high resistivity, the first wiring 12 and the second wiring 22 can be formed adjacent to the ferrite. A ring-shaped core 42 is constituted by the second magnetic layer 31 inside the winding 41. The inductor 41 is configured by the winding wire 41 and the core 42. As described above, the inductor element 40 having the ring-shaped core is more efficient than the inductor element having the linear core because the magnetic flux forms a closed loop.

  By configuring the core 42 of the inductor element 40 with a magnetic material, the magnetic flux density can be increased, and the L value (inductance) and Q value of the inductor element 40 can be remarkably improved. As a result, the inductor element 40 of the present embodiment can function as a choke coil or the like of the power supply circuit.

  Here, a nonmagnetic material layer is also formed in a space between the adjacent second wirings 22. As the nonmagnetic material layer, a second resin layer 38 made of a photosensitive resin such as acrylic resin, photosensitive polyimide, BCB (benzocyclobutene), or phenol novolac resin is formed. As shown in FIG. 2B, the second resin layer 38 is patterned by a photolithography method or the like, and the same as the second wiring 22 in the space between the adjacent second wirings 22 on the surface of the second magnetic layer 31. It is formed with a film thickness.

  A third magnetic layer 36 made of the same magnetic material as the first magnetic layer 35 is formed so as to cover the second wiring 22 and the second resin layer 38. The third magnetic layer 36 is formed in substantially the same shape as the second magnetic layer 31 described above in plan view.

FIG. 3 is a side sectional view of a portion corresponding to the line FF in FIG.
As shown in FIG. 3, the inductor element 40 on the semiconductor chip 1 is surrounded by the magnetic layers 35, 31, and 36 to form a closed magnetic path shielded from the outside. For this reason, a magnetic field 100 generated in a direction perpendicular to the paper surface of FIG. 3 due to a current flowing through the inductor element 40 (a two-dot chain line arrow in FIG. 3) mainly passes through the magnetic layers 35, 31, and 36 having a high magnetic permeability. Pass through.

  In such a closed magnetic circuit type, since the magnetic flux generated by the inductor element 40 mainly passes through the magnetic layers 35, 31, and 36 having high magnetic permeability, the open magnetic circuit that does not shield the periphery of the inductor element 40. Less magnetic flux leakage to the outside than type. Therefore, it is possible to prevent a leakage current generated due to interference with a peripheral member in contact with the inductor element 40. Further, the magnetic flux density can be further increased, and higher L value (inductance) and Q value can be obtained.

  In addition, since the resin layers 37 and 38 are formed in the space between the adjacent wirings of the first wiring 11 and the second wiring 22, the lines of magnetic force are offset by the space between the wirings of the first wiring 11 and the second wiring 22. This can be suppressed and the lines of magnetic force can be concentrated inside the magnetic layers 35, 31 and 36.

  Further, as shown in FIG. 3, a hole 51 for exposing the passivation film 8 is formed around the central axis C of the ring-shaped core 42 and inside the region where the winding 41 is formed. A nonmagnetic material layer is formed in the hole 51. As the nonmagnetic material layer, a central resin layer 50 made of a photosensitive resin such as acrylic resin, photosensitive polyimide, BCB (benzocyclobutene), or phenol novolac resin is formed. The central resin layer 50 is formed with the same thickness as the magnetic layers 35, 31, and 36 described above.

  Thus, since the central resin layer 50 is formed inside the winding 41 of the inductor element 40, the magnetic layers 35 and 31 covering the winding 41 without diffusing the magnetic flux generated in the inductor element 40. , 36 can be concentrated inside. Therefore, the magnetic flux density can be increased, and higher L value (inductance) and Q value can be obtained.

(First modification)
FIG. 4 is a plan view of a first modification of the first embodiment. In the first modification, one second wiring 22 is connected to a connection terminal 26 formed on the stress relaxation layer 30 through a connection wiring 22a. A bump 28 is formed on the surface of the connection terminal 26 so that it can be mounted on the counterpart substrate. Therefore, according to the first modification, the inductor element 40 can be disposed between the electronic circuit of the semiconductor chip 1 and the counterpart substrate. The connection terminal 26 may be formed on the magnetic layer.

(Second modification)
FIG. 5 is a side sectional view of a second modification of the first embodiment. In the second modification, a conductive layer (shield layer) 7 is formed on substantially the entire back surface of the passivation film 8. The conductive layer 7 can be formed of Al or the like using an electronic circuit formation process. If the conductive layer 7 is held at ground or at a constant potential, the influence (coupling) of the magnetic field of the inductor element 40 (toroidal inductor element) on the electronic circuit including the active element of the semiconductor chip 1 is reduced by the electromagnetic shielding effect. be able to. The conductive layer 7 may be formed at any position between the inductor element 40 and the electronic circuit. Further, the conductive layer 7 may be formed at least in the region where the inductor element 40 is formed, even though it is not formed on the substantially entire surface of the semiconductor chip 1. Furthermore, other passive components (inductors, capacitors, resistors) are integrated on the same plane as the inductor element 40 forming layer, or further provided with an insulating layer, a dielectric layer and a conductive layer above or below the inductor element 40 forming layer. You may do it. By doing so, the degree of integration of components can be further improved.

(Electronic substrate manufacturing method)
Next, the semiconductor chip manufacturing method described above will be described with reference to FIGS.
6 to 8 are process diagrams of the semiconductor chip manufacturing method according to the present embodiment. Here, as shown in FIG. 6A, a passivation film 8 for protecting the electronic circuit and a connection for electrically connecting the electronic circuit to the outside are provided on the surface of the semiconductor chip 1 on which the electronic circuit is formed. Description will be made from a state in which the terminal 11 is formed and the opening of the passivation film 8 is formed on the surface of the connection terminal 11.

First, as shown in FIG. 6A, the first magnetic layer 35 is formed on the semiconductor chip 1.
Here, a method for forming the first magnetic layer 35 made of ferrite will be described as an example.
First, a metal film is formed on the entire surface of the semiconductor chip 1. This metal film is composed of Fe as the first metal and Mn, Co, Ni, or the like as the second metal. The metal film can be formed using an electrolytic plating method or an electroless plating method. If the first metal and the second metal are deposited at the same time, it is possible to form a mixed metal film. If the first metal and the second metal are alternately deposited, the first metal and the second metal are deposited. It is possible to form a metal film in which two metals are alternately stacked. The ratio between the first metal and the second metal may be 1: 1, for example. In addition, as a 2nd metal, you may employ | adopt not only one type of metals among Mn, Co, Ni etc. but 2 or more types of metals.

  Next, the metal film is oxidized. The oxidation of the metal film can be performed by holding the semiconductor chip 1 in an atmosphere of oxygen gas or the like, and by heating the semiconductor chip 1 in an oxidizer liquid such as potassium dichromate. It is also possible to do this. By these treatments, the first metal and the second metal constituting the metal film are both oxidized to form ferrite. If these processes are repeated, an arbitrary thickness of ferrite is formed.

  It is also possible to adopt a recently developed ferrite plating method as a method for forming ferrite. The ferrite plating method is a method of directly forming a ferromagnetic ferrite film in an aqueous solution at room temperature to about 90 ° C. Specifically, first, OH groups that serve as adsorption sites for metal ions are formed on the surface of the semiconductor chip 1. Next, the semiconductor chip 1 is immersed in a solution (FeCl2 aqueous solution or the like) containing Fe2 + or other metal ions (Co2 +, Ni2 +, Mn2 +, Zn2 +, etc.). Then, metal ions are adsorbed on the OH groups on the surface of the semiconductor chip 1. Next, a part of divalent Fe2 + is oxidized to trivalent Fe3 + by introducing an oxidant such as nitrite ion (NO2-) or air. Further, spinel ferrite can be generated by adsorbing metal ions to the Fe3 +. The first magnetic layer 35 may be formed of a material other than the ferrite described above.

Next, the planar shape of the first magnetic layer 35 is patterned.
As shown in FIG. 6B, a resist film 90A is first formed on the entire surface of the first magnetic layer 35, and photolithography is performed to form a region where the first magnetic layer 35 is to be formed, that is, formation of an inductor element. A mask is formed in the vicinity of the region.

  The patterning of the first magnetic layer 35 can be performed using wet etching. Specifically, the semiconductor chip 1 is immersed in an etchant aqueous solution such as ferric chloride or sodium thiosulfate. Note that the concentration of the etchant aqueous solution may be approximately the same as that in the case of etching the Fe layer, and is appropriately adjusted in view of the thickness of the magnetic layer. The immersion time of the semiconductor chip 1 is also adjusted as appropriate in consideration of the concentration of the etchant aqueous solution and the thickness of the magnetic layer. The patterning of the first magnetic layer 35 can also be performed using dry etching.

Next, as shown in FIG. 6C, the resist film is peeled off.
Thus, the first magnetic layer 35 in the region other than the vicinity of the region where the inductor element is formed is removed, and the first magnetic layer 35 having a predetermined pattern is formed. Here, the first magnetic layer 35 inside the winding formation region is also removed, and a circular hole 51 (see FIG. 2A) is formed. The first magnetic layer 35 may be formed of a material other than the ferrite described above.

  Next, as shown in FIG. 7A, a base film 14 is formed on the entire surface of the semiconductor chip 1. The base film 14 is composed of a lower barrier layer and an upper seed layer. The seed layer functions as an electrode when the first wiring is formed by an electrolytic plating method, and is formed with a thickness of about several hundreds of nanometers using Cu or the like. The barrier layer prevents Cu from diffusing into the connection terminal made of Al or the like, and is formed with a thickness of about 100 nm using TiW or TiN. Each of these layers can be formed by using a PVD (Physical Vapor Deposition) method such as vacuum deposition, sputtering, or ion plating, or an IMP (Ion Metal Plasma) method.

Next, as shown in FIG. 7B, a resist film 90B is formed on the surface of the base film 14, and photolithography is performed to form first wirings and connection wirings (hereinafter referred to as "first wirings"). An opening of the resist film 90B is formed in the region.
Next, as shown in FIG. 7C, electrolytic Cu plating is performed using the seed layer of the base film 14 as an electrode, and Cu is buried in the opening of the resist film 90B to form the first wiring 12 and the like.

Next, as shown in FIG. 7D, the resist is peeled off.
Next, as shown in FIG. 7E, the base film 14 is etched using the first wiring 12 and the like as a mask. For this etching, reactive ion etching (RIE) or the like can be used. Although the first wiring 12 and the like and the seed layer of the base film 14 are both made of Cu, the first wiring 12 and the like are sufficiently thicker than the seed layer of the base film 14, and thus the seed layer is completely removed by etching. be able to.

Next, the first resin layer 37 (see FIG. 2A) is formed in the space between the adjacent first wirings 12.
Specifically, first, a photosensitive resin that becomes the first resin layer 37 is applied to the entire surfaces of the first magnetic layer 35 and the first wiring 12 by a droplet discharge method, a spin coating method, or the like. Next, by exposing and developing, the photosensitive resin is left in the region where the first resin layer 37 is to be formed, that is, the space between the adjacent first wirings 12, and the photosensitive resin in other regions is removed. Further, etching may be performed to planarize the patterned first resin layer 37 to the same thickness as the first wiring 12.
Simultaneously with the step of forming the first resin layer 37, a stress relaxation layer 30 (see FIG. 1) described later may be formed on the surface of the semiconductor chip 1.

Next, as shown in FIG. 8A, the second magnetic layer 31 is formed so as to cover the first wiring 12 and the like.
Specifically, the second magnetic layer 31 is formed on the surfaces of the first wiring 12 and the first magnetic layer 35 in the same manner as the method for forming the first magnetic layer 35 described above. Next, by forming the inner through hole 33 and the outer through hole 34 described above, the second magnetic layer 31 is formed so as to cover the central portion of the first wiring 12 while exposing the end of the first wiring 12. . Next, the planar shape of the second magnetic layer 31 is patterned. At this time, the second magnetic layer 31 is left only in the vicinity of the inductor element formation region, and the second magnetic layer 31 in other regions is removed. Here, the second magnetic layer 31 inside the winding formation region is also removed to form a circular hole 51 (see FIG. 2A). Of course, the second magnetic layer 31 may be formed of a material other than the ferrite described above.

  Next, the central resin layer 50 is formed in the holes 51 inside the first magnetic layer 35 and the second magnetic layer 31. In the step of forming the central resin layer 50, a stress relaxation layer 30 (see FIG. 1) having a predetermined shape is formed on the surface of the semiconductor chip 1 simultaneously with the central resin layer 50. A specific method can be performed using a printing method or photolithography. In particular, if a resin material having photosensitivity is employed as the constituent material of the central resin layer 50 and the stress relaxation layer 30, the central resin layer 50 and the stress relaxation layer 30 can be patterned easily and accurately using photolithography. . Thus, by forming the stress relaxation layer 30 simultaneously with the central resin layer 50, the manufacturing process can be simplified and the manufacturing cost can be reduced.

  Next, as shown in FIG. 8B, the second wiring 22 and the underlying layer 24 are formed. The specific method is the same as the method of forming the first wiring 12 and the base film 14 described above. In addition, the inductor characteristics can be tuned by trimming the second wiring 22 formed on the surface of the second magnetic layer 31 with a laser or the like. Further, the second wiring 22 can be formed simultaneously with the rearrangement wiring 64 in the step of forming the rearrangement wiring 64 shown in FIG. That is, the second wiring 22 that becomes the winding of the inductor element can be accurately formed by using plating, photolithography, or the like, and an inductor element having desired characteristics can be formed. In this way, by forming the second wiring 22 and the like simultaneously with the rearrangement wiring 64 and the like, the manufacturing process can be simplified and the manufacturing cost can be reduced.

Next, as shown in FIG. 8C, the second resin layer 38 is formed in the space between the adjacent second wirings 22.
Specifically, first, a photosensitive resin to be the second resin layer 38 is applied to the entire surfaces of the first magnetic layer 35 and the second wiring 22 by a droplet discharge method, a spin coating method, or the like. Next, by exposing and developing, the photosensitive resin is left in the region where the second resin layer 38 is to be formed, that is, in the space between the adjacent second wirings 22, and the photosensitive resin in other regions is removed. Further, etching may be performed to planarize the patterned second resin layer 38 to the same thickness as the second wiring 22.
The central resin layer 50 described above may be formed simultaneously with the step of forming the second resin layer 38.

Next, the third magnetic layer 36 is formed on the inductor element.
Specifically, the third magnetic layer 36 is formed on the surface of the second magnetic layer 31 in the same manner as the method for forming the first magnetic layer 35 and the second magnetic layer 31 described above. At this time, patterning is performed so that the third magnetic layer 36 is left only in the vicinity of the inductor element formation region, and the third magnetic layer 36 in other regions is removed. Here, the third magnetic layer 36 formed on the central resin layer 50 is removed, and the surface of the central resin layer 50 is exposed. The patterning of the third magnetic layer 36 can be performed using wet etching or dry etching, similarly to the method of forming the second magnetic layer 35 and the second magnetic layer 31 described above.
Thus, the third magnetic layer 36 having a predetermined pattern is formed. As a result, the winding 41 of the inductor element 40 is surrounded by the magnetic layers 35, 31, and 36 to form a closed magnetic circuit (see FIG. 3). Of course, the third magnetic layer 36 may be formed of a material other than the ferrite described above.

  As described in detail above, in the semiconductor chip 1 according to this embodiment, the core 42 of the inductor element 40 is formed of the second magnetic layer 31 and each of the magnetic layers 35, 31, 36 is around the inductor element 40. And a closed magnetic circuit is formed. In the closed magnetic circuit type, since the magnetic flux generated in the inductor element 40 mainly passes through the magnetic layers 35, 31, and 36 having high magnetic permeability, the closed magnetic circuit type is different from the open magnetic circuit type in which the periphery of the inductor element 40 is not shielded. Thus, there is little leakage of magnetic flux to the outside. Therefore, it is possible to prevent a leakage current generated due to interference with a peripheral member in contact with the inductor element 40. Further, the magnetic flux density can be further increased, and the inductance value and Q value of the inductor element can be improved. Therefore, the electrical characteristics of the inductor element 40 can be improved. As a result, the inductor element 40 of the present embodiment can function as a choke coil or the like of the power supply circuit.

Further, since the central resin layer 50 is formed inside the winding 41 of the inductor element 40, the magnetic lines of force are more concentrated on the magnetic layers 35, 31, 36 covering the inductor element 40 outside the central resin layer 50. be able to.
Note that the central resin layer 50 may not be formed. In this case, the magnetic layers 35, 31, and 36 are left without forming the hole 51 around the central axis of the winding.

  In addition, since the first resin layer 37 and the second resin layer 38 are formed in the space between the adjacent wires of the first wire 11 and the second wire 22, the space between the wires of the first wire 11 and the second wire 22. It is possible to suppress the canceling of the magnetic force lines, and to concentrate the magnetic force lines inside the magnetic layers 35, 31 and 36.

Furthermore, in the method for manufacturing the electronic substrate according to the present embodiment, the stress relaxation layer is formed simultaneously with the central resin layer 50, and the rearrangement wiring is formed simultaneously with the second wiring 22. According to this configuration, the inductor element 40 can be formed easily and at low cost without extremely increasing the number of processes and without requiring special equipment such as a mold.
Compared with a planar inductor element (spiral inductor element), a toroidal inductor is less likely to generate a leakage current due to magnetic flux interference with the semiconductor chip 1 and can ensure a high Q value.

(Second Embodiment)
9A is a semiconductor chip according to the second embodiment, FIG. 9A is a plan view, and FIG. 9B is a side cross-sectional view taken along the line DD in FIG. 9A. is there. The second embodiment differs from the first embodiment in that the cross section of the core is formed in a semicircular shape and that a resin layer is formed in all the gaps of the winding. Detailed description of the same parts as those in the first embodiment will be omitted.

As shown in FIG. 9A, also in the second embodiment, the first wiring 12 is patterned in a substantially trapezoidal shape on the surface of the first magnetic layer 35, and the plurality of first wirings 12 are radially arranged on the same circumference. Has been placed.
Further, a nonmagnetic material layer is formed in the space between the adjacent first wirings 12. As the nonmagnetic material layer, a first resin layer 37 made of a photosensitive resin is formed.

  A second magnetic layer 31 made of the same magnetic material as that of the first magnetic layer 35 is formed so as to cover the central portion of the first wiring 12. The second magnetic layer 31 has a donut shape divided in half perpendicular to the central axis thereof, and as shown in FIG. 9B, the second magnetic layer 31 has a substantially semicircular cross section. The second magnetic layer 31 can be formed by the same method as the second magnetic layer in the first embodiment, but can also be directly drawn and formed by a droplet discharge method, a printing method, or the like.

  As shown in FIG. 9B, the second wiring 22 is formed on the surface of the core 42. As shown in FIG. 9A, the second wiring 22 connects the inner end of one first wiring 12 and the outer end of the other first wiring 12 among the adjacent first wirings 12. It is patterned to do. Thus, the 1st wiring 12 and the 2nd wiring 22 are connected in order, and the helical winding 41 is formed. A ring-shaped core 42 is constituted by the second magnetic layer 31 inside the winding 41. The winding element 41 and the core 42 constitute an inductor element 140.

  Further, a nonmagnetic material layer is formed in the space between the adjacent second wirings 22. As the nonmagnetic material layer, a second resin layer 38 made of a photosensitive resin is formed. The second resin layer 38 is formed so as to connect the inner end of one first resin layer 37 and the outer end of the other first resin layer 37 among the adjacent first resin layers 37. ing. As a result, the first resin layer 37 and the second resin layer 38 are formed in all the gaps between the adjacent windings 41.

Furthermore, a third magnetic layer 36 made of the same magnetic material as the first magnetic layer 35 is formed on the surface of the inductor element 140 so as to cover the inductor element 140 and overlap the end portion of the first magnetic layer 35. ing. The third magnetic layer 36 can be formed by the same method as in the first embodiment, but can also be directly drawn and formed by a droplet discharge method, a printing method, or the like.
A central resin layer 50 is formed in a hole 51 formed around the central axis of the winding 41 and in the central part of the magnetic layers 35, 31, 36.

  Thus, even when the core 42 has a semicircular cross section, a closed magnetic path is formed by the core 42 including the magnetic layers 35 and 53 and the second magnetic layer 31. Further, the resin layers 37 and 38 are formed in all the gaps of the winding 41. Therefore, even in a semiconductor chip including such an inductor element 140, the same effect as that of the first embodiment can be obtained.

(Electronics)
Next, an example of an electronic device including the above-described semiconductor chip (electronic substrate) will be described with reference to FIG.
FIG. 10 is a perspective view of a mobile phone. The semiconductor chip described above is disposed inside the housing of the mobile phone 300.

  Note that the semiconductor device described above can be applied to various electronic devices other than mobile phones. For example, LCD projectors, multimedia personal computers (PCs) and engineering workstations (EWS), pagers, word processors, TVs, viewfinder type or monitor direct view type video tape recorders, electronic notebooks, electronic desk calculators, car navigation systems The present invention can be applied to electronic devices such as a device, a POS terminal, and a device provided with a touch panel.

  It should be noted that the technical scope of the present invention is not limited to the above-described embodiments, and includes those in which various modifications are made to the above-described embodiments without departing from the spirit of the present invention. In other words, the specific materials and layer configurations described in the embodiments are merely examples, and can be changed as appropriate.

  For example, in each of the embodiments described above, an inductor element (toroidal inductor element) is formed on the surface of the semiconductor chip. However, an inductor element may be formed on the back surface of the semiconductor chip to ensure electrical continuity with the surface by the through electrode. In each of the above embodiments, the inductor element is formed on the semiconductor chip on which the electronic circuit is formed. However, the inductor element may be formed on an electronic substrate made of an insulating material. In each of the above embodiments, the inductor element in which the spiral winding is arranged around the ring-shaped core is formed, but the inductor in which the spiral winding is arranged around the rod-shaped core is formed. Also good. However, the inductor element having the ring-shaped core is more efficient than the inductor having the rod-shaped core because the magnetic flux forms a closed loop. In each of the above embodiments, the first wiring and the second wiring are formed by the electrolytic plating method, but other film forming methods such as a sputtering method and a vapor deposition method may be employed.

It is explanatory drawing of a semiconductor chip. It is explanatory drawing of the inductor element which concerns on 1st Embodiment. It is explanatory drawing of the inductor element which concerns on 1st Embodiment. It is explanatory drawing of the inductor element which concerns on the 1st modification of 1st Embodiment. It is explanatory drawing of the inductor element which concerns on the 2nd modification of 1st Embodiment. It is process drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is process drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is process drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the inductor element which concerns on 2nd Embodiment. It is a perspective view of a mobile phone.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 12 ... 1st wiring 22 ... 2nd wiring 30 ... Stress relaxation layer 31 ... 2nd magnetic layer 32 ... 1st magnetic layer 35 ... 1st magnetic layer 36 ... 3rd magnetic layer 37 ... 1st resin layer 38 2nd resin layer 39 ... Resin layer 40, 140 ... Inductor element 41 ... Winding 42 ... Core 50 ... Central resin layer (non-magnetic layer) 53 ... 2nd magnetic layer 63 ... Connection terminal

Claims (11)

Relocation wiring of the connection terminal of the electronic circuit, and a toroidal inductor element having a ring-shaped core and a spiral winding,
The core is made of a magnetic material, a gap between the windings is filled with a non-magnetic material, and the toroidal inductor element is covered with a magnetic material.
The method of manufacturing an electronic substrate, wherein at least a part of the winding is formed in the rearrangement wiring forming step. A method of manufacturing an electronic substrate, wherein a rearrangement wiring of a connection terminal of an electronic circuit and a toroidal inductor element having a ring-shaped core and a spiral winding are formed on the surface,
Forming a first magnetic layer made of a magnetic material on the electronic substrate;
Forming a plurality of first wirings on the first magnetic layer;
Forming a first nonmagnetic layer made of a nonmagnetic material in a gap between adjacent first wirings;
Forming a second magnetic layer made of a magnetic material so as to cover a central portion of the plurality of first wirings;
Forming a plurality of second wirings so as to cross the surface of the second magnetic layer;
Forming a second nonmagnetic layer made of a nonmagnetic material in a gap between adjacent second wirings;
Forming a third magnetic layer made of a magnetic material so as to cover the plurality of second wirings,
In the step of forming the second wiring, the rearrangement wiring is formed simultaneously with the second wiring, and the end of one of the first wiring and the end of the other first wiring are connected in order. The toroidal inductor element having the spiral winding composed of the first wiring and the second wiring is formed by disposing the second wiring on the electronic substrate.   The method for manufacturing an electronic substrate according to claim 1, further comprising a step of forming a nonmagnetic layer made of a nonmagnetic material around the central axis of the ring-shaped core. The electronic substrate includes a stress relaxation layer that relaxes a stress difference between the electronic substrate and the counterpart member between the connection terminal used for connection with the counterpart member and the electronic substrate,
The method of manufacturing an electronic substrate according to claim 3, wherein the nonmagnetic layer is formed in the step of forming the stress relaxation layer.   5. The method of manufacturing an electronic substrate according to claim 1, further comprising a step of trimming a part of the winding to adjust characteristics of the toroidal inductor element. 6.   An electronic substrate manufactured using the method for manufacturing an electronic substrate according to claim 1. Relocation wiring of the connection terminal of the electronic circuit, and a toroidal inductor element having a ring-shaped core and a spiral winding,
The core is made of a magnetic material, a gap between the windings is filled with a non-magnetic material, and the toroidal inductor element is covered with a magnetic material, and an electronic substrate,
Furthermore, at least a part of the winding is made of the same material as the rearrangement wiring. Between the connection terminal used for connection with the counterpart member and the electronic substrate, a stress relaxation layer that relaxes the stress difference between the electronic substrate and the counterpart member,
A nonmagnetic layer made of a nonmagnetic material is formed around the center axis of the ring-shaped core in the toroidal inductor element,
The electronic substrate according to claim 7, wherein the nonmagnetic layer is made of the same material as the stress relaxation layer.   9. The electronic substrate according to claim 7, wherein a space between the windings is formed to have a substantially constant width.   The electronic substrate according to claim 7, wherein a conductive layer is formed between the electronic circuit and the toroidal inductor element.   An electronic apparatus comprising the electronic substrate according to claim 7.

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