JP2008103019A - Semiconductor memory device and data writing method thereof - Google Patents

Abstract

An object of the present invention is to provide a semiconductor memory device that prevents erroneous writing to a non-selected memory cell and has an improved degree of integration.
A semiconductor memory device includes a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, a source line between a predetermined number of word lines, and a first selection transistor connected to the bit lines. And a second selection transistor connected to the source line, one end connected to the first selection transistor, a first control electrode connected to the word line, and a plurality of electrically erasable nonvolatile memory cells connected in series The memory cell unit having the memory cell row, and the memory cell at the other end of the memory cell row and the second selection transistor are electrically connected in series, and the memory cell at the other end is in the non-selected state of the data write operation , An intermediate potential between the potential applied to the first control electrode of the memory cell at the other end and the potential applied to the second control electrode of the second selection transistor is applied to the third control electrode. And a transistor.
[Selection] Figure 1

Description

The present invention relates to a semiconductor memory device and a data writing method thereof, and more particularly to a semiconductor memory device including an electrically erasable nonvolatile memory cell and a data writing method thereof.

In recent years, the demand for small-sized and large-capacity nonvolatile semiconductor memory devices has increased rapidly, and NAND flash memory capable of realizing high integration and large capacity has attracted attention.

This NAND flash memory includes a plurality of bit lines, a plurality of word lines intersecting with the plurality of bit lines, a source line between a predetermined number of word lines, and a memory cell unit. In a NAND flash memory, a memory cell unit is constructed by electrically connecting a plurality of electrically erasable nonvolatile memory cells in series. A bit line is connected to one end of the memory cell unit (the drain region of the memory cell at one end of the array) through a bit line side select transistor. A source line is connected to the other end of the memory cell unit (a source region of the memory cell at the other end of the array) through a source line side select transistor. A word line is connected to the control electrode (control electrode) of each memory cell of the memory cell unit.

In the data write operation of the NAND flash memory, data is written to the selected memory cell. For example, when information “0” is written to the selected memory cell, the selected word line is 20V, the selected bit line is 0V, the gate electrode of the drain side select transistor is the power supply voltage Vdd, the gate electrode of the source side select transistor is 0V, the source line The power supply voltage Vdd and 0 V are applied to the well region where the memory cell unit is formed. When a memory cell is composed of a transistor having a charge storage layer (floating electrode), a high write voltage is applied between the channel region and the selected word line in the selected memory cell, so that tunnel insulation is achieved from the channel region. Electrons as data are injected into the charge storage layer through the film, and data is written.

On the other hand, in the data write operation, data is not written to the unselected memory cells. For example, 10 V is applied to the unselected word line, and the power supply voltage Vdd is applied to the unselected bit line. In the non-selected memory cell, no high voltage is generated between the channel region and the non-selected word line. Therefore, electrons are not injected from the channel region into the charge storage layer, and data is not written.

Note that this type of NAND flash memory is described in, for example, Patent Documents 1 to 3 listed below.
JP-A-6-275800 JP 2003-51557 A JP 2004-241558 A

  However, in the above-described NAND flash memory, the following points have not been considered. In the data write operation of the NAND flash memory, 0 V is applied to the gate electrode of the source side select transistor, and the power supply voltage Vdd is applied to the unselected bit line, so the source connected to the unselected bit line The power supply voltage Vdd is applied between the gate electrode and the drain region of the side selection transistor. In practice, this is a voltage obtained by subtracting the threshold voltage of the memory cell from the power supply voltage Vdd. Electrons are generated by GIDL (gate induced drain leakage) at the drain region end on the channel region side of the source side select transistor. The electrons are injected into the charge storage layer of the non-selected memory cell, and erroneous writing in which data is written to the non-selected memory cell occurs. The erroneous writing appears prominently in an unselected memory cell that is close to the source side select transistor, particularly, in which the source region is directly connected to the drain region of the source side select transistor.

In addition, it is possible to suppress a certain amount of erroneous writing by separating the unselected memory cell where the erroneous writing appears remarkably and the source side selection transistor as much as possible. However, the occupied area increases between the memory cell and the source side select transistor, which hinders the improvement in the degree of integration of the NAND flash memory.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor memory device that can prevent erroneous writing and improve the degree of integration and a data writing method thereof. It is to be.

A first feature according to an embodiment of the present invention is that, in a semiconductor memory device, a plurality of bit lines, a plurality of word lines arranged so as to intersect the plurality of bit lines, and a predetermined number of word lines A first select transistor connected to the bit line and a second select transistor connected to the source line, one end of which is connected to the first select transistor and connected to the word line A memory cell unit having a memory cell column to which a first control electrode is connected and a plurality of electrically erasable nonvolatile memory cells are connected in series, a nonvolatile memory cell at the other end of the memory cell column, and a second selection And a potential applied to the first control electrode of the non-volatile memory cell at the other end in a non-selected state of the data write operation. And a transistor whose serial intermediate potential between the second potential applied to the second control electrode of the selection transistor is applied to the third control electrode.

A second feature according to the embodiment of the present invention is that, in the semiconductor memory device, a plurality of bit lines, a plurality of word lines arranged crossing the plurality of bit lines, and a predetermined number of lines are provided. A source line disposed between the word lines; a first selection transistor connected to the bit line; and a second selection transistor connected to the source line, one end connected to the first selection transistor, A memory cell unit having a memory cell column in which a plurality of electrically erasable nonvolatile memory cells each having a first charge storage electrode and a first control electrode are connected in series, the first control electrode being connected to the line; A dummy nonvolatile memory cell electrically connected in series between the nonvolatile memory cell at the other end of the memory cell column and the second selection transistor, and having a second charge storage electrode and a second control electrode. Preparation The capacitance ratio of the coupling capacitance between the second charge storage electrode and the substrate to the coupling capacitance between the second charge storage electrode and the second control electrode of the dummy nonvolatile memory cell is a nonvolatile memory. The capacitance ratio of the coupling capacitance between the first charge storage electrode and the substrate to the coupling capacitance between the first charge storage electrode and the first control electrode of the cell is small.

The third feature according to the embodiment of the present invention is that it is arranged between a plurality of bit lines, a plurality of word lines arranged crossing the plurality of bit lines, and a predetermined number of word lines. A source line; a first selection transistor connected to the bit line; a second selection transistor connected to the source line; one end connected to the first selection transistor; and a first control electrode connected to the word line And a memory cell unit having a memory cell column in which a plurality of electrically erasable nonvolatile memory cells are connected in series, and a non-volatile memory cell at the other end of the memory cell column and a second select transistor A method for writing data in a semiconductor memory device, comprising: a transistor electrically connected in series, wherein when writing data to a selected nonvolatile memory cell of a memory cell unit, Data is not written to the non-selected non-volatile memory cell at the other end of the unit, and the potential applied to the first control electrode of the non-volatile memory cell and the second control electrode of the second select transistor are applied. And applying an intermediate potential to the third control electrode of the transistor.

According to the present invention, it is possible to provide a semiconductor memory device and a data writing method thereof that can prevent erroneous writing of unselected memory cells and improve the degree of integration.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present embodiment shows an example in which the present invention is applied to a NAND flash memory (NAND EEPROM).

(Embodiment 1)
FIG. 2 is a block diagram showing an outline of the NAND flash memory (nonvolatile semiconductor memory device) 100 according to the first embodiment of the present invention. The NAND flash memory 100 shown in FIG. 2 includes a data input / output buffer 101, a command interface 102, a control unit 103, a selection circuit 104, a row control circuit 105, a column control circuit 106, a sense amplifier 107, A block control circuit 108, an intermediate potential control circuit 109, and a memory cell array 110. The NAND flash memory 100 transmits / receives control signals such as data and commands to / from an external I / O pad (Pad) 200.

Data input / output buffer 101 is connected to external I / O pad 200 via an IO terminal. The data input / output buffer 101 receives control signals such as data and commands from the external I / O pad 200 and temporarily holds them, and the data is sent to the row control circuit 105 and the column control circuit 106, and the control signals are sent to the command To interface 102. Here, the control signal includes a command signal instructing execution of a data read operation, a write operation, and an erase operation. The data input / output buffer 101 outputs data input from the row control circuit 105 and the column control circuit 106 to the external I / O pad 200.

The command interface 102 outputs a control signal input from the data input / output buffer 101 to the control unit 103.

The control unit 103 controls the data input / output buffer 101, the command interface 102, the selection circuit 104, the row control circuit 105, the column control circuit 106, the sense amplifier 107, the block control circuit 108, and the intermediate potential control circuit 109, and Read, write, erase, and data input / output control are performed. Based on the control signal input from the command interface 102, the control unit 103 generates address information for accessing a memory cell in the memory cell array 110 and an internal control signal for applying a potential to the memory cell. Output to the selection circuit 104, the row control circuit 105, the column control circuit 106, and the sense amplifier 107.

In addition, when a control signal instructing data writing is input from the command interface 102, the control unit 103 is an internal for applying a potential to a control electrode (control gate electrode) of a non-selected memory cell to be described later. A control signal is generated and output to the intermediate potential control circuit 109.

The selection circuit 104 sequentially reads bit data from the bit lines of the memory cell array 110 in accordance with an internal control signal input from the control unit 103 and outputs the bit data to the sense amplifier 107 as retained data.

The row control circuit 105 controls the selection circuit 104 and the sense amplifier based on the internal control signal input from the control unit 103 and the data input from the data input / output buffer 101, and controls the control electrode of the memory cell of the memory cell array 110. Potentials (voltages) necessary for erasing, writing, and reading data on selected word lines and non-selected word lines connected to (control gate electrodes) and gate lines connected to control electrodes (control gate electrodes) of selected transistors Is generated and applied.

The column control circuit 106 controls the selection circuit 104 and the sense amplifier based on the internal control signal input from the control unit 103 and the data input from the data input / output buffer 101, and the memory cell is connected to the bit line of the memory cell array 110. A potential (voltage) necessary for erasing data, writing data to the memory cell, and reading data from the memory cell is generated and applied.

The sense amplifier 107 has a plurality of data caches and is connected to the bit lines of the memory cell array 110 via the selection circuit 104. The sense amplifier 107 supplies data to the bit line, detects the potential of the bit line, and holds it in the data cache.

The block control circuit 108 performs data erase control in units of blocks for the memory cell array 110 in accordance with an internal control signal from the control unit 103.

The intermediate potential control circuit 109 uses the internal control signal from the control unit 103 when the memory cell to which one end (drain electrode) of the erroneous write prevention transistor in the memory cell 110 is connected is in a non-selected state of the data write operation. In addition, the potential applied to the control electrode of the memory cell in the non-selected state (hereinafter referred to as the non-selected memory cell) and the selection transistor to which the other end (source electrode) of the erroneous write prevention transistor is connected. An intermediate potential (voltage) with respect to the potential applied to the control electrode is generated and applied to the control electrode of the erroneous writing prevention transistor.

Here, the intermediate potential control circuit 109 controls, for example, the potential applied to the control electrode of the memory cell connected to the erroneous writing prevention transistor and the source line side selection transistor to which the erroneous writing prevention transistor is connected. You may provide the table with which the applied potential to an electrode was matched. When the memory cell to which the erroneous write prevention transistor is connected is a non-selected memory cell, the intermediate potential control circuit 109 calculates an intermediate potential corresponding to the potential applied to the control electrode of the non-selected memory cell. .

In other words, the control unit 103, the row control circuit 105, the column control circuit 106, and the intermediate potential control circuit 109 prevent erroneous writing to the non-selected memory cells and appropriately write data to the selected memory cells. A write control circuit is configured.

The memory cell array 110 includes a plurality of electrically rewritable (electrically erasable) nonvolatile memory cells arranged in a matrix. This memory cell has a charge storage electrode (floating gate electrode) disposed on a substrate (Substrate) such as silicon via a tunnel oxide film (first insulating film) such as a silicon thermal oxide film (SiO ₂ ). And a control electrode disposed on the charge storage electrode with an insulating film (second insulating film) such as an ONO film (Oxide-Nitride-Oxide: oxide film-nitride film-oxide film laminated film) interposed therebetween. (Control gate electrode) and a conductive field effect transistor. The plurality of memory cells constitute a NAND cell unit (memory cell unit), and this NAND cell unit constitutes, for example, a plurality of blocks as shown in FIG.

The memory cell array 110 shown in FIG. 3 is divided into a total of m blocks (BLOCK0, BLOCK1,... BLOCKi,... BLOCKm). Here, the “block” is a minimum unit of data erasure.

Each of the blocks BLOCK0 to BLOCKm is composed of k NAND cell units 0 to k as BLOCKi typically shown in FIG. In the present embodiment, in each NAND cell unit, 32 memory cells MTr0 to MTr31 are connected in series to constitute a memory cell column. One end of the memory cell column is connected to a bit line BL (BL_0, BL_1, BL_2,... BL_k-1, BL_k) via a selection gate transistor (hereinafter referred to as a selection transistor) Tr0 connected to the selection gate line SGS. Connected. The other end of the memory cell column is connected to one end of the erroneous write prevention transistor Tr2. The other end of the erroneous write prevention transistor Tr2 is connected to the common source line (SOURCE) via the selection transistor Tr1 connected to the selection gate line SGS.

More specifically, the source electrode of the erroneous write prevention transistor Tr2 is the drain electrode of the selection transistor Tr1 on the common source line side, and the drain electrode of the erroneous write prevention transistor Tr2 is the memory cell ( It is electrically connected in series with the source electrode of MTr31) shown in FIG. In other words, the erroneous write prevention transistor Tr2 is arranged between the source line side select transistor Tr1 and the nonvolatile memory cell at the other end of the memory cell column.

In other words, the NAND flash memory has a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, a source line between a predetermined number of word lines, and a memory cell unit. . In a NAND flash memory, a memory cell unit electrically includes a first selection transistor connected to a bit line, a second selection transistor connected to a source line, and a plurality of electrically erasable nonvolatile memory cells. And memory cell strings connected in series. A bit line is connected to one end of the memory cell column (the drain region of the memory cell at one end of the array) through a first selection transistor (bit line side selection transistor). An erroneous write prevention transistor Tr2 is connected to the other end of the memory cell column (the source region of the memory cell at the other end of the array). The erroneous write prevention transistor Tr2 is connected to the source line through the second selection transistor (source line side selection transistor).

In addition, word lines WL (WL0 to WL31) are connected to the control electrodes (first control electrodes) of the nonvolatile memory cells MTr of each memory cell unit. The plurality of word lines and the above-described selection gate line are connected to the row control circuit 105. Each of k memory cells MTr connected to one word line WL stores 1-bit data, and these k memory cells MTr constitute a unit of “page”. The control electrode of the erroneous write prevention transistor Tr2 is connected to the intermediate potential control line MCG.

The erroneous writing prevention transistor Tr2 is a transistor that prevents erroneous writing of a non-selected nonvolatile memory cell during data writing. The erroneous write prevention transistor Tr2 controls the nonvolatile memory cell in the non-selected state when the nonvolatile memory cell connected to the erroneous write prevention transistor Tr2 is in the non-selected state of the data write operation. An intermediate potential between the potential applied to the electrode and the potential applied to the control electrode of the source line side selection transistor (second selection transistor) is applied to the control electrode of the erroneous writing prevention transistor Tr2.

In the present embodiment, the number of blocks constituting the memory cell array is m, and one block includes k NAND cell units including 32 memory cells MTr. However, the number of blocks, the number of memory cells MTr, and the number of NAND cell units may be changed in accordance with a desired capacity. In the present embodiment, each memory cell MTr stores 1-bit data. However, each memory cell MTr stores a plurality of bits of data (multi-valued bit data) according to the amount of injected electrons. You may do it. In this embodiment, an example of a NAND flash memory in which one NAND cell unit is connected to one bit line BL is described. However, a plurality of NAND flash memories 100 according to this embodiment are provided. This NAND cell unit may be applied to a so-called shared bit line type NAND flash memory in which one bit line BL is shared.

Next, the structure of the erroneous write prevention transistor will be described with reference to FIG. 4A is a cross-sectional view showing the vicinity of a conventional source line side select transistor, and FIG. 4B is a cross-sectional view showing the vicinity of an erroneous write preventing transistor according to the present embodiment.

As described above, the erroneous write prevention transistor 403 shown in FIG. 4B has one end on the source line side select transistor (Tr1 shown in FIG. 1) 401 and the other end on the memory cell (Mtr31 shown in FIG. 1). 402 is connected. That is, the erroneous write prevention transistor 403 is arranged between the source line side selection transistor 401 shown in FIG. 4A and the memory cell 402 adjacent to the selection transistor 401.

The memory cell 402 has a charge storage electrode (FG) disposed on a substrate such as silicon with a tunnel oxide film (first insulating film) interposed therebetween, and an ONO film on the charge storage electrode. And a first control electrode (word line) provided.

In the erroneous writing prevention transistor 403, an opening such as a contact hole or a via hole is provided between the charge storage electrode of the memory cell 402 and the first control electrode. The opening opens the charge storage electrode of the memory cell 402 and the first control electrode. The erroneous writing prevention transistor 403 includes a first conductive layer on the same layer as the charge storage electrode, and a second conductive layer on the same layer as the first control electrode on the first conductive layer. The third control electrode 403a is electrically connected. That is, the structure of the erroneous write prevention transistor 403 is the same as that of the selection transistor 401.

Next, a data write operation of the NAND flash memory 100 having the above-described configuration will be described.

In the NAND flash memory 100, when a control signal instructing data writing and data are input from the external I / O pad 200 to the data input / output buffer 101, the data input / output buffer 101 sends the control signal to the command interface 102. The data is output to the row control circuit 105 and the column control circuit 106.

The command interface 102 outputs a control signal from the data input / output buffer 101 to the control unit 103. The control unit 103 generates address information and an internal control signal for supplying a potential to the memory cell from the control signal, and outputs the internal control signal to the row control circuit 105, the column control circuit 106, and the intermediate potential control circuit 109.

The row control circuit 105 selects and deselects the row control circuit 105 connected to the control electrode of the memory cell of the memory cell array 110 based on the internal control signal input from the control unit 103 and the data input from the data input / output buffer 101. A potential necessary for data writing is generated and applied to the word line and the gate line connected to the control electrode of the selection transistor. Further, the column control circuit 106 generates and applies a predetermined potential to the selected and non-selected bit lines of the memory cell array 110 based on the internal control signal from the control unit 103.

When the memory cell MTr31 connected to the erroneous write prevention transistor Tr2 shown in FIG. 1 is in a non-selected state of the data write operation, the intermediate potential control circuit 109 is based on the internal control signal from the control unit 103. The intermediate potential between the potential applied to the control electrode of the non-selected memory cell MTr31 and the potential applied to the control electrode of the source line side select transistor Tr1 is set to the erroneous write prevention transistor Tr2 via the intermediate potential control line MCG. Applied to the control electrode.

  Next, the write operation of the information “0” when the memory cell connected to the erroneous write prevention transistor is in a non-selected state will be described in detail with reference to FIGS. 1 to 4 and FIG. Explained.

FIG. 5 is an enlarged circuit diagram in the vicinity of the erroneous write prevention transistor. The circuit diagram of FIG. 5 shows a selection transistor 501 having one end connected to the source line, an erroneous writing prevention transistor 502 connected to the selection transistor 501, and a memory cell 503 connected to the erroneous writing prevention transistor 502. Yes.

When the memory cell connected to the erroneous write prevention transistor 502 is in a non-selected state of the write operation, the intermediate potential control circuit 109 supplies the control electrode of the erroneous write prevention transistor 502 through the intermediate potential control all MCG. An intermediate potential (for example, 4 V) between a potential of 10 V applied to the control electrode of the selected memory cell 503 and a potential of 0 V applied to the control electrode of the source line side select transistor 501 is applied.

In the data write operation of the NAND flash memory, data is not written to the non-selected memory cell. For example, the row control circuit 105 supplies a voltage of 10 V to the non-selected word line WL connected to the control electrode of the non-selected memory cell 503, and a power source to the non-selected bit line BL connected to the drain electrode of the non-selected memory cell 503. A voltage Vdd is applied. In the non-selected memory cell, no high voltage is generated between the channel region and the non-selected word line. Therefore, electrons are not injected from the channel region into the charge storage layer, and data is not written.

On the other hand, in the data write operation, data is written to the selected memory cell. For example, when information “0” is written to the selected memory cell, the row control circuit 105 applies a voltage of 20 V to the selected word line WL connected to the control electrode of the selected memory cell (not shown), and the bit line side select transistor. A power supply voltage Vdd is applied to the selection gate line (SGD) connected to the control electrode, and a voltage of 0 V is applied to the selection gate line (SGS) connected to the control electrode of the source line side selection transistor 501. A power supply voltage Vdd is applied to the source line, and 0 V is applied to the well region where the memory cell unit is formed. The column control circuit 106 applies 0 V to the selected bit line BL connected to the drain electrode of the selected memory cell (not shown). In the case where a memory cell is configured by a transistor having a charge storage layer (floating gate electrode), a high write voltage is applied between the channel region and the selected word line in the selected memory cell. Electrons as data are injected into the charge storage electrode through the insulating film, and the data is written.

Note that the data write operation is not limited to the above-described operation order. For example, the operation of applying the potential to the erroneous write prevention transistor and the operation of applying the potential to the non-selected memory cell may be performed at the same time, either before or after the write operation to the selected memory cell. It may be done.

As a result, the potential of about 6 V induced in the channel of the non-selected memory cell 503 is erroneously written as the channel potential of the non-selected memory cell 503 by applying the intermediate potential of 4 V to the control electrode of the erroneous write prevention transistor 502. The potential difference from the gate potential of the insertion preventing transistor 502 can be reduced to about 2V. As a result, electrons generated at the drain region end on the channel region side of the erroneous write preventing transistor 502 can be reduced (leakage of leakage current), so that the charge storage layer of the non-selected memory cell 503 is supplied to the charge storage layer. Electron injection (incorrect data writing) can be prevented.

Further, by applying an intermediate potential to the control electrode of the erroneous writing prevention transistor 502, the potential difference between the channel potential of the erroneous writing prevention transistor 502 and the gate potential of the selection transistor 501 is also reduced. Electrons generated at the drain region end of the channel region 501 can be reduced (leakage current can be suppressed).

In other words, in the NAND flash memory, by providing an erroneous write prevention transistor in which an intermediate potential is applied to the control electrode, the potential difference between the channel potential of the non-selected memory cell and the gate potential of the source line side select transistor is Divided into a potential difference between the channel potential of the non-selected memory cell and the gate potential of the erroneous write prevention transistor, and a potential difference between the gate potential of the erroneous write prevention transistor and the gate potential of the source line side selection transistor, respectively. The potential difference is reduced.

Note that the intermediate potential applied to the control electrode of the erroneous writing prevention transistor is not limited to 4 V described above. That is, if the potential is intermediate between the potential applied to the control electrode of the source line side select transistor and the potential applied to the control electrode of the memory cell connected to the erroneous write prevention transistor, tunnel insulation between the substrate and the charge storage electrode Different potentials may be used depending on the thickness and quality of the film, the miniaturization of the memory cell, and the like.

As described above, the NAND flash memory 100 according to the first embodiment includes a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and a source line between a predetermined number of word lines. , Having a first selection transistor connected to the bit line and a second selection transistor connected to the source line, one end connected to the first selection transistor, and a first control electrode connected to the word line. A memory cell unit having a memory cell column in which a plurality of electrically erasable nonvolatile memory cells are connected in series, and electrically between a nonvolatile memory cell at the other end of the memory cell column and a second selection transistor When the non-volatile memory cell at the other end is connected in series and the non-selected state of the data write operation, the potential applied to the first control electrode of the non-volatile memory cell at the other end and the second selected transistor Intermediate potential between the potential applied to the second control electrode of the register is provided with a erroneous writing prevention transistor applied to the third control electrode.

As a result, the potential applied to the control electrode of the non-selected memory cell to which one end of the erroneous write prevention transistor is connected to the third control electrode of the erroneous write prevention transistor and the other end of the erroneous write prevention transistor Since an intermediate potential is applied between the potential applied to the control electrode of the selection transistor to which the memory cell is connected, the potential difference between the potential applied to the control electrode of the erroneous writing prevention transistor and the potential induced in the channel of the non-selected memory cell Can be reduced. As a result, since electrons generated in the drain region of the erroneous write prevention transistor are reduced, electrons are not injected into the charge storage electrode of the non-selected memory cell, and erroneous write can be prevented.

In other words, erroneous writing to a non-selected memory cell is close to a source line-side select transistor in which the potential difference between the channel potential of the non-selected memory cell and the gate potential of the source line-side select transistor is always large. This is noticeable when the memory cell in which the source region is directly connected to the drain region of the transistor is an unselected memory cell.

Therefore, in the nonvolatile semiconductor memory device according to the present embodiment, in order to reduce the potential difference between the channel potential of the memory cell directly connected to the source line side select transistor and the gate potential of the source line side select transistor, An erroneous write prevention transistor is provided between the memory cell and the source line side selection transistor. If the memory cell directly connected to the erroneous write prevention transistor is a non-selected memory cell, an intermediate potential between the potential applied to the control electrode of the non-selected memory cell and the potential applied to the control electrode of the selected transistor is By applying to the control electrode of the erroneous write prevention transistor, the electric field between the non-selected memory cell and the erroneous write prevention transistor is relaxed, and the drain region at the channel region side of the erroneous write prevention transistor is The generation amount of electrons is suppressed, and it is possible to achieve a potential at which electrons are not injected into the charge storage layer of the non-selected memory cell.

In addition, according to the present embodiment, since the erroneous write prevention transistor is a selection transistor having the same channel length, the cell block size is equivalent to one cell even when the generation changes and the shrink progresses. Stay on the increase. Therefore, as shrinking progresses, the effective area in the cell block can be increased as compared with the case where a certain separation distance is provided between the selection transistor and the adjacent memory cell as in the prior art. Further shrinking of the cell block is also possible.

In other words, in the present embodiment, a selection transistor connected to the source line and an erroneous write prevention transistor to which an intermediate potential applied to the memory cell on the selection transistor side is added, as in the conventional case. Since it is not necessary to provide a certain separation distance between the selection transistor and the adjacent memory cell, it is possible to prevent the influence of GIDL that occurs when the separation distance is relatively shortened due to miniaturization. Conversely, in this embodiment, the effective area in the cell block is smaller than when the separation distance between the selection transistor and the adjacent memory cell is not changed, that is, when an absolute separation distance is provided. Reduction can be suppressed.

Note that although the structure in which the intermediate voltage control circuit is provided in the semiconductor memory device has been described in this embodiment mode, the present invention is not limited to this structure. That is, the present invention can be applied even if an intermediate potential control circuit is provided as an external device of the semiconductor memory device and the intermediate potential is supplied from the intermediate potential control circuit, which is the external device, to the semiconductor memory device.

In this embodiment, the configuration in which one erroneous write prevention transistor is added has been described. However, the present invention is not limited to this configuration, and a plurality of erroneous write prevention transistors are added. Also good.

In the first embodiment, a case where a memory cell structure is applied to an erroneous write prevention transistor will be described as an example. FIG. 6 is a cross-sectional view illustrating the structure of the erroneous write prevention transistor according to the first embodiment. The configuration of the NAND flash memory 100 is the same as that of the NAND flash memory 100 according to the first embodiment, and a description thereof will be omitted.

  As shown in FIG. 6, the memory cell 402 includes a charge storage electrode (FG) disposed on a substrate such as silicon via a tunnel oxide film (first insulating film) such as a silicon thermal oxide film, A first control electrode (word line: WL) is provided on the charge storage electrode via an insulating film (second insulating film) such as an ONO film.

The erroneous write prevention transistor 601 is provided with an opening such as a contact hole or a via hole between the charge storage electrode of the memory cell 402 and the first control electrode. The opening opens the charge storage electrode of the memory cell 402 and the first control electrode. In the erroneous write prevention transistor 601, the first conductive layer that is the same as the charge storage electrode is electrically connected to the second conductive layer that is the same layer as the control electrode on the first conductive layer. The third control electrode 601a is provided. That is, in the erroneous write prevention transistor 601, dielectrics such as an ONO film (or NONON film) disposed on the same layer of the charge storage electrode and the first control electrode of the memory cell 402 are electrically connected to each other. A third control electrode 601a is connected.

As described above, in the NAND flash memory according to the first embodiment, the nonvolatile memory cell has a charge disposed on the substrate with the tunnel oxide film (first insulating film) such as a silicon thermal oxide film interposed therebetween. A storage electrode and a control electrode (first control electrode) disposed on the charge storage electrode via an insulating film (second insulating film) such as an ONO film are provided. The erroneous write prevention transistor electrically connects the first conductive layer in the same layer as the charge storage electrode and the second conductive layer in the same layer as the first control electrode on the first conductive layer. Connected third control electrode.

As a result, the potential applied to the control electrode of the non-selected memory cell to which one end of the erroneous write prevention transistor is connected to the third control electrode of the erroneous write prevention transistor, the erroneous write prevention transistor, and the like. Since an intermediate potential between the potential applied to the control electrode of the selection transistor to which the end is connected is applied, the potential applied to the control electrode of the erroneous write prevention transistor and the potential induced in the channel of the non-selected memory cell The potential difference can be reduced. As a result, electrons generated in the drain region of the erroneous write preventing transistor are reduced (leakage of leakage current), so that electrons are not injected into the charge storage electrode of the non-selected memory cell, thereby preventing erroneous writing. be able to.

In addition, since the erroneous write prevention transistor 601 according to the first embodiment processes a memory cell having a channel length shorter than that of the selection transistor, the cell block can be further reduced and the memory cell can be miniaturized. The effective area involved can be further expanded.

  Further, the third control electrode of the erroneous write prevention transistor is formed by removing the second insulating film such as the ONO film of the memory cell 402 by processing like the erroneous write prevention transistor 702 shown in FIG. Alternatively, the control electrode 702a in which the charge storage electrode and the control electrode are directly electrically connected may be used.

(Embodiment 2)
FIG. 8 is a block diagram schematically showing a NAND flash memory (nonvolatile semiconductor memory device) 800 according to the second embodiment of the present invention. The NAND flash memory 800 according to the second embodiment has a row control circuit 801 in place of the row control circuit 105 by deleting the intermediate potential control circuit 109 of the NAND flash memory 100 according to the first embodiment. In the NAND flash memory 800 shown in FIG. 8, the same components as those of the NAND flash memory 100 shown in FIG.

The row control circuit 801 controls the selection circuit 104 and the sense amplifier based on the internal control signal input from the control unit 103 and the data input from the data input / output buffer 101, and controls the control electrode of the memory cell of the memory cell array 110. A potential (voltage) necessary for erasing, writing, and reading of data is generated and applied to the selected and unselected word lines connected to the gate and the gate line connected to the control electrode of the selection transistor.

Further, the row control circuit 801 is a dummy nonvolatile memory cell in a plurality of memory cell units constituting the memory cell array, as shown in FIG. 9, based on an internal control signal input at the time of data writing from the control unit 103. The same potential (voltage) as that applied to the word line connected to the non-selected memory cell is generated and applied to the control electrode.

Next, dummy nonvolatile memory cells in a plurality of memory cell units (NAND cell units) constituting the memory cell array 110 will be described with reference to FIG. Each of the blocks BLOCK0 to BLOCKm constituting the memory cell array 110 is composed of k NAND cell units 0 to k as shown in BLOCKi typically shown in FIG. In the present embodiment, each NAND cell unit includes 32 memory cells MTr0 to MTr31 connected in series to form a memory cell column. One end of this memory cell column is connected to a bit line BL (BL_0, BL_1, BL_2,..., BL_k-1, BL_k) via a selection transistor Tr0 connected to a selection gate line SGS. Further, the other end of the memory cell column is connected to one end of the dummy nonvolatile memory cell DMTr1. The other end of the dummy nonvolatile memory cell DMTr1 is connected to the common source line SOURCE via a selection transistor Tr1 connected to the selection gate line SGS.

More specifically, the source electrode of the dummy nonvolatile memory cell DMTr1 is the drain electrode of the selection transistor Tr1 on the common source line side, and the drain electrode of the dummy nonvolatile memory cell DMTr1 is the memory cell at the other end of the memory cell column (FIG. 9). It is electrically connected in series with the source electrode of MTr31). In other words, the dummy nonvolatile memory cell DMTr1 is arranged between the source line side select transistor Tr1 and the nonvolatile memory cell at the other end of the memory cell column.

In other words, the NAND flash memory has a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, a source line between a predetermined number of word lines, and a memory cell unit. . In the NAND flash memory, the memory cell unit includes a first selection transistor connected to the bit line, a second selection transistor connected to the source line, a first charge storage electrode (floating gate electrode), and a first selection transistor. A plurality of electrically erasable nonvolatile memory cells each having one control electrode (control gate electrode) are constructed with a memory cell array electrically connected in series. A bit line is connected to one end of the memory cell column (the drain region of the memory cell at one end of the array) through a first selection transistor (bit line side selection transistor). A dummy nonvolatile memory cell DMTr1 having a second charge storage electrode and a second control electrode is connected to the other end of the memory cell column (the source region of the memory cell at the other end of the array). The dummy nonvolatile memory cell DMTr1 is connected to the source line through the second selection transistor (source line side selection transistor). This dummy non-volatile memory DMTr1 is a non-volatile memory cell for preventing erroneous writing of a non-selected non-volatile memory cell during data writing.

As shown in FIG. 10, the control electrode of the dummy nonvolatile memory cell DMTr1 is connected to a dummy word line DWL, and this dummy word line DWL is connected to a row control circuit 801. The non-volatile memory cell MTr31 connected to the drain electrode of the dummy non-volatile memory cell DMTr1 is not connected to the control electrode of the dummy non-volatile memory cell DMTr1 by the row control circuit 801 when the data write operation is not selected. The same potential as that applied to the control electrode of the selected memory cell MTr31 is applied.

A word line WL (WL0 to WL31) is connected to the control electrode of each nonvolatile memory cell MTr. The plurality of word lines and the above-described selection gate line are connected to the row control circuit 801. Each of k memory cells MTr connected to one word line WL stores 1-bit data, and these k memory cells MTr constitute a unit of “page”.

Next, the dummy nonvolatile memory cell will be described with reference to FIG. FIG. 11 is a cross-sectional view showing the vicinity of a dummy nonvolatile memory cell. A dummy nonvolatile memory cell 1101 shown in FIG. 11 is disposed between a selection transistor 1102 connected to a source line and a memory cell 1103 connected to the dummy nonvolatile memory cell 1101.

The dummy nonvolatile memory cell 1101 has the same cross-sectional structure as the memory cell 1103, and has a charge storage electrode (FG) and a control electrode (CG) on a substrate (Substrate) such as silicon. Compared with the memory cell 1103, the dummy nonvolatile memory cell 1101 has a thickness of a tunnel oxide film (first insulating film) 1104 between the substrate and the charge storage electrode, in other words, the substrate and the charge storage electrode. Only the distance of 1104 is different. That is, the thickness of the tunnel oxide film 1104 between the substrate of the dummy nonvolatile memory cell 1101 and the charge storage electrode is made thinner than 1105 between the substrate of the memory cell 1103 and the charge storage electrode (the substrate and the charge storage electrode). The dielectric constant is increased. As a result, the capacitance ratio of the coupling capacitance between the charge storage electrode and the substrate to the coupling capacitance between the charge storage electrode and the control electrode of the dummy nonvolatile memory cell 1101 is smaller than that of the nonvolatile memory cell 1103.

Here, the thickness of the tunnel oxide film between the substrate and the charge storage electrode is generated, for example, by the following method. First, a thin silicon oxide film and a silicon nitride film (Si ₃ N ₄ ) are formed on a substrate, and a dummy nonvolatile memory cell is masked. Then, the thin silicon oxide film and silicon nitride film are removed by etching, and then the photomask is removed. Then, a tunnel oxide film (SiO ₂ ) is formed by a thermal oxidation method using the silicon nitride film as an oxidation resistant mask.

In addition, the potential (voltage) V _FG applied to the charge storage electrode of the memory cell is expressed by the following equation (1): the charge storage electrode and the substrate with respect to the coupling capacitance between the charge storage electrode and the control electrode. coupling capacitance capacitance ratio applied potential to the C _r and the control electrode during (voltage) obtained by V _CG.
V _FG = C _r × V _CG (1)

This coupling capacity ratio C _r is the coupling capacity between the charge storage electrode and the substrate with respect to the coupling capacity (C _ONO ) between the control electrode and the charge storage electrode, as shown in the following equation (2). It is obtained by (C _OXY + C _ONO ).
C _r = C _ONO / C _OXY + C _ONO (2)

FIG. 12 is a circuit diagram for explaining the coupling capacitance ratio of the dummy nonvolatile memory cell. 12A shows the nonvolatile memory cell MTr, and FIG. 12B shows the dummy nonvolatile memory cell DMTr1.

For example, the capacitance ratio C _r1 of the coupling capacitance c1202 between the charge storage electrode and the substrate to the coupling capacitance c1201 between the control electrode and the charge storage electrode of the nonvolatile memory cell shown in FIG. In the case of 5, when the potential 10v is applied to the word line wl, the potential 5v is applied to the charge storage electrode.

On the other hand, since the thickness of the tunnel oxide film between the substrate and the charge storage electrode is thin as described above, the dummy nonvolatile memory cell dmtr1 shown in FIG. The capacitance ratio C _r2 of the coupling capacitor c1204 between the charge storage electrode and the substrate to the coupling capacitor c1203 between the control electrode and the charge storage electrode is determined between the control electrode and the charge storage electrode of the nonvolatile memory cell mtr. It is smaller than the capacitance ratio C _r1 of the coupling capacitance c1202 between the charge storage electrode and the substrate with respect to the coupling capacitance c1201. That is, the coupling capacity ratios C _r1 and c _{r2 of} the nonvolatile memory cell and the dummy nonvolatile memory cell _satisfy C _r1 > C _r2 .

Specifically, the capacitance ratio C _r of the coupling capacitance c1204 between the control electrode of the dummy non-volatile memory cell shown in FIG. 12 (B) and the charge storage electrode and the substrate to the charge storage electrode capacitance C1203, 12 In the case where the coupling capacity ratio of the memory cell of (b) is 0.4, which is smaller than 0.5, when the same potential 10v as that of the memory cell of FIG. The potential 4v is applied.

As a result, the potential difference between the potential induced in the channel of the non-selected memory cell and the potential applied to the charge storage electrode of the dummy nonvolatile memory cell can be reduced, so that the drain on the channel region side of the dummy nonvolatile memory cell can be reduced. Electrons generated at the edge of the region can be reduced. As a result, injection of electrons into the charge storage layer of the non-selected memory cell can be prevented, that is, erroneous data writing can be prevented.

  Next, in the semiconductor memory device 800 having the above-described configuration, the write operation of information “0” when the memory cell connected to the dummy nonvolatile memory cell DMTr1 is in the non-selected state will be described with reference to FIGS. explain.

When the memory cell MTr31 connected to the dummy nonvolatile memory cell DMTr1 is in a non-selection state of the write operation, a non-selected memory cell is connected to the control electrode of the dummy nonvolatile memory cell DMTr1 through the dummy word line DWL by the row control circuit 801. The same potential as the potential (for example, 10 V) applied to the control electrode of MTr31 is applied.

In the data write operation of the NAND flash memory, data is not written to the non-selected memory cell. For example, the row control circuit 801 supplies a voltage of 10 V to the unselected word line WL connected to the control electrode of the unselected memory cell MTr31, and a power supply to the unselected bit line BL connected to the drain electrode of the unselected memory cell MTr31. A voltage Vdd is applied. In the non-selected memory cell, no high voltage is generated between the channel region and the non-selected word line. Therefore, electrons are not injected from the channel region into the charge storage layer, and data is not written.

On the other hand, in the data write operation, data is written to the selected memory cell. For example, when information “0” is written in the selected memory cell, the row control circuit 801 applies a voltage of 20 V to the selected word line WL connected to the control electrode of the selected memory cell (not shown), and the bit line side selection transistor. A power supply voltage Vdd is applied to the selection gate line (SGD) connected to the control electrode, and a voltage 0 V is applied to the selection gate line (SGS) connected to the control electrode of the source line side selection transistor 501. A power supply voltage Vdd is applied to the source line, and 0 V is applied to the well region where the memory cell unit is formed. The column control circuit 106 applies 0 V to the selected bit line BL connected to the drain electrode of the selected memory cell (not shown). In the case where a memory cell is configured by a transistor having a charge storage layer (floating gate electrode), a high write voltage is applied between the channel region and the selected word line in the selected memory cell. Electrons as data are injected into the charge storage electrode through the insulating film, and the data is written.

Note that the data write operation is not limited to the above-described operation order. For example, the operation of applying a potential to a dummy nonvolatile memory cell and the operation of applying a potential to a non-selected memory cell may be performed at the same time as soon as any operation is earlier than a write operation to a selected memory cell. It may be broken.

Thus, according to the second embodiment, the nonvolatile semiconductor memory device 800 includes a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and a source between a predetermined number of word lines. A first selection transistor connected to the bit line, a second selection transistor connected to the source line, one end connected to the first selection transistor, and a first control electrode to the word line A memory cell unit having a memory cell column connected in series with a plurality of electrically erasable nonvolatile memory cells having a first charge storage electrode and a first control electrode, and a nonvolatile memory at the other end of the memory cell column And a dummy nonvolatile memory cell electrically connected in series between the memory cell and the second select transistor and having a second charge storage electrode and a second control electrode. In the nonvolatile semiconductor memory device 800, the coupling between the second charge storage electrode and the substrate with respect to the coupling capacitance between the second charge storage electrode and the second control electrode of the dummy nonvolatile memory cell. The capacitance ratio of the capacitance is the capacitance ratio of the coupling capacitance between the first charge storage electrode and the substrate to the coupling capacitance between the first charge storage electrode and the first control electrode of the nonvolatile memory cell. On the other hand, it is small.

Therefore, the nonvolatile semiconductor memory device 800 controls the nonvolatile memory cell (that is, the unselected memory cell) when the nonvolatile memory cell whose one end is connected to the dummy nonvolatile memory cell is in the non-selected state of the data write operation. Even if the same potential as the potential applied to the electrode is applied to the control electrode of the dummy nonvolatile memory cell, the cup between the second charge storage electrode and the second control electrode of the dummy nonvolatile memory cell The capacitance ratio of the coupling capacitance between the second charge storage electrode and the substrate relative to the ring capacitance is such that the first of the coupling capacitance between the first charge storage electrode and the first control electrode of the nonvolatile memory cell. Since the capacitance ratio of the coupling capacitance between the charge storage electrode and the substrate is small, the potential induced in the channel of the non-selected memory cell and the dummy nonvolatile memory cell It is possible to reduce the potential difference between the potential applied to the charge storage electrode. As a result, electrons generated at the drain region end on the channel region side of the dummy nonvolatile memory cell are reduced (to reduce the occurrence of leakage current), thereby preventing injection of electrons into the non-selected memory cell charge storage layer. That is, erroneous writing can be prevented.

In the present embodiment, the case where the coupling capacitance ratio is reduced by increasing the dielectric constant between the substrate and the charge storage electrode by reducing the thickness of the tunnel oxide film has been described as an example. The coupling capacitance ratio may be reduced by using an insulating film such as a silicon nitride film (Si ₃ N ₄ ) having a higher dielectric constant than the silicon oxide film between the substrate and the charge storage electrode.

Further, the coupling capacitance ratio of the dummy nonvolatile memory cell is not limited to 0.4 as described above, and the potential applied to the charge storage electrode of the dummy nonvolatile memory cell depends on the control electrode of the source line side selection transistor. If the coupling capacitance ratio is an intermediate potential between the potential applied to and the potential applied to the control electrode of the memory cell connected to the dummy nonvolatile memory cell, the thickness of the tunnel insulating film between the substrate and the charge storage electrode and Different values may be used depending on the film quality.

1 is an overall circuit diagram of blocks constituting a memory cell array of a NAND flash memory according to a first embodiment of the present invention. 1 is a schematic block diagram of a NAND flash memory according to an embodiment. FIG. 3 is a diagram showing a configuration of a memory cell array shown in FIG. 2. It is sectional drawing which shows an example of the structure of the transistor for a mistake write-in concerning this Embodiment. FIG. 3 is a circuit diagram showing main parts of a memory cell unit according to the present embodiment. It is sectional drawing which shows the structure of the transistor for a mistake write-in concerning Example 1 of this invention. It is sectional drawing which shows the structure of the transistor for incorrect write prevention concerning the other Example of this invention. FIG. 6 is a schematic block diagram of a NAND flash memory according to a second embodiment of the present invention. 1 is an overall circuit diagram of blocks constituting a memory cell array of a NAND flash memory according to an embodiment. It is a circuit diagram for explaining a dummy nonvolatile memory cell according to the present embodiment. It is sectional drawing which shows the dummy non-volatile memory cell vicinity which concerns on this Embodiment. It is a circuit diagram for demonstrating the coupling capacitance ratio of the dummy non-volatile memory cell which concerns on this Embodiment.

Explanation of symbols

100, 800 NAND flash memory 101 Data input / output buffer 102 Command interface 103 Control unit 104 Selection circuit 105, 801 Row control circuit 106 Column control circuit 107 Sense amplifier 108 Block control circuit 109 Intermediate potential control circuit 110 Memory cell array 403, 601 702, erroneous write prevention transistors 403a, 601a, 702a Third control electrode Tr0 Bit line side selection transistor (first selection transistor)
Tr1 Source line side selection transistor (second selection transistor)
Tr2 Miswrite prevention transistor DMTr1 Dummy nonvolatile memory cell C1201 Coupling capacitance between the control electrode and the charge storage electrode of the nonvolatile memory cell C1202 Coupling capacitance between the charge storage electrode of the nonvolatile memory cell and the substrate C1203 coupling capacitance C _r coupling capacitance ratio between the control electrode of the dummy non-volatile memory cell and the charge storage electrode and the substrate of the coupling capacitor C1204 dummy nonvolatile memory cells between the charge storage electrode

Claims (5)

Multiple bit lines,
A plurality of word lines arranged crossing the plurality of bit lines;
Source lines arranged between a predetermined number of word lines;
A first selection transistor connected to the bit line and a second selection transistor connected to the source line; one end connected to the first selection transistor; and a first control electrode connected to the word line A memory cell unit having a memory cell column in which a plurality of electrically erasable nonvolatile memory cells are connected in series, and
The nonvolatile memory cell at the other end of the memory cell column is electrically connected in series between the second select transistor and the nonvolatile memory cell at the other end is in a non-selected state of a data write operation. An intermediate potential between the potential applied to the first control electrode of the nonvolatile memory cell at the other end and the potential applied to the second control electrode of the second select transistor is a third control electrode. A transistor applied to
A semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, further comprising an intermediate potential control circuit that applies an intermediate potential to the third control electrode of the transistor. The nonvolatile memory cell includes a charge storage electrode disposed on a substrate with a first insulating film interposed therebetween, and the first storage layer disposed on the charge storage electrode with a second insulating film interposed. A control electrode,
In the transistor, the first conductive layer in the same layer as the charge storage electrode and the second conductive layer in the same layer as the first control electrode on the first conductive layer are electrically connected. 3. The semiconductor memory device according to claim 1, further comprising three control electrodes. Multiple bit lines,
A plurality of word lines arranged crossing the plurality of bit lines;
Source lines arranged between a predetermined number of word lines;
A first selection transistor connected to the bit line; and a second selection transistor connected to the source line; one end connected to the first selection transistor; and a first control electrode connected to the word line A memory cell unit having a memory cell column connected in series with a plurality of electrically erasable nonvolatile memory cells having a first charge storage electrode and a first control electrode;
A dummy nonvolatile memory electrically connected in series between the nonvolatile memory cell at the other end of the memory cell column and the second selection transistor, and having a second charge storage electrode and a second control electrode A cell, and
The capacitance ratio of the coupling capacitance between the second charge storage electrode and the substrate to the coupling capacitance between the second charge storage electrode and the second control electrode of the dummy nonvolatile memory cell is: With respect to the capacitance ratio of the coupling capacitance between the first charge storage electrode and the substrate to the coupling capacitance between the first charge storage electrode and the first control electrode of the nonvolatile memory cell And a small semiconductor memory device. Multiple bit lines,
A plurality of word lines arranged crossing the plurality of bit lines;
Source lines arranged between a predetermined number of word lines;
A first selection transistor connected to the bit line and a second selection transistor connected to the source line; one end connected to the first selection transistor; and a first control electrode connected to the word line A memory cell unit having a memory cell column in which a plurality of electrically erasable nonvolatile memory cells are connected in series, and
A data write method for a semiconductor memory device, comprising: a transistor electrically connected in series between the nonvolatile memory cell at the other end of the memory cell column and the second selection transistor,
When writing data to the selected nonvolatile memory cell of the memory cell unit, data is not written to the non-selected nonvolatile memory cell of the memory cell unit, and the first of the nonvolatile memory cells An intermediate potential between a potential applied to the control electrode of the transistor and a potential applied to the second control electrode of the second selection transistor is applied to the third control electrode of the transistor. Device data writing method.

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