JP2008102016A - Test pattern creation device, test pattern creation method, and test pattern creation program - Google Patents

Abstract

A test pattern creation device, a test pattern creation method, and a test pattern creation program capable of suppressing an increase in the number of test patterns and detecting a bridge fault and an open fault with high accuracy are provided.
A first test pattern creation / determination module 15 for creating a first test pattern for detecting a bridge fault, a capacity information list creation module 19 for creating a capacity information list, and a stuck-at fault in an input terminal of a logic cell are first. Based on the capacity information list, the determination module 16 for determining whether the test pattern is detected, and how much the wiring area corresponding to the open fault accompanying the stuck-at fault is detected according to whether the stuck-at fault is detected or not detected by the first test pattern And a second test pattern creation / determination module 17 for creating a second test pattern for reducing an undetected wiring area of an open fault accompanying a stuck-at fault that is not detected by the first test pattern. .
[Selection] Figure 1

Description

  The present invention relates to an LSI test pattern creation technique, and more particularly to a test pattern creation device, a test pattern creation method, and a test pattern creation program for detecting a bridge fault and an open fault.

  With the miniaturization of processes and the increase in wiring length, the ratio of bridge faults and open faults in semiconductor integrated circuit (LSI) faults is expected to increase. “Bridge failure” means that signal wires are short-circuited due to foreign matter (dust) adhering to a set of adjacent signal wires (hereinafter referred to as “signal wire pair”). It is a failure that occurs. The “open failure” is a failure that occurs due to a disconnection of a signal wiring or a connection failure in a via (VIA) that connects between wirings through which the same signal propagates.

  In general, a bridge failure is assumed (defined) by extracting adjacent signal wiring pairs from layout information of an LSI to be inspected. Conventionally, a bridge fault detection test for detecting a bridge fault is a static power supply current test (IDDQ (IDDQ)) that is easy to implement for mainstream complementary MOS (CMOS) LSIs (LSIs composed of CMOS circuits). IDDQ Quiescent) test) has been put into practical use. The IDDQ test for a bridge fault is based on the premise that a normal CMOS circuit has no direct current (IDDQ) path and therefore almost no direct current flows in a stable state. Then, a test pattern is created so that the signal propagating through one signal wiring of each signal wiring pair assumed to have a bridge failure is “1” and the signal propagating through the other signal wiring is “0”. The IDDQ test is performed by applying (inputting) a test pattern from the tester to the LSI to be inspected and measuring the value of the direct current (IDDQ) flowing through the LSI. If a bridging fault that is “detected” in the test pattern exists in the LSI (sample) to be inspected, the fault is “activated” and an abnormal IDDQ is measured and detected. As a result, the LSI in which the abnormal IDDQ is detected can be rejected as a defective product. However, along with the miniaturization of the process, the IDDQ value at normal time increases significantly in LSIs that operate at high speed, making it difficult to clearly distinguish between the abnormal IDDQ value and the normal IDDQ value, making it difficult to apply the IDDQ test. It has become.

  Therefore, instead of the abnormal IDDQ value, a test pattern for a bridge fault detection test is applied from the LSI tester to the LSI (sample) to be inspected, and the output (logic) value of the LSI is compared with the expected value to determine the bridge fault. A bridge fault detection test for determining pass / fail is being put into practical use. The test pattern for the bridge fault detection test activates each bridge fault in consideration of the potential when each bridge fault is activated and the presence / absence of propagation according to the input logic threshold of the connected logic cell. A signal that is different from the normal signal due to a bridge failure (hereinafter referred to as “error signal”) is logically propagated outside the LSI and detected. Propagation of an error signal due to a failure in an LSI is called “failure propagation”. The bridge failure detection test using such a “logic level” bridge failure detection test pattern is extremely important as a bridge failure detection test applicable to all LSIs.

For open failure testing, a test pattern for stuck-at fault detection is applied from the LSI tester to the LSI (sample) to be inspected, and the output (logic) value of the LSI is compared with the expected value to check for stuck-at faults. It is expected that an open fault is detected as a secondary by a stuck-at fault detection test (a stuck-at fault test) that performs pass / fail judgment. In the stuck-at fault test, in the case of an LSI manufactured by a non-fine process, each signal inside the LSI, or the input terminal / output terminal of each basic cell is fixed to the power supply potential (V _DD ) or the ground potential (GND). Assuming that stuck-at faults are assumed (referred to as “1 stuck-at fault” and “0 stuck-at fault”, respectively), a test pattern for stuck-at fault detection for detecting these faults is created.

  That is, in the case of an LSI manufactured by a non-fine process, in most open faults, the potential of the signal wiring portion floating due to the open fault is regarded as being stable during the time (about several seconds) during which the test pattern is applied. It is. For this reason, even in the conventional stuck-at fault test, the open fault can be detected to the extent that there is no practical problem. However, as the miniaturization of the process progresses, the number of locations where an open failure may occur inside the LSI increases significantly, and the potential (logic level) of the floating portion of the signal wiring caused by the open failure is adjacent to the floating portion. In many cases, it is strongly influenced by capacitive coupling with the signal wiring. As a result, in the stuck-at fault test, an open fault cannot be detected, and a serious problem in terms of LSI quality control, in which the defective product is found in the market after shipping the LSI, is increasing.

For example, when it is predicted that the logic level of the floating portion of the signal wiring is fixed to 0 (low level) due to an open fault (0 stuck-at fault), an adjacent signal wiring that has a logic level of 1 (high level) by chance The logic level of the floating portion may become 1 due to capacitive coupling. In that case, in the stuck-at fault test for detecting 0 stuck-at fault of the signal wiring, since the signal line is set to 1 in order to generate an error signal due to the fault, an open fault cannot be detected. The probability of missing an open failure for the above reason is 1/2 when assuming that the logic level of the adjacent wiring changes randomly. In a stuck-at fault test that assumes a stuck-at fault at the input terminal / output terminal of each logic cell (hereinafter, simply referred to as “cell”) in an LSI, which is generally used recently, 2 is applied to the input terminal of the cell. A kind of stuck-at fault is assumed. Usually, in order to shorten the test time, once each fault is detected, the presence / absence of fault detection is not evaluated (fault drop). Therefore, in the stuck-at fault test, there is a possibility of overlooking the open fault of the signal wiring portion corresponding to the input terminal of each cell (signal wiring portion connected only to the input terminal) with a probability of (1/2) ² = 1/4. is there.

As a test method for reducing the above-described open failure oversight, an N-time detection test created using a multiple detection function has been proposed (see, for example, Patent Document 2). The “multiple detection function” is a function that creates a plurality of test patterns in which the logical values of the input signals of cells included in the LSI are changed, and detects the same failure a plurality of times. In other words, in the “N-times detection test”, the fault model is a stuck-at fault model, and for each signal wiring location, the surrounding situation such as the logic level of the adjacent wiring is random, and the corresponding stuck-at fault is detected multiple times. Will do. For example, when the corresponding 0 stuck-at fault and 1 stuck-at fault are detected j times and m times for a certain signal wiring location by the N times detection test, the probability of missing an open fault occurring at that location is (1/2). ^{j + m} , and overlooked open failures are greatly reduced (j, m: natural numbers).

However, the N-time detection test is a probabilistic method, and the adjacent wiring that may have an influence by the capacitive coupling on the detection target portion is the wiring, or the logical level of the adjacent wiring is high level or low level. Such information is not used when an open failure is detected. Therefore, there is a problem that the number of test patterns increases in order to detect an open failure with high accuracy. On the other hand, when the number of test patterns is limited for reasons such as test cost restrictions, there is a problem in that it is impossible to determine with high accuracy whether or not an open failure occurring in the LSI can be detected by the N-time detection test.
Japanese Patent Laid-Open No. 2003-194889 JP 2002-090428 A

  The present invention provides a test pattern creation device, a test pattern creation method, and a test pattern creation program that can suppress an increase in the number of test patterns and can detect a bridge fault and an open fault with high accuracy.

  According to one aspect of the present invention, (b) an extraction module that extracts bridge fault information from layout information, and (b) bridge fault information, short information between output terminals of logic cells, and logic of input terminals of the logic cells. A bridge fault list creation module that creates a bridge fault list from threshold information and (c) a bridge fault list is used to detect a bridge fault in an adjacent wiring pair in which the distance between the wirings is within the proximity distance range. Using the first test pattern creation / determination module for creating a test pattern and (d) layout information, information on bridge fault information, adjacent wiring length defined as the wiring length of the adjacent wiring pair, inter-wiring distance and adjacent position are used as information. Capacity information list creation module that creates a capacity information list including, and (e) degeneration assumed for the input terminal of the logic cell Using the determination module that determines whether or not is detected by the first test pattern, and (f) the capacity information list, the logic to which the wiring is connected when one wiring of the adjacent wiring pair is assumed to be open A calculation module for calculating how much a wiring area corresponding to an open fault associated with a stuck-at fault at an input terminal of a cell is detected according to whether a stuck-at fault is detected or not detected by the first test pattern; Detecting an undetected stuck-at fault that is not detected by the first test pattern, and a detected stuck-at fault that has an undetected wiring area with an accompanying open fault, or detecting the undetected wiring area by using a constraint that makes the undetected wiring area small There is provided a test pattern creation device including a second test pattern creation / determination module for creating two test patterns.

  According to another aspect of the present invention, an extraction module, a bridge fault list creation module, a first test pattern creation / judgment module, a capacity information list creation module, a judgment module, a calculation module, a second test pattern creation / judgment module, a bridge A test pattern creation method using a test pattern creation device comprising a fault information storage area, a bridge fault list storage area, and a capacity information list storage area, wherein (a) an extraction module extracts bridge fault information from layout information, and A step of storing in the failure information storage area; and (b) bridge failure information read out from the bridge failure information storage area by the bridge failure list creation module, short information between the output terminals of the logic cells, and logic of the input terminals of the logic cells. From the threshold information The step of creating a failure list and storing it in the bridge failure list storage area, and (c) the first test pattern creation / judgment module uses the bridge failure list read from the bridge failure list storage area, and the distance between wirings is close A step of creating a first test pattern for detecting a bridging fault in an adjacent wiring pair within the distance range; and (d) a capacity information list creation module using the layout information to bridge the bridging fault information and the adjacent wiring pair. A capacity information list including information on adjacent wiring length, distance between wirings and adjacent position defined as length, and storing the capacity information list in a capacity information list storage area; and (e) a determination module at an input terminal of the logic cell. Determining whether an assumed stuck-at fault is detected by the first test pattern; and (f) calculating When a module assumes an open failure in one wiring of an adjacent wiring pair using a capacity information list, a wiring area corresponding to an open failure associated with a stuck-at failure in an input terminal of a logic cell to which the wiring is connected is A step of calculating how much the fault is detected according to detection / non-detection of the stuck-at fault by the first test pattern; and (g) undetected degenerate that the second test pattern creation / determination module is not detected by the first test pattern. Detecting a stuck-at fault in which there is an undetected wiring area of a failure and an accompanying open fault, or creating a second test pattern for reducing the undetected wiring area by using a constraint for reducing the undetected wiring area. A test pattern creation method is provided.

  According to another aspect of the present invention, (b) an instruction for causing the extraction module to extract bridge fault information from the layout information, and (b) a bridge fault list creation module between the bridge fault information and the output terminal of the logic cell. An instruction to create a bridge fault list from the short information and the logic threshold information of the input terminal of the logic cell, and (c) the distance between wirings is close to the first test pattern creation / judgment module using the bridge fault list An instruction to create a first test pattern for detecting a bridge failure in an adjacent wiring pair within the distance range, and (d) a bridge failure information and an adjacent wiring pair wiring by using the layout information in the capacity information list creation module A command for creating a capacity information list including information on adjacent wiring length, wiring distance and adjacent position defined as length; (E) an instruction that causes the determination module to determine whether or not the stuck-at fault assumed at the input terminal of the logic cell is detected by the first test pattern; and (f) an adjacent to the calculation module using the capacity information list When an open failure is assumed in one wiring of a wiring pair, the wiring region corresponding to the open failure associated with the stuck-at failure at the input terminal of the logic cell to which the wire is connected is detected or not detected by the first test pattern. An instruction for calculating how much is detected in response to detection, and (g) undetected stuck-at fault that is not detected by the first test pattern in the second test pattern creation / determination module, and undetected wiring of the accompanying open fault A second test in which a detected stuck-at fault in which an area is detected is detected by using a constraint to reduce the undetected wiring area or the undetected wiring area is reduced Test pattern generation program for executing the instructions to create a turn is provided.

  According to the present invention, it is possible to provide a test pattern creation device, a test pattern creation method, and a test pattern creation program that can suppress an increase in the number of test patterns and can detect a bridge failure and an open failure with high accuracy.

  Next, the first and second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The first and second embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention. The technical idea of the present invention The structure and arrangement are not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
As shown in FIG. 1, the test pattern creation device 1 according to the first exemplary embodiment of the present invention includes an extraction module 13 that extracts bridge fault information from layout information, and bridge fault information between the output terminals of the logic cells. Bridge fault list creation module 14 that creates a bridge fault list from short information and logic threshold information of the input terminals of the logic cells, and adjacent wiring pairs in which the distance between the wirings is within the proximity distance range using the bridge fault list The first test pattern creation / determination module 15 for creating a first test pattern for detecting a bridge fault in the network and the layout information, the bridge fault information, the adjacent wiring length defined as the wiring length of the adjacent wiring pair, the wiring A capacity information list creating module 19 for creating a capacity information list including information on the distance and the adjacent position; An open fault is assumed for one of the adjacent wiring pairs by using the determination module 16 for determining whether or not the stuck-at fault assumed at the input terminal of the logic cell is detected by the first test pattern and the capacity information list. In this case, the extent to which the wiring area corresponding to the open fault associated with the stuck-at fault at the input terminal of the logic cell to which the wiring is connected is detected according to the detected / undetected stuck-at fault by the first test pattern The detection stuck fault that is not detected by the calculation module 18 to be calculated and the first test pattern and the accompanying open fault undetected wiring area is detected or not detected by using the constraint to reduce the undetected wiring area. A second test pattern creation / determination module 17 for creating a second test pattern for reducing the detection wiring area;

  Here, the “proximity distance” is a distance that is set in advance as a distance between wiring lines where a bridge failure occurs. For example, based on the measurement result such as the distribution of the bridging fault occurrence rate with respect to the inter-wiring distance, the inter-wiring distance at which the bridging fault occurrence rate per unit adjacent wiring length becomes a certain probability or more is defined as the proximity distance. The bridging fault occurrence rate depends on the adjacent wiring length and the inter-wiring distance between the wiring pairs. In general, the longer the adjacent wiring length and the shorter the inter-wiring distance of the wiring pair, the higher the bridging fault occurrence rate. The bridging fault occurrence rate is calculated from the evaluation result of the test element group (TEG) created for examining the basic device characteristics in the process applied to the manufacture of the LSI, the bridging fault inspection result of the LSI manufactured in the past, and the like. .

  The “proximity distance” is based on the minimum wiring interval or an appropriate unit interval (such as 0.1 μm) of the LSI (hereinafter referred to as “target LSI”) that is the object of the bridge failure detection test and the open failure detection test. It may be defined. For example, an integral multiple of the minimum wiring interval is defined as the proximity distance. Alternatively, the proximity distance may be defined based on the dust size distribution information detected in the process applied to the production of the target LSI. For example, the size of dust including 95% of the total distribution can be defined as the “maximum” proximity distance, and the proximity distance can be defined by dividing the maximum proximity distance into an appropriate number. The dust size distribution can be obtained from a dust inspection result in a process of a product manufactured in the past by applying the same process as that of the target LSI. The “adjacent wiring length” is the wiring length of an adjacent wiring pair whose inter-wiring distance is within the proximity distance range.

  The extraction module 13, the bridge fault list creation module 14, the first test pattern creation / determination module 15, the determination module 16, the second test pattern creation / determination module 17, the calculation module 18 and the capacity information list creation module 19 are a central processing unit. (CPU) 10 included. The CPU 10 further includes a short information creation module 11, a threshold information creation module 12, and a stuck-at fault list creation module 20.

  The short information creation module 11 assumes a short circuit between two output terminals of any two cells (or the same cell), and indicates a relationship between the logical value of the input signal of each cell and the potential of the assumed short point. Create information. The threshold information creation module 12 calculates the logical threshold value of the input terminal of the cell and creates logical threshold information. The stuck-at fault list creation module 20 creates a pin stuck-at fault list including stuck-at faults assumed at the input / output terminals of the cells.

  The bridging fault list creation module 14 uses the bridging fault information, the short information about the driving cell and the receiving cell, and the logic threshold information to determine the relationship between the potential of the shorted portion and the logical threshold value of the input terminal of the receiving cell. A bridging fault list is created that includes the bridging fault types to be propagated and the propagation accuracy that can be propagated across the receiving cell if the bridging fault is activated. The bridge fault list does not describe a bridge fault having a propagation accuracy of 0 (or almost 0). Here, the “driving cell” is a cell that drives an adjacent wiring pair, and the “receiving cell” is a cell that receives a signal that propagates through the adjacent wiring pair.

  Further, the determination module 16 performs a stuck-at fault simulation using the first test pattern for the LSI, and determines whether the stuck-at fault assumed at the input terminal of the cell is detected by the first test pattern. To do. The function of the determination module 16 can be included in the second test pattern creation / determination module 17. The calculation module 18 corresponds to the fault detection rate of the first test pattern in which the bridge fault determined to be detected by the first test pattern is weighted by the above propagation accuracy and the wiring length, and the bridge fault determined to be undetected. Similar weights are calculated. Further, as described later, when an open failure is assumed, the size of the detection wiring region (detection wiring portion) or the non-detection wiring region (non-detection wiring portion) of the open failure detected by the first test pattern is calculated. Also do.

  The test pattern creation device 1 further includes a storage device 200, an input device 30, an output device 40, a short information library 51, and a threshold information library 52. The short information library 51 stores short information between each one output of any two cells of a plurality of cells. The threshold information library 52 stores logical threshold information of a plurality of cells for each input terminal. The cell library 2 shown in FIG. 1 stores a model for circuit simulation of a plurality of cells. Also included are models for automatic test pattern generation (ATPG), fault simulation, and logic simulation.

  The storage device 200 includes a layout information storage area 201, a proximity distance storage area 202, a simulation data storage area 203, a simulation result storage area 204, a bridge fault information storage area 205, a bridge fault list storage area 206, a test pattern storage area 207, a fault A detection information storage area 208, a result report storage area 209, a failure detection rate storage area 210, a capacity information list storage area 211, a pin stuck-at fault list storage area 212, an undetected fault storage area 213, and a signal logical value information storage area 214 are provided. .

  The layout information storage area 201 stores layout information of the target LSI. The layout information includes detailed arrangement and connection information such as cells, wirings, and vias used in the target LSI, wiring layer information, and the like. Normally, the layout information is complete information by combining with design rules such as cell shape, terminal position information, and wiring interval.

  The proximity distance storage area 202 stores a preset proximity distance. The simulation data storage area 203 stores a circuit description for circuit simulation of a cell read from the cell library 2 and an operation model for circuit simulation of an element used in the circuit description. The device circuit simulation model may be stored and managed separately from the cell circuit simulation circuit description. The simulation result storage area 204 stores the execution result of the circuit simulation. The bridging fault information storage area 205 stores bridging fault information extracted from the layout information. The bridge failure list storage area 206 stores a bridge failure list. The test pattern storage area 207 stores test patterns to be applied to the target LSI. The failure detection information storage area 208 stores failure detection information created by executing test pattern creation and failure simulation. The result report storage area 209 stores an execution result report when a test pattern and failure detection information are created. The failure detection rate storage area 210 stores the failure detection rate of the test pattern. The capacity information list storage area 211 stores a capacity information list. The pin stuck-at fault list storage area 212 stores a pin stuck-at fault list. The undetected fault storage area 213 stores undetected stuck-at faults and undetected bridge faults that are not detected by the first test pattern, and further stores undetected stuck-at faults and undetected bridge faults according to the second test pattern. . The signal logical value information storage area 214 stores the logical value of the signal in the target LSI for the first test pattern and the second test pattern.

  The input device 30 includes a keyboard, a mouse, a light pen, a flexible disk device, or the like. A test pattern creation executor can specify layout information and proximity distance from the input device 30. Also, it is possible to input an instruction to execute or cancel test pattern creation.

  As the output device 40, a display or printer that displays an execution result report, a failure detection rate, or the like, or a recording device that stores data in a computer-readable recording medium can be used. Here, the “computer-readable recording medium” means a medium that can record electronic data, such as an external memory device of a computer, a semiconductor memory, a magnetic disk, and an optical disk. Specifically, a “flexible disk, CD-ROM, MO disk, etc.” are included in the “computer-readable recording medium”.

  An example of a bridge failure will be described with reference to FIG. FIG. 2 shows a wiring L01 that connects the first driving cell CD1 and the first receiving cell CR1, and a wiring L02 that connects the second driving cell CD2, the second receiving cell CR2, and the third receiving cell CR3. This is an example of short-circuiting by the resistor R. The signal S11, the signal S12, and the signal S13 are input to the first driving cell CD1, and the first driving cell CD1 outputs the signal S10 to the first receiving cell CR1. The signal S21 and the signal S22 are input to the second drive cell CD2, and the second drive cell CD2 outputs the signal S20 to the second reception cell CR2 and the third reception cell CR3. Signals S31 and S32 are further input to the first reception cell CR1, and the first reception cell CR1 outputs a signal S30. The signal S41 is further input to the second reception cell CR2, and the second reception cell CR2 outputs the signal S40. The third reception cell CR3 outputs a signal S50.

Whether the bridge fault indicated by the resistor R and activated can propagate to the output terminal of the target LSI via the first reception cell CR1, the second reception cell CR2, or the third reception cell CR3. Are the potential V1 at the connection point P1 between the wiring L01 and the resistor R, the potential V2 at the connection point P2 between the wiring L02 and the resistance R, the logical threshold value of the input terminal of the first reception cell CR1, and the second reception cell. It depends on the relationship between the logic threshold value of the input terminal of CR2 and the logic threshold value of the input terminal of the third reception cell CR3. For example, when the signal S10 is at a low level (logic value 0) and the signal S20 is at a high level (logic value 1), the potential V1 is equal to or higher than the logic threshold value of the input terminal of the first reception cell CR1. The output state of the first reception cell CR1 changes to a state different from the normal state. That is, an error signal due to the activated bridge fault can be propagated to the output terminal of the target LSI via the first reception cell CR1. That is, a bridge fault can be detected. (Depending on the logic values of the signals S31 and S32, the signal of S10 may not be able to propagate to S30, but this is considered to be that there is no input logic threshold, and so on.)
The test pattern for detecting the bridge fault corresponding to the propagated error signal is basically an automatic test pattern generation tool (propagating the error signal actually generated by activating each bridge fault to the output terminal of the target LSI. ATPG tool). However, when the signal S10 is at a low level and the signal S20 is at a high level, if the potential V1 is smaller than the logical threshold value of the input terminal of the first receiving cell CR1, a bridge fault is the output of the first receiving cell CR1. This state cannot be changed to a state different from the normal state, and the error signal does not propagate to the output terminal of the target LSI. That is, the bridge failure is not detected via the first reception cell CR1. In that case, if the potential V2 is equal to or lower than the logical threshold value of the input terminal of the second reception cell CR2 or the third reception cell CR3, the error signal due to the activated bridge fault is the second reception cell CR2 or The signal can be propagated to the output terminal of the target LSI via the third reception cell CR3. That is, a bridge fault can be detected by an appropriate test pattern in which an error signal is propagated to the output terminal via the target LSI.

  Whether or not the output state of the first reception cell CR1 changes when the bridge fault indicated by the resistor R in FIG. 2 is activated depends on the logical value of the signal S31 input to the first reception cell CR1. May also depend. For example, when the first receiving cell CR1 is a composite logic gate, the logic threshold value of the input terminal of the first receiving cell CR1 to which the signal S10 is input can be changed according to the logic values of the signals S31 and S32. There is sex. Note that the potential V1 and the potential V2 are the magnitude of the resistance R, the signal S11 input to the first drive cell CD1, the logical values of the signals S12 and S13, and the signal S21 and signal input to the second drive cell CD2. Depends on the logical value of S22.

  As described above, when the signal S10 and the signal S20 are set to different logical values and the bridge fault between the wiring L01 and the wiring L02 is activated, the error signal is transmitted to the first receiving cell CR1 and the second receiving cell CR1. It can be propagated to the output terminal of the reception cell CR2 or the third reception cell CR3. When the error signal propagates to the output terminal of the target LSI, a bridge failure between the wiring L01 and the wiring L02 is actually detected. Note that the combination of the sub-input signals of the receiving cell may affect whether or not a bridge fault propagates in the LSI. The “sub input signal” is an input signal of a cell other than the error signal.

  The short information generation module 11 targets all combinations of drive cells that can drive a wiring pair, and logic values of arbitrary two output signals of the same or different drive cells and logic values of other input signals of the drive cells. In consideration of the above, the potential of the shorted portion assumed in the wiring pair is calculated by circuit simulation, and a short information group is created. A method of creating the short information group by the short information creating module 11 will be described using the flowchart shown in FIG.

  (A) In step S 01, the short information creation module 11 reads the circuit description for cell circuit simulation and the operation model for circuit simulation of the elements used in the circuit description from the cell library 2, and stores them in the simulation data storage area 203. Store.

  (B) In step S02, the short information creation module 11 creates a circuit simulation netlist in which any two cell outputs stored in the simulation data storage area 203 are short-circuited via the resistor R. The created netlist includes input patterns necessary for circuit simulation. The created netlist includes a netlist obtained by shorting two outputs of the same cell. The short information creation module 11 executes circuit simulation for all combinations of possible inputs for the created netlist. Basically, the circuit simulation is executed by setting the resistance value of the resistor R to 0, but the resistance value of the resistor R may be set to other than 0. The execution result is stored in the simulation result storage area 204.

  (C) In step S03, the short information creation module 11 reads out the execution result of the circuit simulation from the simulation result storage area 204. The short information creation module 11 extracts the value of the potential of the assumed short location (short potential) together with the input of the corresponding two cells from the execution result of the circuit simulation using the net list assuming the short circuit between the wirings. Information such as the extracted short potential is stored in the short information library 51 as short information.

  The short information creation module 11 creates the short information described above for all combinations of arbitrary two cell outputs included in the cell library 2. Creating short information generally requires a lot of CPU time, but once a short information library is created for a cell library, if another target LSI uses the same cell library There is no need to create it again. If it is difficult to completely create a short information library due to time constraints, short information may be created only for cells used in the target LSI. A format example of the short information is shown in FIG. As shown in FIG. 4, short information is created for all combinations of cell A input and cell B input. The item “input frequency” shown in FIG. 4 indicates how many combinations of substantially the same input in cell A or cell B exist. The combinations of inputs may be appropriately grouped based on the result of circuit simulation (short potential or logic threshold), but as shown in FIGS. 5 and 6, using information on the cell configuration, In some cases, grouping is possible in advance. When grouping of combinations of inputs is possible in advance, the circuit simulation can be performed only for representative inputs of each group, so that the CPU time can be considerably reduced. Here, “information on the cell configuration” depends on the cell library. For example, an AND / OR gate uses the same gate size for all inputs, and an AND / OR gate has an output buffer. Information indicating that the driving force is the same for any input if the output logical value is the same.

  FIG. 6 shows grouping information obtained by grouping combinations of inputs of the NAND circuit that inputs the input signals A, B, and C shown in FIG. 5 and outputs the output signal Z. When the combinations of inputs of the NAND circuit are substantially the same from the viewpoint of the load driving force of the output signal, they are classified into the same group. As shown in FIG. 6, the number of groups of NAND circuits in which the logical value of the output signal Z is 1 is 3. Group 1 includes input combinations in which only input signal A, only input signal B, or only input signal C is 0, and the input frequency is 3. Group 2 includes input combinations in which only input signal A, only input signal B, or only input signal C is 1, and the input frequency is 3. Group 3 is an input combination in which all of the input signals A, B, and C are 0, and the input frequency is 1. The logical value of the output signal Z of the NAND circuit is 0 because the input signals A, B, and C are all input combinations of 1 and the input frequency is 1.

  In the same group, the short potential and the current value (short current value) flowing in the short location are almost the same, so it may be determined whether or not a bridge fault can be detected for one input combination in the group. In other words, using grouping information is important for reducing the overall calculation amount and ensuring high accuracy within the allowable calculation amount range. By the way, generally, the load driving force of cells such as NAND circuits and NOR circuits varies depending on the input. For example, in the group shown in FIG. 6, the load driving force is larger in the order of group 3, group 2, and group 1. However, since cells such as an AND circuit and an OR circuit have a buffer for increasing the load driving force at the output portion, it should be noted that the load driving force is the same when outputting the same logical value.

  In addition to basic cells such as an AND circuit and a NOR circuit, there may be a bridge failure with the output terminal of a large hard macroblock such as a memory. Therefore, a hard macroblock may be a bridge failure detection target. When memory is targeted for bridging fault detection, a simplified netlist that omits the description of the memory cell part and extracts only necessary parts such as address input and data output buffers (including output enable signals) It is efficient to use it for circuit simulation.

  A method in which the threshold information creation module 12 creates the logical threshold information of the cell input terminal will be described below. If the cell is a combinational circuit, circuit simulation is performed by changing the input potential of any one input of each input group of the cell very little, and the input potential when the output logic value changes is the logic threshold value. It is defined as In the case of memory circuits such as flip-flops and latches, data is taken in at the edge of the clock signal. Therefore, a circuit simulation is performed when the input potential of the data input is slightly different, and the logic value of the output changes. The input potential of data input is defined as a logic threshold value. The extracted threshold information is stored in the threshold information library 52. Threshold information also requires a lot of CPU time to create, but as with short information, once a threshold information library has been created for a certain cell library, another target LSI will then have the same cell. If you are using a library, you do not need to create it again.

  Next, a description will be given of a method in which the extraction module 13 extracts bridge fault information relating to adjacent wiring pairs within the set proximity distance range from the layout information of the target LSI. The extraction module 13 obtains the adjacent wiring length of the adjacent wiring pair, the signal information of the adjacent wiring pair, and the adjacent wiring pair whose inter-wiring distance is within the adjacent distance range from the wiring position and connection detailed information included in the layout information of the target LSI. Bridge fault information including drive cell information relating to each drive cell to be driven and reception cell information relating to a receive cell to which a signal propagating through an adjacent wiring pair is input is extracted. “Signal information” is a detailed name in the target LSI of a signal propagating through each adjacent wiring pair. The drive cell information includes the terminal name (drive terminal name) of the drive terminal that outputs a signal to the adjacent wiring pair. In order to perform more advanced processing, the drive cell information may include the input terminal name of the drive cell. The reception cell information includes the terminal name (reception terminal name) of the reception terminal to which the signal propagating through the adjacent wiring pair is input.

  A format example of the bridging fault information is shown in FIG. The bridge fault information shown in FIG. 7 includes the detailed names including the module hierarchy in the net list of the wiring through which the signals A and B propagate, the adjacent wiring length L, and the driving terminal that outputs a signal to each adjacent wiring pair. It consists of the details related to the receiving cell including the terminal name (driving terminal name) and the terminal name (receiving terminal name) of the receiving terminal to which each signal propagating in the adjacent wiring pair is input. The “instance name” shown in FIG. 7 is a cell identification name in the net list of the target LSI. In some cases, a plurality of tri-state buffers may be connected to a bus or the like, and the enable terminal name is included in the bridge fault information together with the drive terminal name because of the necessity of determining the drive cell causing the bridge fault. I am doing so.

  The bridge fault information may be divided into two types of files whose format examples are shown in FIGS. FIG. 8 is a file describing signal information and adjacent wiring length included in the bridge fault information shown in FIG. FIG. 9 is a file describing information on the drive cell and drive terminal name, and the reception cell and reception terminal name included in the bridge failure information shown in FIG. By dividing the bridge fault information, the file size of the bridge fault information can be reduced as a whole, which is effective when extracting bridge fault information of a large-scale LSI.

  Next, a method in which the bridge failure list creation module 14 creates a bridge failure list will be described. The bridge fault list creation module 14 assumes the drive line information and the received cell information included in the bridge fault information stored in the bridge fault information storage area 205 and the adjacent line pair included in the short information library 51 for each adjacent line pair. The short circuit potential due to the bridge fault is acquired, and a bridge fault list is created. Furthermore, the logical threshold value of the receiving terminal included in the logical threshold information library 52 may be acquired and added as an item to the bridge fault list. FIG. 10 shows a detailed format example of a bridge fault list related to a bridge fault assumed in an adjacent wiring pair composed of a wiring through which the signal A propagates and a wiring through which the signal B propagates. The bridge fault type, relative occurrence probability, propagation probability, and detection accuracy included in the detailed format shown in FIG. 10 will be described below.

  “Bridge fault type” is a type of bridge fault determined by the relationship between the short-circuit potential and the logical threshold value of the input terminal of the receiving cell. FIG. 11 shows an example of a bridge fault type when a bridge fault is assumed between the output terminal of the cell CA that outputs the signal A and the output terminal of the cell CB that outputs the signal B. In the example shown in FIG. 11, the bridge failure type includes a wired-AND (WA) type, a wired-OR (Wired-OR: WO) type, an A-Dominate (AD) type, and a B-Dominate (B). -Dominate: BD) is an example of classification. In the WA type, the logical value of the propagating bridge fault is the logical product of the logical value of the signal A and the logical value of the signal B. In the WO type, the logical value of the propagating bridge fault is the logical sum of the logical value of the signal A and the logical value of the signal B. In the AD type, the logical value of the propagating bridge fault is the logical value of the signal A. For example, when the load driving force of the cell CA is larger than the cell CB, the bridge failure type is an AD type. In the BD type, the logical value of the propagating bridge fault is the logical value of the signal B. When the load driving force of the cell CB is larger than the cell CA, the bridge failure type becomes the BD type. The bridge fault type is determined by the relationship between the short potential and the logical threshold value of the receiving terminal. Therefore, even if a bridge failure occurs at the same location, the bridge failure type may vary depending on the combination of input signals of the driving cells and the logical threshold value of the input terminal of the receiving cell. Although not described in detail here, there is also a method of classifying the bridge fault type according to the intensity of the signal A and the signal B instead of the above WA type, WO type, AD type and BD type. The concept of the present embodiment is also effective in the method of classifying the bridge fault type according to the intensity of the signal A and the signal B.

  “Relative occurrence probability” is the probability that a specific combination of inputs will occur. Here, the value obtained by dividing the input frequency of the combination of input signals of the cells that output signal A and signal B by the number of all possible combinations. Relative occurrence probability. More precisely, the relative occurrence probability may be calculated by strictly calculating the probability that the logical value of each input signal is 0 or 1. That is, the relative occurrence probability increases as the input signal combination has a higher input frequency.

  “Propagation probability” is the probability that an error signal is propagated to the output of the receiving cell (appears at the output of the receiving cell) when a bridge fault is activated. In other words, the propagation probability is the probability that an error signal due to the bridge fault can propagate in the LSI according to the test pattern created for the bridge fault detection by the ATPG tool, and the short-circuit potential and the logical threshold of the receiving terminal Depends on the relationship. That is, the propagation probability depends on the bridge fault type. Hereinafter, the propagation probability will be described by taking as an example a case where the logical value of a signal having a logical value of 1 at normal time becomes 0 due to a bridge failure. When the short potential is lower than the logical threshold value of the receiving terminal, an error signal due to the activated bridge fault propagates to the output terminal of the receiving cell, and the error signal passing through the receiving cell propagates in the LSI. That is, the first test pattern creation / judgment module 15 succeeds in creating a test pattern for bridge failure detection of the target LSI, and the error signal generated by the bridge failure set as “detection” is actually propagated in the LSI and transmitted to the LSI. To the output terminal. As a result, the bridging fault determined as “detection” is actually detected by the first test pattern.

  On the other hand, when the short potential is higher than the logical threshold value of the receiving terminal, the error signal generated due to the bridge failure is not propagated to the output terminal of the receiving cell, and the error signal cannot propagate through the LSI. That is, even if a bridge failure is determined as “detected” by the first test pattern creation / determination module 15, the error signal does not propagate in the LSI via the reception cell, so the error signal reaches the output terminal of the LSI. Can not. As a result, the bridge fault determined as “detected” in the first test pattern is not actually detected.

FIG. 12A shows an example of short potential distribution, and FIG. 12B shows an example of logical threshold distribution. In the example of the short potential and logic threshold distribution shown in FIGS. 12A and 12B, there is no short potential lower than the logic threshold distribution. Therefore, a bridge fault of a bridge fault type in which the logical value of a signal having a normal logic value of 1 becomes 0 due to a bridge fault is blocked by the receiving cell and cannot propagate through the LSI. That is, the propagation probability is zero. In that case, if the logic value of a signal whose logical value is 0 at normal time is a bridge fault of a bridge fault type in which the logical value of the signal is 1 due to a bridge fault, an error signal can propagate through the LSI via the receiving cell. The propagation probability is 1. In FIGS. 12A and 12B, the potential V _DD is the power supply voltage of the target LSI.

  In the example of the short potential and logic threshold distribution shown in FIGS. 13A and 13B, there is a short potential that overlaps the logic threshold distribution. In other words, even if the bridge logic is a bridge fault type in which the logical value of the signal that is 0 at normal time is 1 due to a bridge fault, or the logical value of the signal that is 1 at the normal time is a bridge fault type in which the logical value of the signal that is 1 is 0. Even if there is a bridge failure, the bridge failure may be able to propagate through the LSI via the receiving cell. That is, the propagation probability is greater than zero.

  Furthermore, although not shown, there may be a case where there is no short potential higher than the distribution of logic threshold values. In this case, a bridge fault of a bridge fault type in which the logical value of a signal that is 0 at normal time becomes 1 due to a bridge fault is blocked by the receiving cell and cannot propagate through the LSI. That is, the propagation probability is zero. On the other hand, if the logic value of a signal that is 1 at normal time is a bridge failure of a bridge failure type that becomes 0 due to a bridge failure, an error signal can propagate through the receiving cell and the propagation probability is 1 It becomes. For a bridge fault due to the same adjacent wiring pair, the propagation probability of a bridge fault of a bridge fault type in which the logical value of a signal that is 0 when normal is 1 due to the bridge fault and the logical value of a signal that is 1 when normal is a bridge The sum of propagation probabilities of bridge faults of a bridge fault type that becomes 0 by a fault is 1.

  “Detection accuracy” indicates the accuracy with which the bridge failure that is “detected” by the first test pattern creation / determination module 15 is a bridge failure that is actually detectable that propagates through the LSI. The first test pattern creation / determination module 15 creates a test pattern so that a bridge fault is detected based only on the bridge fault type and the logical connection information of the circuit, and determines the presence or absence of detection. Therefore, the error signal generated by the bridge failure determined as “detected” by the first test pattern creation / determination module 15 is not propagated to the output terminal of the LSI due to the relationship between the short potential and the logic threshold value of the receiving cell. A bridge failure may not be detected. Therefore, the detection accuracy can be used for proper evaluation of the failure detection rate of the test pattern.

A method for calculating the detection accuracy when the logical value 1 of a normal signal becomes a logical value 0 due to a bridge failure will be described below. Here, the ratio of the frequencies of the short potentials V _{s1 to} V _sn of the input group 1 to the input group n with respect to all short potentials at which bridge failure of each signal of each adjacent wiring pair is possible is defined as a relative frequency fV _{s1 to} fV _sn ( n: natural number). The ratio of the logic threshold frequency greater than the short potential V _si to the input logic thresholds V _{TH1 to} V _THm of the bridge failure receiving cell is _defined as a relative frequency fV _THi (m: natural number). The detection accuracy T _DT is calculated by the following equation (1):

T _DT = Σ _i {fV _si × (fV _THi / fV _THall )} / Σ _i fV _si (1)

In equation (1), Σ _i means the sum from i = 1 to n. fV _THall is the sum of the relative frequencies of the logical thresholds of the received cells.

In the above, an example has been described in which the logical value of a signal that is 1 when normal is 0 due to a bridge failure. The detection accuracy of other bridge faults is calculated in the same manner, for example, when the logical value of a signal that is 0 at normal time becomes 1 due to a bridge fault. For example, as the relative frequency fV _THi , a logic threshold frequency ratio smaller than the short potential V _si may be used.

  As described above, the logical value of the bridge fault propagating in the LSI is determined by the bridge fault type determined by the relationship between the short potential and the logical threshold value of the receiving terminal. In order to determine the bridge fault type more simply, an appropriate value may be set as the logical threshold value of the receiving terminal.

For example, it is possible to set a half value of the power supply voltage V _DD of the target LSI as the logical threshold value of the receiving terminal. In this case, however, the reliability of the determination result of the bridge fault detection by the first test pattern creation / determination module 15 may be lowered. Alternatively, an appropriate logic threshold value may be set by examining the frequency distribution of the logic threshold values of the input terminals of all cells included in the target LSI. Furthermore, the frequency distribution of the logic threshold values of the input terminals of all cells is used in place of the frequency distribution of the logic threshold values of the receiving cell corresponding to each bridge fault, and the detection accuracy of each bridge fault type according to equation (1). You may ask for. In that case, the logic threshold distribution is common to all bridge faults. The merit of these methods is that it is not necessary to extract the detailed information of the receiving cell corresponding to each bridging fault. Therefore, in a large-scale LSI, the CPU time can be greatly saved, and a certain degree of accuracy can be expected. It is. However, in a large-scale LSI, there is a possibility that the distribution of the logic threshold value may vary, and as described above, it is possible to calculate the logic threshold value distribution of the receiving terminal corresponding to the bridge failure in each adjacent wiring pair. It may be desirable.

  The first test pattern creation / determination module 15 creates a first test pattern for detecting a bridge fault for an adjacent wiring pair and a bridge fault type included in the bridge fault list, and determines the presence or absence of detection. Specifically, the first test pattern creation / determination module 15 creates a first test pattern in consideration of the bridge fault type determined for the bridge fault in each adjacent wiring pair, and determines the presence or absence of detection. . Since the bridge fault type determined by the relationship between the short potential and the logical threshold value of the input of the receiving cell is used, a first test pattern for accurately detecting a bridge fault propagating in the LSI is created.

  The first test pattern creation / determination module 15 also assists in determining whether or not there is a secondary detection of a bridge fault other than the bridge fault in the target LSI directly detected by the ATPG tool for each of the first test patterns. Fault simulation can also be performed. The first test pattern creation / determination module 15 determines whether or not a bridge fault in each adjacent wiring pair included in the bridge fault list can be detected by the first test pattern based on the connection information of the target LSI. Create discovery information. The fault detection information includes the bridge fault type of each bridge fault. Further, the first test pattern creation / determination module 15 creates an execution result report. The execution result report includes the execution log of the first test pattern creation and auxiliary fault simulation, the number of patterns of the first test pattern, the faults by total and bridge fault types obtained by the first test pattern creation and auxiliary fault simulation. Includes detection rate, number of detections, number of undetected, redundant faults, etc. “Redundant failure” will be described later.

  When the first test pattern creation / determination module 15 detects any of the bridge fault types in each adjacent wiring pair, the first test pattern creation / determination module 15 treats other bridge fault types in the same adjacent wiring pair as detections depending on the detection accuracy. It is desirable to have a function to With this function, bridge faults (types) for which test patterns are to be created are efficiently reduced with the progress of test pattern creation, and the first effective in less CPU time while ensuring high detection accuracy. Test patterns can be created.

The first test pattern creation / determination module 15 preferably has a detection function of multiple times in order to execute the N-time detection test. For example, in the case of a test pattern in which a bridge failure is detected n times for the same adjacent wiring pair, the probability that a bridge failure in the adjacent wiring pair is detected in the bridge failure detection test of the actual target LSI is “1- {1− (detection accuracy T _{DT in} each pattern)} ⁿ ”. That is, the greater the number of detections n, the higher the possibility that a bridge fault will actually be detected by the bridge fault detection test. Also, the higher the detection accuracy T _DT in one pattern, it is possible to detect the bridge fault with a small number of detection times. Furthermore, by setting so that the number of detections is increased for those with low detection accuracy (so that more detection is required to remove them from the detection target), a first test pattern with higher quality can be efficiently obtained. be able to.

Here, the detection accuracy of p bridge faults determined as “detected” by the first test pattern creation / determination module 15 is DT _DT1 to DT _DTp , and the number of bridge fault detections is N1 to Np (p: Natural number). The detection accuracy DT _{DT1 to} DT _DTp is a detection accuracy that _combines the detection accuracy of each bridge fault type. The calculation module 18 calculates the bridge fault detection rate FC (Fault Coverage) of the first test pattern weighted by the detection accuracy using the following equation (2):

FC = Σ _k {1- (1-DT _DTk ) ^Nk } / (AD-DD) (2)

In Equation (2), Σ _k is the sum from k = 1 to p, AD is the total number of bridge faults included in the bridge fault list, and DD is the number of redundant faults. In detail, “detection” includes “potential detection” (when an indefinite value is detected due to a failure) and the like, and detailed handling is required, but it is not related to the essence of the present invention, so here The description is omitted. Further, considering the adjacent wiring lengths WL _{1 to} WLp as weights, the bridge failure detection rate FC_WL of the first test pattern weighted by the detection accuracy and the adjacent wiring length may be calculated using Expression (3):

FC_WL =
Σ _k WL _k {1- (1-DT _DTk ) ^Nk } / (AD_WL−DD_WL) (3)

In Expression (3), AD_WL is the total wiring length of bridge faults included in the bridge fault list, and DD_WL is the total wiring length of redundant faults. Since the bridge fault occurrence rate is generally proportional to the adjacent wiring length, a high-accuracy quality index having a stronger correlation with the actual bridge fault occurrence rate based on the bridge fault detection rate FC_WL calculated using Equation (3). Can provide. Note that the weight of the undetected fault can be calculated by the same weighting, which is effective information for improving the test quality efficiently.

  An example of a redundant failure in a bridge failure is shown by hatched portions in FIGS. FIG. 14 shows a wiring 311 and a wiring 312 through which the signal SA1 and the output signal SA2 of the buffer circuit 310 that transfers the signal SA1 without level conversion are respectively transmitted. Since the signal SA1 and the signal SA2 are always at the same level value, a bridge failure between the wiring 311 and the wiring 312 cannot be detected.

  FIG. 15 shows a wiring 321 through which the signal SB1 input to the AND circuit 320 propagates, a wiring 322 through which the signal SB2 propagates, and a wiring 324 through which the signal SB3 input to the buffer circuit 323 propagates. The output signal of the buffer circuit 323 does not propagate to other circuits and is not output to the external terminal of the LSI. Therefore, when there is only a possibility that an error signal due to a bridge failure occurring between the wiring 321 and the wiring 324 propagates through the buffer circuit 323, a bridge failure between the wiring 321 and the wiring 324 cannot be detected.

  Next, capacitive coupling between adjacent wiring pairs that affects open failure detection in adjacent wiring pairs will be described. The open failure of the wiring is affected by the capacitive coupling, and even if it is an open failure in the same wiring, the way in which the influence appears (whether or not the failure propagates, the route, etc.) differs depending on the occurrence location.

  The influence of the capacitive coupling of the adjacent wiring pair on the logic level of the cell output terminal depends on the relationship between the position of the open fault in the wiring connected to the input terminal of the cell and the position of the adjacent wiring. Taking the logic gate G and the wiring LA connected to the input terminal Ga of the logic gate G shown in FIG. 16 as an example, the position where the open failure occurs in the wiring LA (indicated by “X” in FIG. 16), the logic gate The relationship with the logic level of the output terminal Gz of G will be described. As shown in FIG. 16, the wiring length of the wiring LA from the input terminal Ga to the position of the open failure (hereinafter referred to as “open wiring length”) is L. In addition, the wiring LB is adjacent to the wiring LA with a distance D between wirings from the position x1 to the position x2 of the wiring LA. The distances from the input terminal Ga to the position x1 and the position x2 are the distance L1 and the distance L2, respectively (L1 <L2). The distance between the position x1 and the position x2, that is, the adjacent wiring length of the wiring LA and the wiring LB is LM.

Here, the capacitance with respect to the ground line L _GND of the wiring LA with the open wiring length L, that is, the capacitance to the ground is C _GND (L), and the capacitance with respect to the power supply line L _VDD , that is, the capacitance to the power supply is C _VDD (L). And C _GND (L) and C _VDD (L) are capacitance values depending on the open wiring length L. When the earth capacitance per unit length of the wiring LA C _{GND_0,} a pair power capacity and C _{VDD_0,} C _GND (L) and C _VDD (L) are represented respectively by the following formulas (4) and (5) :

C _GND (L) = C _GND — ₀ × L (4)
C _VDD (L) = C _VDD — ₀ × L (5)

In the equations (4) and (5), it is assumed that the ground layout of the wiring LA is uniform and the ground capacitance and the power supply capacitance per unit length are uniform over the entire open wiring length L. Yes. However, in some cases, it may not be uniform. In this case, the ground capacity and the power capacity per unit length are defined for each finely divided area based on detailed layout information. An expression similar to that on the right side of (5) may be created and the sum calculated. Further, the coupling capacitance between the wiring LA and the wiring LB is C _CM (D). C _CM (D) is a capacitance value that depends on the inter-wiring distance D.

Further, it is assumed that the ground capacitance of the input terminal Ga is CG _GND and the power supply capacitance is CG _VDD . For example, when the potential of the wiring LB is driven to the power supply voltage V _DD , the potential at the position “X” (distance L from the input terminal Ga) at which the open failure of the wiring LA is assumed (hereinafter referred to as “open potential”). .) V is represented by the following formulas (6) to (8):

When 0 ≦ L <L1:
V = (C _VDD (L) + CG _VDD ) × V _DD
/ (C _VDD (L) + CG _VDD + C _GND (L) + CG _VDD ) (6)

When L1 ≦ L <L1 + LM = L2:
V = (C _CM (L) + C _VDD (L) + CG _VDD ) × V _{DD
/ (C CM (L) +} C VDD (L) + CG VDD + C GND (L) + CG VDD) ··· (7)

When L1 + LM = L2 ≦ L:
V = (C _CM + C _VDD (L) + CG _VDD ) × V _DD
/ (C _CM + C _VDD (L) + CG _VDD + C _GND (L) + CG _VDD ) (8)

As described above, the calculation accuracy of the open potential V can be increased by using the capacitance C _GND (L) and the capacitance C _VDD (L) calculated in consideration of the influence of the base of the wiring LA and the like. Further, the capacity C _CM (L) in the equation (7) is expressed by the following equation (9):

C _CM (L) = C _CM × (L−L1) / LM (9)

Here, for example, in order to detect 0 stuck-at fault of the wiring LA (input terminal Ga connected to) outside the LSI, the input terminal Ga has a logical value 1 (power supply voltage V _DD ) and the input terminal Gb has a logical value 1 Is set, the wiring LB is driven to the power supply voltage V _DD (logical value 1). Assuming that the logical threshold value of the input terminal Ga is V _th , when the following equation (10) is satisfied, an open failure at the position “X” is caused by the capacitive coupling with the wiring LB and the drive potential (V _DD ). to be influenced. Then, the logic of the wiring LA becomes 1 and the logic value 1 propagates to the output terminal Gz side of the logic gate G, so that it appears as if there is no open failure, and naturally, the open failure cannot be detected:

V ≧ V _th (10)

Note that the logic threshold value V _th may vary depending on the potential of another input terminal (not shown) of the logic gate G.

  When Expression (10) is established, the logic level of the output terminal Gz is affected by the coupling capacitance between the wiring LA and the wiring LB. In other words, although it is repeated, even if a test pattern for detecting a 0 stuck-at fault of the input terminal Ga with the logic level of the wiring LA set to 1 is applied, the presence of an open defect in the wiring LA cannot be detected. When the wiring LA has a plurality of adjacent wirings, the open potential V is determined depending on a combination of potentials at which the adjacent wirings are driven. That is, in order to accurately simulate the influence of the open failure, it is necessary to calculate the open potential V using the potentials that drive all adjacent wirings.

  However, when the wiring length excluding all adjacent wiring lengths from the open wiring length L becomes a certain value or more, the influence of the ground capacitance and the power supply capacitance becomes dominant, and the open potential V It is less affected by the driving potential. The open wiring length L in which the open potential V is not affected by capacitive coupling with the adjacent wiring is hereinafter referred to as “critical wiring length”. That is, when the open wiring length L is greater than or equal to the critical wiring length, the logic level of the wiring LA becomes 0 (or 1) due to an open failure regardless of the potential of the adjacent wiring during the LSI test period. Therefore, when the open wiring length L is equal to or longer than the critical wiring length of the wiring, it is possible to detect an open fault by a test pattern for detecting 0 stuck-at fault and 1 stuck-at fault of the input terminal Ga without considering the potential of the adjacent wiring. It is. The critical wiring length is obtained for each wiring as a wiring length by which the open potential V does not exceed the logical threshold value of the input terminal Ga by simulation or the like.

In the above, the case where the potential of the wiring LB is driven to the power supply voltage V _{DD of} , for example, 1 V has been described as an example, but the same applies to the case where the potential of the wiring LB is driven to 0 V which is the ground potential. whether open failure is detected, it can be determined by calculating an open voltage V using open wire length L, the adjacent wire length LM, the capacitance C _CM.

The capacity C _CM is dependent on the wiring distance D, therefore, if wiring lines that are close are close by a plurality of wiring distance is to use the capacitance C _CM in accordance with the distance Of course, it is necessary to do this.

An open failure can also occur inside the basic cell. For example, in the case of a NAND circuit including n-channel MOS (hereinafter referred to as “nMOS”) transistors T _N1 and T _N2 and p-channel MOS (hereinafter referred to as “pMOS”) transistors T _P3 and T _{P4 shown in FIG} . think of. As shown in FIG. 17, the power supply voltage V _DD is applied to the source electrodes of the pMOS transistors T _P3 and T _P4 , and the nMOS transistors T _N1 and T _N2 are connected in series to the drain electrodes. The signal A1 is input to the gate electrodes of the nMOS transistor T _N1 and the pMOS transistor T _P3 , and the signal A2 is input to the gate electrodes of the nMOS transistor T _N2 and the pMOS transistor T _P4 . A power supply voltage Vss (ground potential) is applied to the source electrode of the nMOS transistor _TN2 . A connection point between the pMOS transistors T _P3 and T _P4 and the nMOS transistor T _N2 is connected to the output terminal OUT.

When an open failure that impairs the complementarity of CMOS, such as an open failure at the position F between the drain terminal and the output terminal OUT of the pMOS transistor T _P4 , the nMOS transistors T _N1 and T _N2 are normal and output a logical value 0 Is possible. In order to detect the above open failure, first, a test pattern (A1 = 1, A2 = 1) whose output is a logical value 0 is applied, and then the pMOS transistor T _P4 is turned on (conductive). It is necessary to apply a test pattern (A1 = 1, A2 = 0) whose output is a logical value 1.

  An example of detecting an open failure that impairs the complementarity of the CMOS inside the basic cell C1 shown in FIG. 18 will be described. The basic cell C1 is arranged in the LSI 100 together with a plurality of flip-flops (F / Fs) and the like constituting the scan chain 110. A signal output from the F / F 101 included in the scan chain 110 propagates through a circuit (not shown) in the LSI 100 and is input as a signal A to the basic cell C1. The signal A may be a signal obtained by synthesizing signals propagated from a plurality of F / F output terminals included in the scan chain 110. The basic cell C1 receives another signal B and outputs a signal Z. The signal B is also a signal obtained by combining a signal propagated from a specific F / F output terminal of the scan chain 110 or a signal propagated from a plurality of F / F output terminals.

  FIG. 19 shows a part of the timing chart of the circuit operation of the LSI 100 shown in FIG. In FIG. 19, a signal CLK is a clock signal input to the scan chain 110, and a signal TEN is a shift enable signal input to the scan chain 110. The signal Q is a signal waveform in which a plurality of F / F output signals constituting the scan chain 110 are superimposed and displayed. When the external input of the LSI 100 and the output of each F / F included in the LSI 100 are determined, the signal A and the signal B input to the basic cell C1 are stabilized at a constant value after a period of unstable operation in each clock cycle.

  Except for the period when the operation is unstable, as shown in FIG. 19, the signal A is stabilized at the logical value 1 in the last shift operation cycle TS of the shift operation for shifting the scan chain 110 and is included in the scan chain 110. In the capture operation cycle TC in which data is input to each F / F, the signal A is stabilized at the logical value 0. Further, the signal B is stabilized at the logical value 1 in any cycle. That is, by first generating a test pattern in which a signal A and a signal B having a logical value of 1 are input to the basic cell C1, and then a signal A having a logical value of 0 is input to the basic cell C1, the signal is generated inside the basic cell C1. It is possible to detect an open failure in the pMOS transistor that impairs the CMOS complementarity described above (the output of the basic cell C1 is a logical value 1 when normal and a logical value 0 when a failure occurs). In this case, in order to reliably detect an open failure of the pMOS transistor connected to the signal A, the signal B needs to remain at the logical value 1 in the capture operation cycle. In addition, there is a possibility that an unstable operation may be performed before each signal is stabilized. Under the influence, charges are supplied from the pMOS transistor connected to the normal B signal, and the signal from the basic cell C1 is lost. There is a possibility that the output will be the same as normal. In order to perform more reliable detection, it is necessary to make the signal B stably remain at the logical value 1 in any cycle, and to create a test pattern that satisfies these conditions as much as possible. desirable.

  Although an example in which an open failure in a pMOS transistor is detected has been described above, an open failure in an nMOS transistor can be detected in the same manner. For example, a complementary pattern of CMOS is created by first creating a test pattern in which a signal A having a logical value 0 and a signal B having a logical value 1 are input to the basic cell C1, and then a signal A having a logical value 1 is input to the basic cell C1. It is possible to detect an open failure in an nMOS transistor that impairs performance. That is, the CMOS generated in the basic cell C1 by setting the test pattern so that the logical value of the signal A becomes 0 and 1 and the signal B becomes the logical value 1 in the shift operation cycle TS and the capture operation cycle TC, respectively. It is possible to detect open faults that impair the complementarity of.

  As described above, in order to detect an open failure in a cell, basically, only the logical value of the input terminal (corresponding to the target) of each cell in the last shift operation cycle and capture operation cycle is determined. It is necessary to create a test pattern in which the output of the cell changes due to the change, and the ATPG tool must have a function that can cope with such a test occurrence restriction (condition).

  Next, the operation of the test pattern creation apparatus 1 shown in FIG. 1 for creating an open failure detection test pattern (second test pattern) will be described.

  The capacity information list creation module 19 uses the layout information of the target LSI for each wiring of the adjacent wiring pair included in the target LSI, and includes capacity information including bridge fault information, adjacent wiring length, inter-wiring distance, and adjacent position as information. Create a list. Each wiring is divided into a plurality of sections according to the distance from the wiring adjacent to the wiring. Information on the critical wiring length of each wiring is also included in the capacity information list. Examples of the capacity information list are shown in FIGS. 20 (a) and 20 (b). FIG. 20A shows a propagation state of a general signal A in the LSI. The signal A is output from the driving cell C1, propagates on the wiring connected to the receiving cells C2, C3, and C4, and is input to the input terminal B1 of the receiving cell C2, the input terminal A2 of the receiving cell C3, and the receiving cell C4. Input to terminal A3. The hatched portion in FIG. 20A is the adjacent wiring portion. FIG. 20B is an example shown in FIG. 20A in a more generalized form of the capacitance information list of the wiring LA shown in FIG.

  “1”, “2”, and “3” in FIGS. 20A and 20B are used to distinguish the terminals of the receiving cell in the net of the signal wiring through which the signal A propagates. It is. Each terminal is given a serial number in the LSI, and this is preferably the same as an ID number for distinguishing stuck-at faults. That is, for example, 0 stuck-at fault and 1 stuck-at fault are expressed as “sa0_ <serial number of cell input terminal in LSI>” and “sa1_ <serial number of cell input terminal in LSI>”, respectively. Further, as the received cell related information, an input terminal name other than that connected to the signal wiring through which the signal A propagates may be added to obtain more detailed information from the capacity information list.

  In general, as the wiring is traced from the input terminal side of the receiving cell, the capacity information list is structured in consideration of this because it sequentially merges with the wiring to other receiving cells. In FIG. 20 (b), “(1)” indicates the wiring portion related to the receiving cell input terminal with the number 1 in the net, and “(1,2)” indicates the receiving cell input with the numbers 1 and 2 in the net. The wiring part related to the terminal is shown (the same applies to “(1,2,3)”), and thereafter, detailed information about the wiring part and the adjacent wiring is described up to “;”. That is, the total length of the wiring part, the total capacity, the serial number of the adjacent wiring, the position from the starting point of the wiring part, and the distance between the wirings are described. Although not shown in FIG. 20A, wiring portions (1, 2) and (1, 3) may exist depending on the wiring conditions. Also, since the same adjacent wiring is close to the wiring portion (1) with two types of wiring distances D1 and D2, it is like “(x13, x14, D1) (x14, x15, D2)”. Such a notation can be seen in FIG. The critical wiring length information is described in parentheses in the wiring portion including the critical wiring length. In FIG. 20B, it appears in the wiring part (1, 2, 3,). In this case, the effective length of this wiring portion is from the starting point to the critical wiring length.

  The stuck-at fault list creation module 20 creates a pin stuck-at fault list as a list of stuck-at faults assumed for the input / output terminals of the cells included in the target LSI from the layout information of the target LSI. The bridge fault list, capacity information list, and pin stuck-at fault list are all created based on the layout information of the target LSI. Therefore, the bridge fault list, the capacity information list, and the pin stuck fault list can be linked. A stuck-at fault created based on the logical net (logical connection information) of the target LSI may be input from the outside. However, it is troublesome to associate the plurality of lists alternately.

  The determination module 16 first links the bridge fault list, the capacity information list, and the pin stuck-at fault list, and performs a stuck-at fault simulation of the target LSI using the first test pattern created for bridge fault detection. It is determined whether or not each stuck-at fault assumed at the input terminal of each cell described in the pin stuck-at fault list is detected by the first test pattern.

  Next, the calculation module 18 obtains the logic value of each signal in the target LSI in the first test pattern by logic simulation or the like and stores it in the signal logic value information storage area 214, and each degeneration determined to be detected. For the failure, refer to the capacity information list and obtain the net information of the corresponding signal. In addition, the calculation module 18 acquires the drive potential of the adjacent wiring in the test pattern in which the stuck-at failure is detected from the signal logical value information storage area 214. Based on the acquired data and the open potential V calculated by using the equations (6) to (8) for each wiring portion, the calculation module 18 is, for example, the largest wiring for which the negative of the equation (10) is established. A length L is obtained, and a wiring portion where an open failure is reliably detected by the first test pattern is calculated. In the calculation of the open potential V, the coupling capacitance with all the wirings adjacent to the wiring assumed to have an open failure is taken into consideration.

  At this time, the ratio of open faults (detection accuracy, signal-to-signal wiring) detected accompanying the detected stuck-at fault (detection accuracy 1) is “(total sum of lengths of wiring parts calculated to be detectable) / ( Signal wiring length (portion below critical wiring length)) ”. The sum of all open faults in the denominator and numerator of the ratio of open faults is the (weighted) open fault detection rate. The logical value of each signal line may be acquired at the same time when the first test pattern is created and stored in the signal logical value information storage area 214 in advance.

  The open fault propagates outside the LSI via the input terminal (possibly plural) of the cell to which the signal wiring including the location where the open fault occurs is connected. Therefore, the open fault can be associated with the stuck-at fault of the input terminal through which the open fault passes. An open fault that can be associated with each stuck-at fault and propagates through an input terminal on which the stuck-at fault is assumed is referred to as an “open fault associated with the stuck-at fault”.

  The wiring area (wiring part) corresponding to the open fault associated with the stuck-at fault of each input terminal is from the input terminal corresponding to the wiring to the output terminal of the cell driving that wiring up to the critical wiring length. Part. For this wiring area, a wiring area in which an “incorrect determination” of the first test pattern in which an open failure is not detected due to the influence of capacitive coupling with the wiring adjacent to each wiring corresponds to the capacity information list. Calculated based on stuck-at fault detection / non-detection information. Then, the wiring area where the “false determination” occurs is set as an undetected wiring area of the open fault accompanying the stuck-at fault assumed for each input terminal.

  The calculation module 18 calculates the potential of the wiring at a position assuming an open failure using the potential of the adjacent wiring and the distance between the wirings. Then, the calculation module 18 compares the logical threshold value of the input terminal to which the wiring assuming the open failure is connected with the calculated potential of the wiring, so that the open failure associated with the stuck-at failure is determined according to the occurrence location. A wiring area detected by one test pattern or a wiring area not detected is calculated.

  There are some overlaps with respect to open faults, and if any open fault has been detected, the overlap portion needs to be a detection wiring area. The main duplication includes duplication due to the definition of two types of stuck-at faults, 0 stuck-at faults and 1 stuck-at faults, at one input terminal, duplication at the wiring portion before branching, and the like. Therefore, the weighted failure detection rate for open failures is calculated so as to eliminate duplication.

  An undetected stuck-at fault that is not detected by the first test pattern and a stuck-at fault itself are detected, but there is a wiring region (wiring portion) that is not detected by the first test pattern among the open faults accompanying the detected stuck-at fault. Information on the detected stuck-at fault (hereinafter referred to as “open fault undetected stuck-at fault”) is stored in the undetected fault storage area 213. Information such as an undetected stuck-at fault includes information such as a logical value of a signal propagating through a wiring assumed to have an open fault and a wiring adjacent to the wiring when the first test pattern is applied to the target LSI.

  Note that, as described above, the open potential V is not affected by the capacitive coupling with the adjacent wiring as to the open failure occurring in the wiring portion having the critical wiring length or longer. Therefore, a wiring portion having a critical wiring length or longer is considered to be detected and detected by the first test pattern when any stuck-at fault assumed at the input terminal connected to the wiring assumed to have an open fault is detected. The wiring area is not detected.

  The second test pattern creation / judgment module 17 detects undegenerated faults and open fault undetected stuck faults that have not been detected by the first test pattern as undetected wiring areas (undetected) of open faults associated with open fault not detected stuck faults. A constrained stuck-at fault detection test pattern (second test pattern) for detecting the detection wiring portion) to be as small as possible is created. Specifically, when the logical value of a signal propagating through a wiring assuming an open failure (hereinafter referred to as “target wiring”) fluctuates due to capacitive coupling with the adjacent wiring, it is adjacent to the target wiring and the target wiring. For the logical value of the signal propagating through the wiring to be connected, the stuck-at fault assumed at the input terminal of the cell to which the target wiring is connected can be detected so that the undetected wiring area of the open fault accompanying the stuck-at fault becomes as small as possible. Constraints (conditions) are calculated and set using the calculation module 18, and a second test pattern is created.

  In addition, the second test pattern creation / determination module 17 determines whether or not a stuck-at fault is detected based on the created first and second test patterns based on an auxiliary stuck-at fault simulation, and also detects an open fault associated with the stuck-at fault. The undetected wiring area is calculated by using the calculation module 18, the entire results are collected, and the open failure detection rate and the like are output.

  As for the creation of the second test pattern, for example, a case where a signal ST1 propagating through the wiring LT1 adjacent to the wiring LT2 through which the signal ST2 propagates is input to the cell CT as shown in FIG. Here, a first test pattern (logic value 1 is propagated as signal ST1) is detected by detecting the zero stuck-at fault at the input terminal of the cell CT to which the signal ST1 is input due to the influence of the capacitive coupling between the wiring LT1 and the wiring LT2. )), The logical value of the signal ST2 is 1 at the time of detection, and it is assumed that an open failure in the range indicated by the thick solid line in FIG. 21 is not detected. In that case, when the normal logical value of the signal ST1 is 1, a constraint is set such that the logical value of the signal ST2 is 0 (the same value as the stuck-at fault of the input terminal of the cell CT to be detected), and the cell CT A second test pattern for testing the logical value of the output signal is generated. By applying the second test pattern with the above constraints to the target LSI, it is determined from the logic value of the output signal of the cell CT that the logic value of the input signal of the signal ST1 that should be 1 is 0. The open fault associated with the 0 stuck-at fault at the input terminal of the cell CT can be detected.

  Further, in the first test pattern for detecting one stuck-at fault assumed at the input terminal of the cell CT (a logical value 0 is propagated as the signal ST1), the logical value of the signal ST2 becomes 0 at the time of detection, and FIG. When an open failure in the same range is not detected, the second test is performed by setting a constraint such that a test pattern for testing the logical value of the output signal of the cell CT is created with the normal logical values ST1 = 0 and ST2 = 1. A pattern is created. By setting the above constraints, it is possible to detect an open fault associated with one stuck-at fault at the input terminal of the cell CT to which the signal ST1 is input. Detection of an open failure (wiring area to be detected) can be substantially realized by the second test pattern that satisfies any of the above-described restrictions. More precisely, a wiring area detected by any one of the second test patterns satisfying these two types of restrictions is detected (the detected wiring areas may be slightly different due to the restrictions). More generally, each signal is adjacent to a plurality of signals, and the efficiency of creating the second test pattern is improved by restricting the value of the adjacent signal having a greater effect. Acquisition of such desirable constraints (conditions) is performed in the calculation module 18.

  Instead of creating a constrained stuck-at fault detection test pattern as described above, a test pattern for N times detection may be created. For example, if the number of detections of each stuck-at fault in the second test pattern is set according to the size of the undetected wiring area of the accompanying open fault based on the result calculated by the calculation module 18 for the first test pattern, High open failure detection rate can be obtained with fewer test patterns.

  A method of creating a test pattern to be applied to the target LSI using the test pattern creation device 1 shown in FIG. 1 will be described using the flowchart shown in FIG.

  (A) In step S10, the layout information of the target LSI is stored in the layout information storage area 201 via the input device 30 shown in FIG. A preset proximity distance is stored in the proximity distance storage area 202.

  (B) In step S20, the short information creation module 11 creates short information by the method described with reference to the flowchart of FIG. That is, a short potential at a short point assumed between cell outputs is calculated using a circuit description for cell circuit simulation and a model for circuit simulation of an element used in the circuit description, and short information library 51 is used as short information. Stored in

  (C) In step S30, the threshold information creation module 12 executes circuit simulation and creates the logical threshold information of the cells stored in the simulation data storage area 203. The created logical threshold information is stored in the threshold information library 52.

  (D) In step S40, the extraction module 13 reads the layout information and the proximity distance from the layout information storage area 201 and the proximity distance storage area 202, respectively. Then, the extraction module 13 extracts bridge fault information related to an adjacent wiring pair whose inter-wiring distance is equal to or less than the proximity distance among the plurality of signal wiring pairs included in the layout information. As already described, the bridging fault information includes signal information corresponding to the adjacent wiring pair, adjacent wiring length, drive cell information, and may further include received cell information. The extracted bridge fault information is stored in the bridge fault information storage area 205.

  (E) In step S50, the bridge fault list creation module 14 reads the short information, the logical threshold information, and the bridge fault information from the short information library 51, the threshold information library 52, and the bridge fault information storage area 205, respectively. Create a bridging fault list. As already described, the bridge fault list includes signal information, adjacent wiring length, drive cell information, bridge fault type, occurrence probability, propagation probability, detection accuracy, and the like. Further, there are cases where received cell information is included. The created bridge fault list is stored in the bridge fault list storage area 206.

  (F) In step S60, the first test pattern creation / determination module 15 reads the bridge fault list from the bridge fault list storage area 206. Then, the first test pattern creation / determination module 15 creates a first test pattern and failure detection information for detecting a bridge failure in an adjacent wiring pair included in the bridge failure list. The first test pattern creation / determination module 15 creates a first test pattern in consideration of the bridge fault type determined for each adjacent wiring pair. The created first test pattern is stored in the test pattern storage area 207. In addition, the first test pattern creation / determination module 15 executes auxiliary fault simulation, and ATPG calculates the detection rate of bridge faults other than bridge faults directly targeted by each test pattern, and creates fault detection information. You can also. The failure detection information is stored in the failure detection information storage area 208. Further, the first test pattern creation / determination module 15 creates an execution result report. The execution result report is stored in the result report storage area 209.

  (G) In step S70, the calculation module 18 reads the bridge fault list and the fault detection information from the bridge fault list storage area 206 and the fault detection information storage area 208. Then, the calculation module 18 calculates the bridge failure detection rate FC of the first test pattern using Expression (2). Further, the calculation module 18 calculates the weighted bridge fault detection rate FC_WL of the first test pattern using Expression (3). The bridge failure detection rates FC and FC_WL are stored in the failure detection rate storage area 210. The calculation module 18 also calculates the weight of the undetected failure and stores it in the undetected failure storage area 213.

  (H) In step S80, the capacity information list creation module 19 reads layout information from the layout information storage area 201. The capacity information list creating module 19 creates a capacity information list for each wiring included in the target LSI. The capacity information list is stored in the capacity information list storage area 211.

  (I) In step S90, the stuck-at fault list creation module 20 reads layout information from the layout information storage area 201 and creates a pin stuck-at fault list. The pin stuck-at fault list is stored in the pin stuck-at fault list storage area 212.

  (N) In step S100, the determination module 16 reads the pin stuck-at fault list and the first test pattern from the pin stuck-at fault list storage area 212 and the test pattern storage area 207, and the target LSI stuck-at fault using the first test pattern. Perform a simulation. Then, the determination module 16 determines whether or not each stuck-at fault assumed at the input terminal of each cell is detected by the first test pattern. Fault detection information including information on undetected stuck-at faults that are not detected by the first test pattern is stored in the fault detection information storage area 208.

  (L) In step S110, the calculation module 18 reads the capacity information list including the bridge fault information and the degenerate fault detection information of the first test pattern from the capacity information list storage area 211 and the fault detection information storage area 208, and sets the adjacent wiring pair. When an open failure is assumed for one of the wirings, the wiring region corresponding to the open failure associated with the stuck-at failure at the input terminal of the cell connected to the wire assuming the open failure is detected by the first test pattern. Calculate how much is detected in response to undetected, calculate whether at least each open fault is detected, and calculate the size of the wiring area where open faults remain undetected. The calculation result is stored in the failure detection information storage area 208 as stuck-at fault detection additional information.

  (W) In step S120, the second test pattern creation / determination module 17 reads out the stuck-at fault detected information including the undetected stuck-at fault from the fault detection information storage area 208, and opens the open fault accompanying the unopened stuck-out fault. The undetected wiring area of the undetected stuck fault that is not detected by the first test pattern and the open fault that is not detected by the first test pattern among the stuck faults is reduced by using the constraint that the undetected wiring area of the open circuit becomes small. A second test pattern or a second test pattern for detection N times is created, and the effect of reducing the additional detection and undetected wiring areas is determined. The second test pattern is stored in the test pattern storage area 207. Further, information on the undetected failure and the open failure undetected stuck-at failure of the second test pattern is stored in the undetected failure storage area 213.

  As explained above, the stuck-at faults assumed at the input terminals of each cell and the open faults associated with the stuck-at faults are not targeted, and stuck-at faults that cannot be detected by the first test pattern, and open faults not detected Only for stuck-at faults, constrained stuck-at fault test patterns or N-time detection test patterns are created as second test patterns. As a result, an increase in the number of second test patterns is suppressed. A test pattern in which the first test pattern and the second test pattern are combined is applied to a test for detecting a bridge fault, a stuck-at fault, and an open fault of the target LSI.

  Note that a detected stuck-at fault with a large open-detected undetected wiring area associated with it may be an open-fault undetected stuck-at fault that is taken into account when setting a constraint in creating the second test pattern. For example, the average size of the undetected wiring area of the open failure is calculated for the detected stuck-at fault that has a wiring area that is not detected by the first test pattern, and the size of the undetected wiring area is larger than the average. In this case, the detected stuck-at fault is a large open fault undetected wiring area accompanying the stuck-at fault. Alternatively, with the size of the undetected part of the open fault as a weight, the detected stuck-at faults with undetected wiring areas are arranged in descending order of the weight, and the sum of the weights exceeds 1/2 or 2/3 of the total weight. The detection stuck-at fault may be a detected stuck-at fault with a large undetected wiring area of the accompanying open fault. Further, the same definition may be made with the frequency of occurrence of open faults depending on the wiring status as a weight. In addition to the above, it is possible to define a detected stuck-at fault with a large undetected wiring area of an open fault, but the concept of this embodiment is effective in any definition.

  The series of test pattern creation operations shown in FIG. 22 can be executed by controlling the test pattern creation device 1 shown in FIG. 1 by a program of an algorithm equivalent to FIG. This program may be stored in the storage device 200 constituting the test pattern creation device 1 shown in FIG. Further, the program is stored in a computer-readable recording medium, and the recording medium is read into the storage device 200 shown in FIG. 1, whereby the series of test pattern creation operations of the present invention can be executed.

  Conventionally, it has been determined whether or not a bridge failure in an adjacent wiring pair is detected by a test pattern based only on circuit connection information. Therefore, there is a possibility that the detected bridge fault is not a bridge fault that propagates in the LSI that can be actually detected. That is, the test pattern cannot be evaluated with high accuracy.

  On the other hand, in the test pattern creation device 1 according to the first exemplary embodiment of the present invention, the bridge fault type of the bridge fault occurring in the adjacent wiring pair is determined by obtaining the short potential and the logical threshold value of the receiving terminal by circuit simulation. To do. Then, using the bridge fault type, a first test pattern for detecting a bridge fault that can propagate through the LSI via the receiving cell is created. Further, the failure detection rate weighted by the detection accuracy of the first test pattern and the adjacent wiring length is calculated. Therefore, the failure detection rate and the bridge failure occurrence rate in the actual product shipping test can be predicted with high accuracy. When the failure detection rate and the bridge failure occurrence rate are lower than desired values, the failure detection rate and the bridge failure occurrence rate can be improved by correcting the first and second test patterns.

  Further, in the test pattern creation device 1 according to the first exemplary embodiment of the present invention, the stuck-at fault assumed at the input terminal of each cell and the open fault associated with the stuck-at fault are not detected by the first test pattern. Open faults associated with detected stuck-at faults and undetected stuck-at faults, and stuck-at faults themselves are detected, but the open faults associated with open faults are large (the undetected trace length is long). Extracted. Then, the second test pattern for detecting the stuck-at fault is created so that the undetected stuck-line length of the associated open fault becomes as short as possible for both the undetected stuck-at fault and the open-fault undetected stuck-at fault. Since the second test pattern is not created for all the stuck-at faults assumed at the input terminals of each cell, an increase in the number of patterns of the second test pattern can be suppressed. In addition, it is possible to determine with high accuracy whether or not a bridge failure and an open failure occurring in the LSI can be reliably detected. In addition, it is possible to create a test pattern that takes into account the nature of open faults that have different effects depending on the location due to the effect of capacitive coupling. By applying the created test pattern to a product using an LSI tester, the risk of shipping a defective product can be reduced.

  In the above description, the example in which the first test pattern for detecting the bridge failure is considered in consideration of the adjacent wire pair and the bridge failure type included in the bridge failure list has been described. A first test pattern that detects a bridging fault assumed for the pair may be created. First, create a preliminary test pattern that detects stuck-at faults in the target LSI, perform bridge fault simulation to find undetected bridge faults, and undetected wiring for open faults associated with stuck-at faults After obtaining the area, the flow of the test pattern creation method according to the first embodiment of the present invention described above may be performed. In general, the stuck-at fault test has a small number of test patterns, so that the number of test patterns as a whole may be suppressed.

(Second Embodiment)
As mentioned in the description of the first embodiment, once the bridge fault library and the threshold information library are created for a specific cell library, in other LSIs using the same cell library, The contents equivalent to those of the first embodiment of the present invention can be implemented only by referring to these libraries. This is shown in FIG. The cell library 2 shown in FIG. 1 does not include a circuit simulation model, and the short information library 51 and the threshold information library 52 are provided from the outside of the test pattern creation apparatus 1. The test pattern creation apparatus does not include the short information creation module 11, the threshold information creation module 12, the simulation data storage area 203, and the simulation result storage area 204. Others are the same as those of the first embodiment, and redundant description is omitted.

(Other embodiments)
As described above, the present invention has been described according to the first and second embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the description of the first and second embodiments already described, whether or not a bridge fault in each adjacent wiring pair included in the bridge fault list can be detected by the first test pattern based on the connection information of the target LSI. Although an example in which failure detection information is created by determining whether or not a failure is detected, it is also possible to determine whether or not a bridge failure can be detected by the first test pattern by executing a failure simulation.

  In addition, the wiring areas of the bridge fault and the open fault associated with the stuck-at fault have been described using only the wiring length (the probability of occurrence of the fault is uniform). However, depending on the number of the minimum VIA included in the wiring area, these faults For example, the “wiring region” (rWL + (1-r) NVIA: where r is the weight ratio of the wiring length WL and the minimum number of VIAs NVIA) is defined in consideration of this. It is also possible to apply the second embodiment in the same way. Further, the influence of capacitive coupling may be taken into account by stochastically setting the logical values of adjacent wirings.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is a schematic diagram which shows the structure of the test pattern production apparatus which concerns on the 1st Embodiment of this invention. It is a typical circuit diagram which shows the example of a bridge failure. It is a flowchart for demonstrating the creation method of the short information which concerns on the 1st Embodiment of this invention. It is an example of the format of the short information which concerns on the 1st Embodiment of this invention. It is a schematic circuit diagram which shows the example of a NAND circuit. It is an example of the grouping information which concerns on the 1st Embodiment of this invention. It is an example of the format of the bridging fault information which concerns on the 1st Embodiment of this invention. It is another example of the format of the bridging fault information which concerns on the 1st Embodiment of this invention. It is another example of the format of the bridging fault information which concerns on the 1st Embodiment of this invention. It is an example of a format of a bridge fault list according to the first embodiment of the present invention. It is a table | surface of the bridge fault type which concerns on the 1st Embodiment of this invention. FIG. 12A shows an example of short potential distribution, and FIG. 12B shows an example of logical threshold distribution. FIG. 13A shows another example of short potential distribution, and FIG. 13B shows another example of logic threshold distribution. It is a typical circuit diagram which shows the example of a redundant failure. It is a typical circuit diagram which shows the other example of a redundant failure. It is a typical circuit diagram which shows the example of an open failure. FIG. 3 is a schematic equivalent circuit diagram of a NAND circuit. It is a typical circuit diagram for demonstrating the example which detects an open failure. 19 is a timing chart for explaining the operation of the circuit shown in FIG. 18. FIG. 20A is a circuit diagram for explaining an example of the capacity information list according to the first embodiment of the present invention, and FIG. 20B is a first embodiment of the present invention. It is an example of the capacity | capacitance information list concerning. It is a typical circuit diagram for demonstrating the production method of the 2nd test pattern which concerns on the 1st Embodiment of this invention. It is a flowchart for demonstrating the test pattern creation method which concerns on the 1st Embodiment of this invention. It is a schematic diagram which shows the structure of the test pattern creation apparatus which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Test pattern creation apparatus 2 ... Cell library 10 ... CPU
DESCRIPTION OF SYMBOLS 11 ... Short information creation module 12 ... Threshold information creation module 13 ... Extraction module 14 ... Bridge fault list creation module 15 ... First test pattern creation / judgment module 16 ... Judgment module 17 ... Second test pattern creation / judgment module 18 ... calculation module 19 ... capacity information list creation module 20 ... degenerated fault list creation module 30 ... input device 40 ... output device 51 ... short information library 52 ... threshold information library 200 ... storage device 201 ... layout information storage area 202 ... proximity Distance storage area 203 ... Simulation data storage area 204 ... Simulation result storage area 205 ... Bridge fault information storage area 206 ... Bridge fault list storage area 207 ... Test pattern storage area 208 ... Reason Failure detection information storage area 209 ... Result report storage area 210 ... Failure detection rate storage area 211 ... Capacity information list storage area 212 ... Pin degenerate failure list storage area 213 ... Undetected failure storage area 214 ... Signal logic value information storage area

Claims (5)

An extraction module for extracting bridge fault information from layout information;
A bridge fault list creation module that creates a bridge fault list from the bridge fault information, short information between output terminals of the logic cells, and logic threshold information of the input terminals of the logic cells;
A first test pattern creation / determination module that creates a first test pattern for detecting a bridge fault in an adjacent wiring pair in which the distance between wirings is in the proximity distance range using the bridge fault list;
Using the layout information, a capacity information list creation module that creates a capacity information list that includes the bridge fault information, the adjacent wiring length defined as the wiring length of the adjacent wiring pair, the inter-wiring distance and the adjacent position as information,
A determination module for determining whether a stuck-at fault assumed at the input terminal of the logic cell is detected by the first test pattern;
Using the capacity information list, when assuming an open failure in one wiring of the adjacent wiring pair, a wiring region corresponding to an open failure associated with a stuck-at failure in an input terminal of a logic cell to which the wiring is connected is A calculation module that calculates how much is detected according to detection / non-detection of a stuck-at fault according to the first test pattern;
An undetected stuck-at fault that is not detected by the first test pattern and a detected stuck-at fault that has an undetected wiring area associated with an open failure are detected using a constraint that reduces the undetected wiring area or the undetected wiring area is detected. A test pattern creation device comprising: a second test pattern creation / determination module that creates a second test pattern to be reduced.   The calculation module calculates the potential of the wiring at a position assuming the open failure using the potential of the adjacent wiring of the wiring and the distance between the wirings, and calculates the calculated potential and the logical threshold value of the input terminal. The wiring area detected by the first test pattern or the wiring area that is not detected is calculated according to the location where the open fault accompanying the stuck-at fault is generated. Test pattern creation device described in 1. Extraction module, bridge fault list creation module, first test pattern creation / judgment module, capacity information list creation module, judgment module, calculation module, second test pattern creation / judgment module, bridge fault information storage area, bridge fault list storage area And a test pattern creation method using a test pattern creation device comprising a capacity information list storage area,
The extraction module extracts bridge fault information from layout information and stores it in the bridge fault information storage area;
The bridging fault list creation module creates a bridging fault list from the bridging fault information read from the bridging fault information storage area, short information between output terminals of logic cells, and logical threshold information of input terminals of the logic cells. Storing in the bridge fault list storage area;
The first test pattern creation / determination module uses the bridge fault list read from the bridge fault list storage area to detect a bridge fault in an adjacent wiring pair whose inter-wire distance is within the close distance range. Creating a test pattern;
The capacity information list creation module uses the layout information to generate a capacity information list including, as information, the bridge fault information, the adjacent wiring length defined as the wiring length of the adjacent wiring pair, the inter-wiring distance, and the adjacent position. Creating and storing in the capacity information list storage area;
The determination module determining whether a stuck-at fault assumed at the input terminal of the logic cell is detected by the first test pattern; and
When the calculation module assumes an open failure in one wiring of the adjacent wiring pair using the capacity information list, the calculation module responds to an open failure associated with a stuck-at failure at an input terminal of a logic cell to which the wiring is connected. Calculating how much the wiring area is detected according to the detection / non-detection of the stuck-at fault according to the first test pattern;
Constraint that the second test pattern creation / determination module makes the undetected wiring area small for undetected stuck-at faults that are not detected by the first test pattern, and for detected stuck-at faults that have undetected wiring areas that are associated with open failures. A method of creating a test pattern, comprising: creating a second test pattern for detecting or reducing the undetected wiring area using the method. Calculating a degree to which a wiring region corresponding to an open fault accompanying the stuck-at fault is detected in response to detection / non-detection of the stuck-at fault according to the first test pattern;
Calculating the potential of the wiring at a position assuming the open failure using the potential of the wiring adjacent to the wiring and the distance between the wiring;
By comparing the calculated potential with the logical threshold value of the input terminal, the open fault associated with the stuck-at fault is detected or not detected by the first test pattern according to the occurrence location. The test pattern creating method according to claim 3, further comprising: calculating a wiring area. An instruction that causes the extraction module to extract bridge fault information from the layout information;
A command for causing the bridge fault list creation module to create a bridge fault list from the bridge fault information, short information between output terminals of the logic cells, and logic threshold information of the input terminals of the logic cells;
A command for causing the first test pattern creation / determination module to create a first test pattern for detecting a bridge fault in an adjacent wiring pair in which the distance between wirings is in the proximity distance range using the bridge fault list;
A capacity information list creation module uses the layout information to create a capacity information list that includes the bridge fault information, the adjacent wiring length defined as the wiring length of the adjacent wiring pair, the distance between the wirings, and the adjacent position as information. Instructions and
An instruction that causes a determination module to determine whether a stuck-at fault assumed at an input terminal of the logic cell is detected by the first test pattern;
A wiring corresponding to an open fault associated with a stuck-at fault at an input terminal of a logic cell to which the wiring is connected when an open fault is assumed in one wiring of the adjacent wiring pair using the capacity information list in the calculation module A command for calculating how much the area is detected according to detection / non-detection of the stuck-at fault according to the first test pattern;
The second test pattern creation / determination module has a constraint that the undetected stuck fault that is not detected by the first test pattern and the detected stuck stuck fault that has an undetected interconnect area of the open fault that accompanies it are reduced. A test pattern creation program for executing a command to create a second test pattern that is detected or used to reduce the undetected wiring area.

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