JP2015141098A - Test board, integrated circuit test method, integrated circuit device, and integrated circuit test system - Google Patents

Abstract

Provided is a technique capable of performing an AC test at an actual operation speed including a connection part of a transmission / reception circuit and a package without increasing a cost while sharing a test board in an AC test and a DC test. .
A filter circuit for passing a direct current component and cutting an alternating current component on a wiring 11 electrically connecting an input / output terminal 20a of an integrated circuit device 20 to be tested and a tester terminal 10a connected to the tester 30; Using the test board 10 provided with the termination circuit 13, in the integrated circuit device 20, a test pattern to which a pattern not to be tested is added before and after the test circuit 10 is generated and output from the input / output terminal 20 a by a bidirectional buffer. An AC (Alternating Current) test is performed by receiving a pattern input to the terminal 20a using a bidirectional buffer and comparing the test pattern with the received pattern.
[Selection] Figure 1

Description

  The present invention relates to a technique for testing an integrated circuit device.

  In recent years, electronic devices such as computers have dramatically improved performance by speeding up signal transmission between LSIs (Large Scale Integration) and increasing the number of channels and adopting a high-density mounting structure such as three-dimensional mounting. . Along with this, miniaturization of LSI processes and LSI packages has progressed, and the speed of circuits has increased. As a result, the margin of LSI tends to decrease. For this reason, it is essential to remove defective products in a DC (Direct Current) test and an AC (Alternating Current) test.

  As shown in FIG. 7, a general DC test and AC test are performed by connecting an LSI to be tested to a tester via a test board. In this case, the DC test is performed by generating a fixed level by the LSI and inputting it to the tester, generating a fixed level by the tester and inputting it to the LSI, and measuring whether or not the generated fixed level is received. The AC test is performed by inputting a test pattern generated from the LSI to the tester, inputting the test pattern generated from the tester to the LSI, and comparing the test pattern with the received pattern. At this time, it is difficult for a general tester to input and output high-speed signals. Therefore, when input / output from a general tester is used, it is difficult to perform an AC test by operating the LSI at an actual operation speed. At present, it is difficult to realize a tester capable of inputting / outputting such a high-speed signal in terms of both performance and cost.

  Therefore, as an AC test at an actual operation speed, there is a method of connecting a semiconductor memory (RAM: Random Access Memory) or the like to a test board as shown in FIG. In this case, the test target LSI generates and outputs a test pattern and writes it in the semiconductor memory. Then, the LSI reads a test pattern from the semiconductor memory, and compares the generated test pattern with the read test pattern.

  A technique related to LSI testing is described in Patent Document 1. The related technology described in Patent Document 1 includes a memory control circuit that outputs dummy data as write data when a test mode is set in an LSI, and a read data selection circuit that loops back the write data to the memory control circuit. Have. Then, the memory control circuit holds the write data looped back by the read data selection circuit in the register, and reads the write data held in the register. An LSI to which this related technology is applied can perform an AC test at an actual operation speed by itself.

JP 2009-199703 A

  However, the above-described general test method and related techniques have the following problems.

  In the general AC test method having the configuration shown in FIG. 7, the AC test at the actual operation speed is difficult as described above.

  Further, in the AC test method in which the semiconductor memory is connected to the test board as shown in FIG. 8, it is necessary to use two types of test boards for the DC test and the AC test. For this reason, it has been unavoidable to increase the test time, increase the number of parts accompanying the connection of the semiconductor memory and the semiconductor memory, increase the mounting area, and increase the cost.

  The related technique described in Patent Document 1 can test the read operation and write operation of the memory control circuit in the LSI at an actual operation speed. However, in the AC test, it is desirable to test not only the memory control circuit in the LSI but also the connection portion of the memory control circuit to the external transmission / reception circuit and the LSI package at the actual operation speed. However, with this related technology, an AC test cannot be performed on an LSI input / output circuit and an LSI package.

  The present invention has been made to solve the above-described problems. The actual operation including the connection part of the transmission / reception circuit and the package without increasing the cost while sharing the test board in the AC test and the DC test. An object of the present invention is to provide a technique that enables AC testing at a speed.

  The test board of the present invention includes a filter circuit that passes a DC component and cuts an AC component on a wiring that electrically connects an input / output terminal of the integrated circuit device to be tested and a tester terminal connected to the tester, and the integrated circuit And a termination circuit that terminates a transmission path from the input / output terminal of the circuit device to the filter circuit on the filter circuit side.

  In the integrated circuit test method of the present invention, in the integrated circuit device connected to the above-described test board, a test pattern to which an untested pattern is added before and after the test circuit is generated, and the input / output terminal is connected by a bidirectional buffer. While outputting, a pattern input to the input / output terminal is received by the bidirectional buffer, and an AC (Alternating Current) test is performed by comparing the test pattern with the received pattern.

  In the integrated circuit test method of the present invention, a fixed level signal is generated in the tester through the test board and input to the integrated circuit device, and a fixed level signal is generated in the integrated circuit device. Then, a DC (Direct Current) test is performed by inputting to the tester.

  Further, an integrated circuit device of the present invention, a controller having a pattern generation circuit that generates a test pattern to which a non-test target pattern is applied before and after that, and a pattern comparison circuit that compares the test pattern and the received pattern; A transmission circuit that outputs a pattern output from the controller to the outside; and a reception circuit that outputs a reception pattern input from the outside to the controller, and simultaneously operates the transmission circuit and the reception circuit during an AC test operation. A bidirectional buffer.

  The integrated circuit test system of the present invention includes the above-described test board, the above-described integrated circuit device connected to the test board as a test target, and the tester connected to the tester terminal.

  The present invention provides a technique that enables AC testing at an actual operation speed including a connection part of a transmission / reception circuit and a package without increasing cost while sharing a test board in AC test and DC test. be able to.

1 is a block diagram showing a configuration of an integrated circuit test system as an embodiment of the present invention. It is a block diagram which shows the structure of the integrated circuit device as embodiment of this invention. (A) And (c) is a figure which shows an example of the pattern outside a test object generated by the integrated circuit device as embodiment of this invention, (b) is a figure which shows an example of a test pattern. . It is a figure which shows the example of mounting of the integrated circuit test system as embodiment of this invention. It is a figure which illustrates typically the principle of the DC test by embodiment of this invention. It is a figure which illustrates typically the principle of the AC test by embodiment of this invention. It is a block diagram which shows the structural example of the system which performs a general AC test. 1 is a block diagram illustrating a configuration example of a general system for performing an AC test by connecting a RAM. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a configuration of an integrated circuit test system 1 as an embodiment of the present invention. In FIG. 1, the integrated circuit test system 1 includes a test board 10, an integrated circuit device 20, and a tester 30.

  The test board 10 includes a test board wiring 11 that electrically connects the input / output terminal 20 a of the integrated circuit device 20 and the tester terminal 10 a connected to the tester 30. Further, the test board 10 includes a filter circuit 12 and a termination circuit 13 on the test board wiring 11.

  The filter circuit 12 passes the direct current component and cuts the alternating current component. For example, the filter circuit 12 may be configured by an inductor inserted in series with the test board wiring 11.

  The termination circuit 13 terminates the transmission line from the input / output terminal 20a to the filter circuit 12 on the filter circuit 12 side. When an AC component is output from the input / output terminal 20 a of the integrated circuit device 20, the termination circuit 13 matches the impedance of the transmission path from the bidirectional buffer 26 to the filter circuit 12 described later. For example, the termination circuit 13 may be configured by a resistor connected in parallel to the test board wiring 11.

  In FIG. 1, one test board wiring 11 that electrically connects one input / output terminal 20 a of the integrated circuit device 20 and one tester terminal 10 a connected to the tester 30, and one filter circuit. 12 and one termination circuit 13, the number of wirings, filter circuits and termination circuits included in the test board of the present invention, and the number of tester terminals connected to the input / output terminals and the tester of the integrated circuit device are shown. It is not intended to limit.

  As shown in FIG. 2, the integrated circuit device 20 includes a controller 23 having a pattern generation circuit 21 and a pattern comparison circuit 22, and a bidirectional buffer 26 having a transmission circuit 24 and a reception circuit 25. Specifically, the integrated circuit device 20 is configured by a package including an integrated circuit 201 having a controller 23 and a bidirectional buffer 26. The package is provided with a package wiring 202 for connecting the integrated circuit 201 to the outside and an input / output terminal 20a. When the integrated circuit device 20 is connected to the test board 10, the bidirectional buffer 26 is connected to the test board 10 via the package wiring 202 and the input / output terminal 20a. 2 shows one bidirectional buffer 26, one package wiring 202, and one input / output terminal 20a. However, the bidirectional buffer, package wiring, and the like included in the integrated circuit device of the present invention are shown in FIG. The number of input / output terminals is not limited.

  The controller 23 includes a write circuit, a read circuit, an input circuit, an output circuit, and the like in addition to the illustrated elements. For example, the controller 23 outputs a signal input to the write circuit to the bidirectional buffer 26. Further, the controller 23 reads a signal input from the bidirectional buffer 26 to the read circuit and performs various processes. Further, the controller 23 switches between an AC test operation, a DC test operation, and a normal operation in accordance with an instruction signal input through the input circuit.

  Further, during the DC test operation, the controller 23 causes the pattern generation circuit 21 to generate a fixed level signal (High or Low), switches the bidirectional buffer 26 to the transmission circuit 24, and outputs the signal to the outside. Further, the controller 23 switches the bidirectional buffer 26 to the receiving circuit 25 and outputs a signal received from the outside to the outside through the output circuit.

  Further, during the AC test operation, the controller 23 causes the pattern generation circuit 21 to generate a test pattern to which a non-test target pattern is added before and after. The controller 23 operates the transmission circuit 24 and the reception circuit 25 of the bidirectional buffer 26 simultaneously. Then, the controller 23 causes the pattern comparison circuit 22 to compare the test pattern with the reception pattern input to the reception circuit 25.

  The pattern generation circuit 21 generates a test pattern to which a non-test target pattern is added before and after the AC test operation. That is, the pattern generation circuit 21 generates a test pattern after generating a non-test target pattern for a predetermined period. Then, the pattern generation circuit 21 outputs the generated pattern to the outside via the bidirectional buffer 26 by inputting it to the above-described write circuit. The pattern generation circuit 21 generates a non-test target pattern for a predetermined period after the generation of the test pattern. An example of a non-test target pattern and a test pattern generated by the pattern generation circuit 21 are shown in FIG. FIG. 3A is an example of a non-test target pattern to be applied before the test pattern. FIG. 3B is an example of a test pattern generated following FIG. FIG. 3C is an example of a non-test target pattern that is generated after the generation of FIG.

  Here, the test pattern is, for example, a predetermined pseudo random pattern. In the test pattern, it is desirable that the portion where 0 or 1 continues is a length that is not regarded as a DC component (for example, within 7 bits to within 11 bits).

  Further, the non-test target pattern is a pattern for causing the pattern comparison circuit 22 described later to identify a period not to be tested. Here, when the pattern generation circuit 21 starts pattern generation from the pattern stop state, there is a DC component that passes through the filter circuit 12 during the transition period from the DC component to the AC component. Similarly, when the pattern generation circuit 21 stops pattern generation from the pattern generation state, there is a DC component that passes through the filter circuit 12 during the transition period from the AC component to the DC component. For this reason, in order to make this transition period non-test target, a non-test target pattern is added before and after the test pattern. The non-test target pattern may be, for example, a repeating pattern of 0101. The pattern generation circuit 21 generates a non-test target pattern before and after the test pattern for a predetermined period. As the predetermined period, a period (for example, several microseconds) sufficient for removing the influence of the DC component during such a transition period is determined in advance.

  The pattern comparison circuit 22 compares the test pattern generated by the pattern generation circuit 21 with the reception pattern during the AC test operation. The reception pattern is a pattern of signals input from the bidirectional buffer 26 to the above-described read circuit.

  The bidirectional buffer 26 operates by switching between the transmission circuit 24 and the reception circuit 25 during normal operation and DC test operation. In addition, the bidirectional buffer 26 operates the transmission circuit 24 and the reception circuit 25 simultaneously during the AC test operation. The transmission circuit 24 outputs the pattern output from the controller 23 to the outside. The reception circuit 25 outputs a reception pattern input from the outside to the controller 23.

  The tester 30 executes a test for the integrated circuit device 20. For example, during the DC test operation, the tester 30 generates a fixed level signal, inputs the signal to the integrated circuit device 20 via the test board 10, and compares the signal with a signal output from the output circuit of the integrated circuit device 20. In addition, the tester 30 receives a fixed level signal from the integrated circuit device 20 via the test board 10, and measures DC characteristics and the like. A known DC test technique performed on the integrated circuit device 20 connected via the test board 10 can be applied to the DC test performed by the tester 30.

  An example of the mounting structure of the integrated circuit test system 1 configured as described above is shown in FIG. In FIG. 4, the filter circuit 12 is configured by an inductor, and the termination circuit 13 is configured by a resistor. The package constituting the integrated circuit device 20 is mounted in a socket 10b provided on the test board 10. The test board wiring 11 electrically connects the input / output terminal 20a of the integrated circuit device 20 mounted in the socket 10b and the tester terminal 10a connected to the tester 30. The input / output terminal 20 a of the integrated circuit device 20 is connected to the bidirectional buffer 26 of the integrated circuit 201 via the package wiring 202. In FIG. 4, the tester 30 is not shown.

  Next, the operation of the integrated circuit test system 1 will be described.

  First, the DC test of the transmission circuit 24 and the reception circuit 25 will be described.

<DC test of transmission circuit>
Here, it is assumed that a signal instructing the DC test of the transmission circuit 24 is input to the controller 23 from the outside.

  In this case, the controller 23 causes the pattern generation circuit 21 to generate a high level and a low level, respectively. In addition, the controller 23 switches the bidirectional buffer 26 to the transmission circuit 24 to output a fixed level signal. The fixed level signal output from the integrated circuit device 20 passes through the filter circuit 12 of the test board 10 and is input to the tester 30. Then, the tester 30 determines whether a high level signal or a low level signal generated by the integrated circuit device 20 has been received.

<DC test of receiver circuit>
Here, it is assumed that a signal instructing a DC test of the receiving circuit 25 is input to the controller 23 from the outside.

  In this case, the controller 23 switches the bidirectional buffer 26 to the receiving circuit 25. Further, the tester 30 generates and outputs fixed levels of High level and Low level, respectively. The fixed level signal output from the tester 30 passes through the filter circuit 12 of the test board 10 and is input to the integrated circuit device 20. In the integrated circuit device 20, the signal from the tester 30 is received by the receiving circuit 25, and the controller 23 outputs the received high level or low level signal. This makes it possible to determine whether or not the integrated circuit device 20 has received a fixed level signal generated by the tester 30.

  The principle of such a DC test is schematically shown in FIG. In FIG. 5, it is assumed that the filter circuit 12 is configured by an inductor and the termination circuit 13 is configured by a resistor, as in the mounting example of FIG. As shown in FIG. 5, since the DC component is ω = 0, the impedance Z0 = 0 of the filter circuit 12 (inductor) is obtained. Therefore, the DC component is not affected by the filter circuit 12. In this way, DC level input from the integrated circuit device 20 to the tester 30 and DC level input from the tester 30 to the integrated circuit device 20 are possible via the test board 10, and the DC of the integrated circuit device 20 is enabled. Characteristics can be measured.

<AC test>
Here, it is assumed that a signal instructing the AC test is input to the controller 23 from the outside.

  In this case, the controller 23 causes the pattern generation circuit 21 to generate a test pattern, for example, as shown in FIG. In addition, the controller 23 causes the transmission circuit 24 and the reception circuit 25 to operate simultaneously in the bidirectional buffer 26. Therefore, the transmission circuit 24 outputs the pattern generated by the pattern generation circuit 21 to the outside.

  In addition, the receiving circuit 25 operating simultaneously receives a signal output from the transmitting circuit 24 to the outside. The receiving circuit 25 outputs the received signal to the controller 23. In the controller 23, the pattern comparison circuit 22 compares the test pattern generated by the pattern generation circuit 21 with the pattern of the received signal (reception pattern).

  The operations of these integrated circuit devices 20 are performed at an actual operation speed.

  FIG. 6 schematically shows the principle of such an AC test. Also in FIG. 6, as in the mounting example of FIG. 4, it is assumed that the filter circuit 12 is configured by an inductor, and the termination circuit 13 is configured by a resistor. As shown in FIG. 6, since the AC component is defined by Z0 = ωL (= 2πfL), the filter circuit 12 (inductor) has a high impedance. Therefore, the AC component is not affected by the wiring from the filter circuit 12 (inductor) to the tester terminal 10 a connected to the tester 30. At the same time, the transmission line (test board wiring 11, package wiring 202, etc.) from the receiving circuit 25 to the termination circuit 13 (resistance) is impedance-matched by the termination circuit 13 (resistance) provided on the filter circuit 12 side. Taken. For this reason, the waveform input to the receiving circuit 25 has no waveform distortion caused by the transmission path when the transmission path is correctly designed. Therefore, the received waveform observed by the receiving circuit 25 should be free from distortion as the received waveform 601. If the waveform observed by the receiving circuit 25 is distorted like the received waveform 602, the cause may be a defect in the integrated circuit 201 or a package in which the integrated circuit 201 is mounted. High nature. In this case, the comparison by the pattern comparison circuit 22 does not match and the test fails. As a result, such an integrated circuit device 20 can be removed as a defect.

  Further, when pattern generation is started from a state where pattern generation is stopped in the pattern generation circuit 21 at the start of the AC test, there is a component that passes through the filter circuit 12 (inductor) during the transition period from the DC component to the AC component. In this case, the waveform observed in the receiving circuit 25 is distorted due to the influence of the wiring from the filter circuit 12 (inductor) to the tester terminal 10 a connected to the tester 30. Therefore, by generating a sufficiently long non-test target pattern (for example, repetition of 0101) before the test pattern is generated, it is possible to make the pattern generated during this period non-test target.

  Further, when the pattern generation is stopped from the state where the pattern is generated in the pattern generation circuit 21 at the end of the AC test, there is a component that passes through the filter circuit 12 (inductor) in the transition period from the AC component to the DC component. Also in this case, the waveform observed by the receiving circuit 25 is distorted due to the influence of the wiring from the filter circuit 12 (inductor) to the tester terminal 10 a connected to the tester 30. Therefore, by generating a sufficiently long non-test target pattern (for example, repetition of 0101) after the test pattern is generated, it is possible to make the pattern generated during this period non-test target.

  Next, effects of the embodiment of the present invention will be described.

  The integrated circuit test system according to the embodiment of the present invention can share a test board for AC test and DC test at an actual operation speed including the connection part of the transmission / reception circuit and the package without increasing the cost. Enable AC testing.

  The reason for this is that, on the test board, a filter circuit that passes a DC component and cuts an AC component on a wiring that electrically connects the input / output terminal of the integrated circuit device to be tested and the tester terminal, and the input / output terminal This is because a termination circuit for terminating the transmission path from the filter circuit to the filter circuit is provided on the filter circuit side.

  In the DC test, a fixed level signal is generated in the tester and input to the integrated circuit device, and a fixed level signal is generated in the integrated circuit device and input to the tester to perform the DC test. At this time, since the signal (DC component) at a fixed level passes through the filter circuit on the test board wiring, a DC test of the transmission circuit and the reception circuit can be performed using a known DC test technique.

  Also, during an AC test, in an integrated circuit device connected to the same test board as during a DC test, a test pattern to which a non-test target pattern is added before and after it is generated and output from an input / output terminal by a bidirectional buffer. This is because the AC test is performed by receiving the pattern input to the input / output terminal by the bidirectional buffer and comparing the test pattern with the received pattern. At this time, a signal obtained by outputting the test pattern from the transmission circuit is input to the reception circuit that operates simultaneously with the transmission circuit. Since the test pattern (AC component) is cut by the filter circuit on the test board wiring, the received waveform observed by the receiving circuit is not affected by the wiring from the filter circuit to the tester terminal. Further, since the transmission line from the reception circuit to the filter circuit is impedance-matched by the termination circuit provided on the filter circuit side, the distortion due to the transmission line does not occur in the reception waveform. In addition, since a non-test target pattern is generated before and after the test pattern and the period is excluded from the test target, the transition period in which the received waveform is distorted due to the influence of the DC component at the start or end of pattern generation is excluded. The Therefore, when the test pattern generated in the integrated circuit device is compared with the received pattern and cannot be regarded as matching, it can be regarded as a failure of the integrated circuit device including the bidirectional buffer and the package wiring.

  As described above, since the AC test of this embodiment performs pattern generation and comparison in the integrated circuit device, the test of the integrated circuit device including the bidirectional buffer and the package wiring can be performed while enabling the test at the actual operation speed. Test is possible. As described above, this embodiment enables AC testing at an actual operation speed of an integrated circuit device without connecting expensive components such as a RAM. Furthermore, the present embodiment makes it possible to perform tests in the AC test and the DC test without using a dedicated board. As a result, since this embodiment does not require board replacement, the test time can be shortened. In addition, this embodiment does not require expensive parts such as RAM, and the test board can be constructed with inexpensive parts such as inductors and resistors, so that the cost can be reduced.

  In the embodiment of the present invention, the non-test target pattern and the test pattern are not limited to the specific example shown in FIG. The test pattern may be another pattern suitable as an AC test. The non-test target pattern may be another pattern that can be distinguished from the test pattern.

  In addition, the example in which the filter circuit provided on the wiring of the test board is configured by an inductor and the termination circuit is configured by a resistor has been mainly described, but these may be in other connection modes or other circuit configurations. Good.

  The present invention is not limited to the above-described embodiments, and can be implemented in various modes.

DESCRIPTION OF SYMBOLS 1 Integrated circuit test system 10 Test board 10a Tester terminal 10b Socket 11 Test board wiring 12 Filter circuit 13 Termination circuit 20 Integrated circuit device 20a Input / output terminal 21 Pattern generation circuit 22 Pattern comparison circuit 23 Controller 24 Transmission circuit 25 Reception circuit 26 Bidirectional Buffer 30 Tester 201 Integrated circuit 202 Package wiring

Claims (5)

On the wiring that electrically connects the input / output terminals of the integrated circuit device to be tested and the tester terminals connected to the tester,
A filter circuit that passes the DC component and cuts the AC component;
A termination circuit for terminating a transmission line from the input / output terminal of the integrated circuit device to the filter circuit on the filter circuit side;
With test board.   2. The integrated circuit device connected to the test board according to claim 1, wherein a test pattern to which a non-test target pattern is added before and after the test circuit is generated and output from the input / output terminal by a bidirectional buffer, An integrated circuit test method, wherein a pattern input to a terminal is received by the bidirectional buffer, and an AC (Alternating Current) test is performed by comparing the test pattern and the received pattern.   A fixed level signal is generated in the tester and input to the integrated circuit device via the test board according to claim 1, and a fixed level signal is generated and input to the tester in the integrated circuit device. An integrated circuit test method in which a DC (Direct Current) test is performed. A controller having a pattern generation circuit for generating a test pattern to which a test target pattern is added before and after the pattern, and a pattern comparison circuit for comparing the test pattern and the reception pattern;
A transmission circuit that outputs a pattern output from the controller to the outside; and a reception circuit that outputs a reception pattern input from the outside to the controller, and simultaneously operates the transmission circuit and the reception circuit during an AC test operation. A bidirectional buffer to
An integrated circuit device. A test board according to claim 1;
The integrated circuit device according to claim 4 connected to the test board as a test target;
The tester connected to the tester terminal;
Integrated circuit test system with

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