JP2008198761A - Semiconductor device - Google Patents

Abstract

A technique capable of suppressing unnecessary electromagnetic radiation (EMI) is provided.
An impedance balance element (first step) for impedance matching between a semiconductor chip, a power supply wiring for driving the semiconductor chip, a GND wiring, and a wiring path of the power supply wiring and a wiring path of the GND wiring. 1 element) 111 and 112, and a bypass capacitor (first capacitor) that electrically connects the GND wiring 121 and the power supply wiring 117 are provided in the same package, and the current when the semiconductor chip 101 is driven is all impedance The impedance balance elements 111 and 112 are configured to be arranged between the semiconductor chip 101 and the bypass capacitor 130 so as to flow through the balance element 111 or the impedance balance element 112. 1

Description

  The present invention relates to a semiconductor device technology, and more particularly to a technology for suppressing unnecessary electromagnetic radiation (EMI) from an electronic device including a semiconductor device including an active circuit such as a microcomputer (hereinafter referred to as a microcomputer).

  For example, in Japanese Patent Laid-Open No. 2001-119110 (Patent Document 1), in a printed circuit board on which an LSI is mounted, a first capacitor that electrically connects a power supply terminal and a via hole, a first power supply wiring, and a second power supply A wiring and a second capacitor, and in a predetermined frequency range, the characteristic impedance of the power supply wiring is set to be at least three times the impedance magnitude of the capacitor, and the length of the power supply wiring is set to 20 mm. A configuration is described in which the value is not less than the value obtained by multiplying the wavelength shortening rate of the printed circuit board and not more than the value obtained by multiplying the quarter wavelength of the upper limit frequency of the predetermined frequency by the wavelength shortening rate.

  Further, for example, Japanese Patent Laid-Open No. 2001-267702 (Patent Document 2) includes a first signal layer, a GND layer, a power supply layer, and a second signal layer, and the first signal layer to the ninth pad of the first signal layer. The pad is connected to a capacitor grounded to the GND layer and a power supply wiring provided extending to the upper layer of the sub power supply layer. The power supply wiring penetrates the GND layer and is connected to the sub power supply layer. The sub power supply layer is provided in the same layer as the main power supply layer, and is substantially elliptical so as not to be directly connected to the main power supply layer at a predetermined position in the substantially elliptical opening of the main power supply layer. A configuration in which a power supply voltage is supplied from a main power supply layer through an L-type filter is described.

  Further, for example, in Japanese Patent Laid-Open No. 2003-297963 (Patent Document 3), an IC mounting layer, a layer including an external power supply power pattern to which an external power supply is connected, and an IC mounting layer are opposite to each other. In the multilayer circuit board comprising a power wiring and a layer including a ground wiring to which both terminals of the bypass capacitor are connected to the IC power terminal, an IC power terminal power pattern in which the IC power terminal is connected in any layer The external power supply power pattern is connected to the bypass capacitor power supply wiring, and the bypass capacitor power supply wiring is connected to the IC power supply terminal power supply pattern. A certain configuration is described.

Further, for example, Japanese Patent Laid-Open No. 2003-223997 (Patent Document 4) discloses a DC power supply, a power conversion unit including a switching element and an inductor, a control circuit that controls the power conversion unit, a high-pressure discharge lamp DL, and power A polarity reversing unit interposed between the conversion unit and the high-pressure discharge lamp DL and a high-pressure discharge lamp starting device are provided, and the output characteristics at the time of full lighting are substantially constant currents in a low voltage state where the high-pressure discharge lamp is in the starting process. In a lighting device that has a substantially constant power characteristic in the vicinity of the characteristic and rated voltage, a configuration is described in which a voltage range that has a substantially constant power characteristic during dimming lighting is shifted or widened to a lower side of the lamp end voltage.
JP 2001-119110 A JP 2001-267702 A JP 2003-297963 A JP 2003-223997 A

  In recent years, as digital devices such as LSIs (Large Scale Integrated Circuits) and memories become faster and more densely mounted, obstacles to other electronic devices due to unnecessary electromagnetic radiation (EMI) from electronic devices equipped with these devices. Is a problem.

  This EMI not only causes other radio circuits to interfere with reception of radio waves and malfunctions, but also has an adverse effect on its own circuits. For this reason, it is important to develop a technique for reducing the EMI of a digital device.

  The inventor has studied a technique for reducing EMI and found the following problems.

  As a main cause of EMI from electronic equipment, a high-frequency current generated by a high-speed switching operation of an internal circuit of a digital device such as an LSI can be considered. When this high-frequency current is generated, the power-ground layer of a printed circuit board (PCB) on which the LSI is mounted may be excited to cause resonance. Further, it is considered that the high-frequency current propagated to the PCB further propagates to a harness attached for the purpose of external power supply and signal transmission / reception, and this harness acts as an antenna to generate EMI.

  In particular, in a radio noise frequency band (up to 200 MHz), which is a problem in electronic devices mounted on automobiles, a high-frequency current (common mode) that flows in the same phase through a harness power source and a reference potential ground (hereinafter referred to as GND) wiring. Current) is the main cause of EMI. For this reason, in an electronic device to which a harness is attached, it is important how to suppress the generation of the common mode current.

  As a result of studies by the present inventor, it is considered that there are mainly the following two factors that cause a common mode current in an electronic device in which a digital device such as a microcomputer is mounted. First, there is a component that is generated due to electrical coupling between a portion having a large potential fluctuation, such as a high-speed signal output wiring from an LSI or an oscillation circuit, and another wiring (potential fluctuation drive type). Second, there is a component due to inadvertent reflection due to imbalance of wiring impedance in a portion where high-frequency current flows, such as power supply wiring / GND wiring of PCB (current drive type).

  The former potential fluctuation drive type has a strong peak in the current spectrum at an even multiple of the microcomputer operating frequency and the signal driving frequency. On the other hand, the latter current drive type has a strong peak at an odd multiple of the microcomputer operating frequency in the current spectrum.

  As a method of suppressing a common mode current that directly excites EMI in an electronic device, a method of preventing a high frequency current that causes the common mode current from diffusing from the LSI to the wiring on the PCB is used.

  For example, in Patent Document 1, in order to prevent the high-frequency current generated inside the microcomputer from diffusing outside, an inductor with a pattern is formed in the power supply wiring to enhance the effect of the low-frequency pass filter. In Patent Document 4, a high frequency current bypass capacitor is mounted as close to the microcomputer as possible.

  However, in the methods according to Patent Documents 1 to 4, since there is still an impedance imbalance in the power supply wiring / GND wiring inside the microcomputer, which is a path for high-frequency current, generation of a common mode current that is a direct factor of EMI inside the microcomputer Can not be suppressed.

  An object of the present invention is to provide a technique capable of suppressing unnecessary electromagnetic radiation (EMI).

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a wiring board, a semiconductor chip mounted on the wiring board, a first power supply wiring that supplies a first power supply potential to the semiconductor chip, a second power supply wiring that supplies a second power supply potential, and the first The first element for adjusting the impedance of the power supply wiring and the wiring path of the second power supply wiring, and the first capacitor that electrically connects the first power supply wiring and the second power supply wiring are included in the same package. The first capacitor is wired so as to flow through the first element, and the first capacitor has a path distance from the semiconductor chip from the first to the first chip. It is configured to be connected to a position farther than the path distance to the element.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, EMI of the semiconductor device can be suppressed.

  Components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the first embodiment, as an example of a semiconductor device, a semiconductor chip is mounted on a wiring substrate having a two-layer wiring structure having a first wiring layer and a second wiring layer, and the semiconductor chip mounting surface of the semiconductor chip and the wiring substrate is sealed. A semiconductor device sealed with resin will be described. As an example of such a semiconductor device, for example, there is a microcomputer package in which an LSI (Large Scale Integrated Circuit) chip is mounted on a wiring board.

  In the first embodiment, for ease of explanation, the wiring layer structure of the wiring board is described as a two-layer structure, but the number of wiring layers is not limited to this. The semiconductor device can be applied to a semiconductor device having a plurality of wiring layers more than two layers depending on the function and application of the semiconductor device.

  FIG. 1 is a plan view showing a state in which the first wiring layer and the second wiring layer of the wiring board inside the package of the semiconductor device of Embodiment 1 are viewed from above, and FIG. 2 is a plan view shown in FIG. 3 is a plan view showing only the first wiring layer, FIG. 3 is a plan view showing only the second wiring layer in the plan view shown in FIG. 1, and FIG. 4 is an equivalent circuit diagram of the semiconductor device shown in FIG. It is.

  In FIG. 1, the semiconductor device 100 according to the first embodiment includes a wiring board 1. The wiring board includes two wiring layers including a first wiring layer shown in FIG. 1 and a second wiring layer shown in FIG. 3, and a semiconductor chip 101 is formed on the surface of the uppermost first wiring layer. It is installed. The semiconductor chip 101 is mounted in the center of the first wiring layer, and the semiconductor chip 101 is sealed with a sealing resin (sealing body) 2.

  1 shows a plan view of the wiring substrate 1 of the semiconductor device 100 as seen through the sealing resin 2, only the outline of the outer edge of the sealing resin 2 is shown by a dotted line in FIG. 1.

  Further, the power supply terminal formed on one main surface of the semiconductor chip 101 is electrically connected to the power supply wiring (first power supply wiring) 105 formed in the first wiring layer via the wire 102 which is a conductive member. It is connected. The semiconductor chip 101 is supplied with the first power supply potential (the power supply potential on the high potential side) via the power supply wiring 105.

  Further, a terminal for a reference potential (second power supply potential: hereinafter referred to as GND) lower than the first power supply potential formed on one main surface of the semiconductor chip 101 is a wire 103 which is a conductive member. Is electrically connected to a GND wiring (second power supply wiring) 106 formed in the first wiring layer. The semiconductor chip 101 is supplied with GND as the second reference potential via the GND wiring 106.

  The signal terminal formed on one main surface of the semiconductor chip 101 is electrically connected to the signal wiring 107 formed in the first wiring layer via the wire 104 which is a conductive member.

  Further, the power wiring 105 in the first wiring layer is electrically connected to the power wiring 116 (see FIG. 3) in the second wiring layer through the via 108. The GND wiring 106 in the first wiring layer is electrically connected to the GND wiring 119 (see FIG. 3) in the second wiring layer through the via 109. Here, the via 108 and the via 109 fill the via hole formed through the first wiring layer with a conductor to form an interlayer conductive path.

  Further, as shown in FIG. 2 or FIG. 3, the power supply wiring 116 of the second wiring layer is electrically connected to the power supply wiring 118 formed in the first wiring layer through the via 117, and the GND of the second wiring layer is formed. The wiring 119 is electrically connected to the GND wiring 121 formed in the first wiring layer through the via 120.

  The power supply wiring 118 shown in FIG. 2 is electrically connected to an external terminal for supplying power for driving the semiconductor chip 101 via the via 122 and the power supply wiring 123 (see FIG. 3). For this reason, all the power supply current when the semiconductor chip 101 is driven flows through the power supply wiring 118.

  2 is electrically connected to an external terminal for supplying a reference potential via a via 124 and a GND wiring 125 (see FIG. 3). For this reason, all of the GND current when the semiconductor chip 101 is driven flows through the GND wiring 121.

  The power supply wiring 118 and the GND wiring 121 are arranged along each other. Further, the power supply wiring 118 and the GND wiring 121 are arranged so as to extend from one corner portion outside the semiconductor chip 101 toward the corner portion of the wiring substrate 1.

  Further, the power supply wiring 118 and the GND wiring 121 shown in FIG. 2 are electrically connected via a bypass capacitor (first capacitor) 130. Further, as shown in FIG. 1, the power supply wiring 118, the GND wiring 121, and the bypass capacitor 130 are sealed so as to be included in the sealing body 2.

  As shown in FIG. 1, the semiconductor device 100 also includes an oscillation circuit 113, an internal step-down power supply capacitor 114, and a high-speed signal output damping resistor 115 inside the package.

  Here, the semiconductor device 100 according to the first embodiment includes impedance balance elements (first elements) 111 and 112 inside the package. The impedance balance elements 111 and 112 are disposed between the semiconductor chip 101 and the bypass capacitor 130.

  That is, the impedance balance elements 111 and 112 are connected to a position where the wiring path distance from the semiconductor chip 101 is shorter than the wiring path distance from the semiconductor chip 100 to the bypass capacitor 130.

  More specifically, the impedance balance element 112 is provided in the power supply wiring 118 through which all power supply currents when the semiconductor chip 101 is driven, and the impedance balance is provided in the GND wiring 121 through which all GND currents are supplied when the semiconductor chip 101 is driven. An element 111 is mounted.

  The impedance balance element 112 and the impedance balance element 111 are the wire 102, the power supply wiring 105, the via 108, the power supply wiring 116, the via 117, the power supply wiring 118, and the GND wiring path, which are the power supply wiring paths of the semiconductor device 100. This is an element for adjusting the impedance with the wire 103, the GND wiring 106, the via 109, the GND wiring 119, the via 120, and the GND wiring 121.

  Here, the adjustment of the impedance means matching the impedance between the power supply wiring path and the GND wiring path.

  The impedance balance elements 111 and 112 only need to have a function of matching the overall impedance between the power supply wiring path and the GND wiring path of the semiconductor device 100.

  As an element having such a function, for example, an inductor as shown in FIG. 4 can be used. In the first embodiment, an inductor element having a desired inductance is formed by making a part of the power supply wiring 118 and the GND wiring 121, for example, meandering wiring patterns.

  By using the inductor in which the wiring is processed into a desired shape as the impedance balance elements 111 and 112, the impedance balance elements 111 and 112 can be formed simultaneously with the wiring formation process of the first wiring layer in the manufacturing process of the semiconductor device 100. it can.

  Therefore, the manufacturing process can be simplified as compared with the case where the impedance balance elements 111 and 112 are mounted on the semiconductor device 100 as individual elements. In addition, since the number of individual components of the semiconductor device 100 can be reduced, the manufacturing cost can be reduced.

  By forming the impedance balance elements 111 and 112 in the GND wiring 121 and the power supply wiring 118, respectively, all the current that flows when the semiconductor chip 101 is driven flows through the impedance balance element 111 or the impedance balance element 112.

  Therefore, impedance matching between the power supply wiring path of the semiconductor device 100 and the GND wiring path can be easily achieved without requiring a complicated circuit.

  Further, by arranging the impedance balance elements 111 and 112 between the semiconductor chip 101 and the bypass capacitor 130, impedance matching between the power supply wiring path to the bypass capacitor and the GND wiring path can be performed.

  Here, the relationship between the impedance matching and the common mode current generated in the semiconductor device 100 will be described with reference to FIGS.

  FIG. 5 is an equivalent circuit diagram showing a state where the semiconductor device 100 according to the first embodiment is mounted on a printed circuit board and a harness connected to a power source is attached. In FIG. 5, the semiconductor device 100 according to the first embodiment is mounted on a printed circuit board 500. In addition, a harness 503 including a power supply wiring 501 and a GND wiring 502 is electrically connected to the printed circuit board 500.

  The power supply wirings 105, 116, and 118 of the semiconductor device 100 are electrically connected to the power supply wiring 501 of the harness 503 through the power supply wiring 504 of the printed circuit board 500. Further, the GND wirings 106, 119, and 121 of the semiconductor device 100 are electrically connected to the GND wiring 502 of the harness 503 through the GND wiring 505 of the printed circuit board 500.

  Further, in FIG. 5, the parasitic capacitance between the power supply wirings 105, 116, and 118 of the semiconductor device 100 and the GND 506 serving as a reference is the parasitic capacitance 507, the GND wirings 106, 119, and 121 of the semiconductor device 100 and the GND 506 serving as a reference. Parasitic capacitance is shown as parasitic capacitance 508.

  Here, when the semiconductor chip 101 mounted on the semiconductor device 100 operates, a through current 509 that causes noise flows from the power supply wirings 105, 116, 118 to the GND wirings 106, 119, 121.

  The circuit diagram shown in FIG. 5 can be approximated to the circuit diagram shown in FIG. FIG. 6 is an equivalent circuit diagram obtained by approximating the circuit diagram shown in FIG. 5 focusing on the noise generation mechanism.

  In FIG. 6, the semiconductor chip 101 shown in FIG. 5 can be approximated with a voltage source 510 as a noise generation source. In addition, the inductance components of the power supply wirings 105, 116, and 118 and the impedance balance element 112 shown in FIG. Further, the inductance components of the GND wirings 106, 119, 121 and the impedance balance element 111 shown in FIG.

  Further, the impedances of the power supply wiring 504 of the printed circuit board 500 and the power supply wiring 501 of the harness 503 shown in FIG. 5 are added together, and the impedance 513 shown in FIG. 6 and the GND wiring 505 of the printed circuit board 500 and the GND wiring 502 of the harness 503 are shown. These impedances are added together and shown as impedance 514 shown in FIG.

  Here, in the circuit shown in FIG. 6, the impedance of the bypass capacitor 130 is sufficiently smaller than the impedance of the inductors 511 and 512 in the semiconductor device 100 in the frequency band (˜200 MHz) that causes radio noise.

  Therefore, the circuit diagram shown in FIG. 6 can be further approximated to the circuit diagram shown in FIG. FIG. 7 is a circuit diagram further approximating the circuit diagram shown in FIG.

  In FIG. 7, a point on the circuit where the harness 503 illustrated in FIG. 5 is connected to the semiconductor device 100 is illustrated as a node 515. When attention is paid to the common mode current flowing through the harness, the common mode impedance of the harness can be expressed as an impedance 516 as shown in FIG.

  Here, conditions for suppressing the common mode current Ic flowing through the harness will be described.

  In FIG. 7, inductors 511 and 512 have inductances Lv and Lg, respectively, and parasitic capacitances 508 and 507 have capacitances Cv and Cg, respectively. Further, when the impedance 516 is Zc, the potential difference between the node 515 and the reference GND 506 (see FIG. 5) is Vc, and the voltage of the voltage source 510 is Vd, the potential difference Vc can be expressed by Expression (1).

  Here, since the magnitude of the common mode current Ic flowing through the harness is proportional to the potential difference Vc, the common mode current Ic can be suppressed by reducing Vc. For this reason, the conditions for the inductances Lv and Lg and the capacitances Cv and Cg for suppressing the common mode current Ic can be obtained from the equation (1). This is shown in equation (2).

  The common mode current Ic can be suppressed by adjusting the inductances Lv and Lg and the capacitances Cv and Cg to have the relationship shown in the expression (2).

  The semiconductor device 100 of the first embodiment can be adjusted by the impedance balance elements 111 and 112 (FIG. 5) so that the inductances Lv and Lg and the capacitances Cv and Cg satisfy the relationship of the expression (2). For this reason, it is possible to suppress the generation of the common mode current Ic that occurs when the semiconductor device 100 is mounted on the printed circuit board to which the harness is attached and driven.

  Next, as a comparative example of the first embodiment, a semiconductor device 300 not equipped with the impedance balance elements 111 and 112 is prepared from the configuration of the semiconductor device 100 shown in FIG. The confirmed result will be described.

  FIG. 8 shows the amount of common mode current generated when an electronic device in which the semiconductor device 100 according to the first embodiment is mounted and an electronic device in which the semiconductor device 300, which is a comparative example of the first embodiment, is operated. It is explanatory drawing which compared these.

  In FIG. 8, a line connecting round plots indicates the amount of common mode current for each frequency that flows through the harness attached to the electronic device when the semiconductor device 100 of the first embodiment is mounted on the electronic device. Further, the line connecting the square plots indicates the common mode current amount for each frequency flowing in the harness attached to the electronic device by mounting the semiconductor device 300 as the comparative example of the first embodiment on the electronic device.

  The semiconductor device 300 as a comparative example has the same configuration as the semiconductor device 100 except that the impedance balance elements 111 and 112 shown in FIG. 1 are not mounted. In FIG. 8, the horizontal axis represents the frequency, and the vertical axis represents the common mode current amount (noise level).

  As shown in FIG. 8, the electronic device in which the semiconductor device 100 according to the first embodiment is mounted has a common mode current amount that causes EMI at almost all frequencies compared to the electronic device in which the semiconductor device 300 is mounted. It can be seen that is decreasing. In particular, at 80 MHz, which is a problem due to noise mixing in FM radio, the electronic device mounted with the semiconductor device 100 has a common mode current amount of about 20 dBμA smaller than the electronic device mounted with the semiconductor device 300. I understand.

  The semiconductor device 100 according to the first embodiment includes impedance balance elements 111 and 112 inside the semiconductor device, and matches the impedance of the power supply wiring path and the GND wiring path inside the semiconductor device. Generation of common mode current can be suppressed. For this reason, it is possible to suppress unnecessary electromagnetic radiation (EMI) generated in the electronic device on which the semiconductor device 100 is mounted.

  Further, by suppressing the generation of the common mode current inside the semiconductor device 100, it is possible to suppress the EMI without arranging a complicated circuit for suppressing the generation of EMI on the printed circuit board on which the semiconductor device 100 is mounted. It becomes possible.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.

  (A) First, the wiring board 1 shown in FIG. 1 is prepared. In this wiring board preparation step, the wiring board 1 is prepared in a state where a plurality of wiring boards 1 as shown in FIG. 1 are connected.

  Here, at the stage of this wiring board preparation process, power wirings 105, 116, 118, 123 and GND wirings 106, 119, 121, 125 are formed on the wiring board 1 in a predetermined wiring pattern. Are electrically connected to the external terminal for supplying power supply potential and the external terminal for supplying reference potential, respectively. Further, the signal wiring 107 is electrically connected to an external terminal for electric signal input / output formed on the wiring board 1.

  Further, an impedance balance element 112 is formed on the power supply wiring 118, and an impedance balance element 111 is formed on the GND wiring 121, respectively. A bypass capacitor 130, an oscillation circuit 113, an internal step-down power supply capacitor 114, and a high-speed signal output damping resistor 115 are also formed or mounted on the main surface of the wiring board 1, respectively.

  (B) Next, the semiconductor chip 101 is mounted in the semiconductor chip mounting region of the wiring board 1 prepared in the step (a). In this semiconductor chip mounting step, the semiconductor chip 101 is mounted on the semiconductor chip mounting region of the wiring board 1 via an adhesive.

  Wires 102, 103, and 104 are wire-bonded to the power supply terminal, the GND terminal, and the signal terminal formed on the main surface of the semiconductor chip 101, and the power supply wiring 105, the GND wiring 106, and the signal wiring 107 are respectively connected. Electrically connected.

  (C) Next, semiconductor chip 101, wires 102, 103, 104, power supply wirings 105, 118, GND wirings 106, 121, signal wiring 107, oscillation circuit 113, and internal step-down power supply formed on wiring board 1 The capacitor 114, the high-speed signal output damping resistor 115, the impedance balance elements 111 and 112, and the bypass capacitor 130 are sealed with the sealing resin 2.

  (D) Finally, the connected wiring substrate 1 is separated into pieces together with the sealing resin 2 to obtain the semiconductor device 100.

(Embodiment 2)
In the first embodiment, the semiconductor device using the inductor obtained by processing the wiring into a desired shape as the impedance balance element has been described. In the second embodiment, a semiconductor device using individual component elements as impedance balance elements will be described.

  Next, Embodiment 2 will be described with reference to FIGS. 9, 10, 11, and 12. 9 is a plan view showing a state in which the first wiring layer and the second wiring layer inside the package of the semiconductor device of the second embodiment are viewed from above, and FIG. 10 is a plan view of FIG. 11 is a plan view showing only the first wiring layer, FIG. 11 is a plan view showing only the second wiring layer in the plan view shown in FIG. 9, and FIG. 12 is an equivalent circuit diagram of the semiconductor device shown in FIG.

  In FIG. 9, in the semiconductor device 200 of the second embodiment, the power supply wiring 118 is divided in the middle of the wiring path. A pair of impedance balance element pads (first terminals) 212, which are conductive members for mounting elements, are formed at the ends of the wirings at the divided portions.

  The GND wiring 121 is also divided in the middle of the wiring path, and a pair of impedance balance element pads (second terminals) 211 that are conductive members for mounting elements are formed at the ends of the wiring.

  The impedance balance element pads 211 and 212 are mounted on the impedance balance element pads 211 and 212 as the individual elements by adjusting the impedance adjusting element (first element) described in the first embodiment, respectively. Can be connected.

  According to the second embodiment, by forming the impedance balance element pads 211 and 212, all the currents flowing when driving the semiconductor chip 101 adjust the impedance mounted on the impedance balance element pads 211 and 212. Will flow through the element.

  As an element mounted on the impedance balance element pads 211 and 212, for example, an individual element of an inductor can be used.

  Here, each wiring formed on the wiring board 1 may not necessarily have a constant impedance value due to a processing accuracy error or the like. In the semiconductor device 200 according to the second embodiment, it is possible to appropriately select and mount individual elements (impedance balance elements) corresponding to each wiring impedance inside the semiconductor device.

  For this reason, since the impedance of the power supply wiring path and the GND wiring path can be matched, the common mode current generated in the semiconductor device can be suppressed, and the reliability can be improved.

  Moreover, the semiconductor device 200 of the second embodiment can mount an impedance balance element according to the mounting conditions of the user. For this reason, the performance of the semiconductor device can be improved.

  Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. In the second embodiment, since the steps (c) and (d) are common to the method for manufacturing the semiconductor device 100 described in the first embodiment, the description thereof is omitted.

  (A) First, the wiring board 1 shown in FIG. 9 is prepared. In this wiring board preparation step, the wiring board 1 is prepared in a state where a plurality of wiring boards 1 as shown in FIG. 9 are connected.

  Here, at the stage of this wiring board preparation process, power wirings 105, 116, 118, 123 and GND wirings 106, 119, 121, 125 are formed on the wiring board 1 in a predetermined wiring pattern. Are electrically connected to the external terminal for supplying power supply potential and the external terminal for supplying reference potential, respectively. Further, the signal wiring 107 is electrically connected to an external terminal for electric signal input / output formed on the wiring board 1.

  Further, the power supply wiring 118 and the GND wiring 121 are divided as shown in FIG. 9, and a pair of impedance balance element pads 212 and 211 for mounting elements are formed at the ends of the wiring, respectively.

  A bypass capacitor 130, an oscillation circuit 113, an internal step-down power supply capacitor 114, and a high-speed signal output damping resistor 115 are also formed or mounted on the main surface of the wiring board 1, respectively.

  (B) Next, the semiconductor chip 101 is mounted in the semiconductor chip mounting region of the wiring board 1 prepared in the step (a). In this semiconductor chip mounting step, the semiconductor chip 101 is mounted on the semiconductor chip mounting region of the wiring board 1 via an adhesive.

  Wires 102, 103, and 104 are wire-bonded to the power supply terminal, the GND terminal, and the signal terminal formed on the main surface of the semiconductor chip 101, and the power supply wiring 105, the GND wiring 106, and the signal wiring 107 are respectively connected. Electrically connected.

  Here, in the second embodiment, before the (c) sealing step, which is the next step, impedance matching between the power supply wiring path and the GND wiring path is performed on the impedance balance element pads 211 and 212, respectively. An impedance balance element that is an individual element for mounting is mounted.

  As a mounting method of the impedance balance element, for example, a method of mounting on the impedance balance element pads 211 and 212 via a conductive connection member such as solder can be exemplified.

  Steps (c) and (d) can be manufactured in the same manner as the manufacturing method described in the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to an electronic device in which a semiconductor device having an active circuit such as a microcomputer is mounted.

It is a top view which shows the state which looked at the 1st wiring layer and the 2nd wiring layer inside the package of the semiconductor device which is Embodiment 1 of this invention from the upper part. FIG. 2 is a plan view showing only a first wiring layer in the plan view shown in FIG. 1. FIG. 2 is a plan view showing only a second wiring layer in the plan view shown in FIG. 1. FIG. 2 is an equivalent circuit diagram of the semiconductor device shown in FIG. 1. It is an equivalent circuit diagram which shows the state which mounted the semiconductor device 100 of Embodiment 1 of this invention on the printed circuit board, and attached the harness connected to the power supply. FIG. 6 is a circuit diagram approximating the circuit diagram shown in FIG. 5. FIG. 7 is a circuit diagram further approximating the circuit diagram shown in FIG. 6. Description of comparison of the amount of common mode current generated when operating an electronic device mounted with the semiconductor device of the first embodiment of the present invention and an electronic device mounted with a semiconductor device which is a comparative example of the first embodiment FIG. It is a top view which shows the state which piled up the 1st wiring layer and the 2nd wiring layer in the package of the semiconductor device of Embodiment 2 of this invention from the upper part. FIG. 10 is a plan view showing only the first wiring layer in the plan view shown in FIG. 9. FIG. 10 is a plan view showing only a second wiring layer in the plan view shown in FIG. 9. FIG. 10 is an equivalent circuit diagram of the semiconductor device shown in FIG. 9.

Explanation of symbols

1 Wiring board 2 Sealing resin (sealing body)
100, 200, 300 Semiconductor device 101 Semiconductor chips 102, 103, 104 Wires 105, 116, 118, 123 Power supply wiring (first power supply wiring)
106, 119, 121, 125 GND wiring (second power supply wiring)
107 Signal wiring 108, 109, 117, 120, 122, 124 Via 111, 112 Impedance balance element (first element)
113 Oscillator circuit 114 Capacitor 115 for internal step-down power supply Damping resistor 130 for high-speed signal output Bypass capacitor (first capacitor)
211 Pad for impedance balance element (second terminal)
212 Pad for impedance balance element (first terminal)
500 Printed circuit boards 501, 504 Power supply wiring 502, 505 GND wiring 503 Harness 506 GND
507, 508 Parasitic capacitance 509 Through current 510 Voltage source 511, 512 Inductor 513, 514, 516 Impedance 515 Node

Claims (3)

A wiring board;
A semiconductor chip mounted on the wiring board;
A sealing body for sealing the semiconductor chip,
The wiring board is
A first power supply wiring for supplying a first power supply potential to the semiconductor chip;
A second power supply wiring for supplying a second power supply potential lower than the first power supply potential to the semiconductor chip;
A first element disposed in the middle of the path of the first power supply wiring and the second power supply wiring, for adjusting the impedance between the first power supply wiring and the second power supply wiring;
A first capacitor that electrically connects the first power supply wiring and the second power supply wiring is included in the sealing body;
The first element is arranged so that all the current when the semiconductor chip is driven flows through the first element,
The semiconductor device, wherein the first capacitor is connected to a position where a path distance from the semiconductor chip is longer than a path distance from the semiconductor chip to the first element. The semiconductor device according to claim 1,
The semiconductor device, wherein the first element is an inductor formed by processing each of the first power supply wiring and the second power supply wiring into a desired shape. The semiconductor device according to claim 1,
The first power supply wiring is divided in the middle of the wiring path, and a pair of first terminals for mounting elements is formed at the wiring end portion of the divided portion,
The second power supply wiring is divided in the middle of the wiring route, and a pair of second terminals for element mounting is formed at the wiring end portion of the divided portion,
The first element is electrically connected between the pair of first terminals formed at the dividing portion of the first power supply wiring and between the pair of second terminals formed at the dividing portion of the second power supply wiring. A semiconductor device is mounted so as to be connected to the semiconductor device.

Images