JP2008193210A - Analog-to-digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit scale and power consumption in a flash type A/D converter. <P>SOLUTION: A plurality of transistors N<SB>0</SB>to N<SB>n</SB>having respectively different threshold voltages are arranged in parallel, an analog input signal is supplied to respective gates of the plurality of transistors N<SB>0</SB>to N<SB>n</SB>and output signals from respective transistors N<SB>0</SB>to N<SB>n</SB>are encoded to obtain a digital output signal, so that as compared with a conventional case that comparators each of which is composed of at least two transistors are connected in parallel, the number of transistors to be used can be reduced to a half and the necessity of a reference voltage generation circuit can be eliminated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an analog-digital converter, and is particularly suitable for use in a flash type A / D converter.

In recent years, A / D converters that do not use an operational amplifier have been actively developed with the progress of lowering the voltage of an analog circuit in an analog-digital mixed system LSI. A typical example is a flash (parallel) A / D converter. Flash type, as shown in FIG. 3, the number of comparators 51 are arranged in parallel, the voltage value V _in of the analog input signal is compared simultaneously with a plurality of reference voltage values V _R0 ~V _Rn, the analog input voltage V _in Which reference voltages V _{R0 to} V _Rn match with each other (for example, refer to Patent Documents 1 and 2).
Japanese Patent Laid-Open No. 5-199116 Japanese Patent Laid-Open No. 9-83316

  Since the flash type A / D converter determines the level of the analog input signal with a single operation, it is suitable for speeding up. However, as shown in FIG. 3, it is necessary to provide a large number of comparators 51 and a reference voltage generation circuit 52 in which a plurality of resistors R are connected in series. For example, in 10 bits, 1023 comparators 51 and 1023 resistors R are required, and the comparator 51 that compares two inputs is configured by combining at least four transistors. Therefore, at least 4092 transistors are required. It becomes. Therefore, there is a problem that the circuit scale and power consumption increase.

  The present invention has been made to solve such a problem, and an object of the present invention is to reduce the circuit scale and power consumption of a flash A / D converter.

  In order to solve the above problems, in the present invention, a plurality of transistors having different threshold voltages are arranged in parallel, an analog input signal is supplied to each gate of the plurality of transistors, and an output signal of each transistor is encoded. Thus, a digital output signal is obtained.

  According to the present invention configured as described above, a transistor whose analog input voltage supplied to the gate is smaller than the threshold voltage is turned off, and a transistor larger than the threshold voltage is turned on. Thus, the voltage level of the analog input signal is determined depending on which transistor is turned off or on, and a digital output signal corresponding to the voltage level can be obtained. Compared to the conventional example in which a comparator composed of at least two transistors is connected in parallel, the number of transistors used for determining the voltage level can be halved. For this reason, the circuit scale and power consumption can be reduced.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a configuration example of the flash A / D converter according to the present embodiment. As shown in FIG. 1, the flash A / D converter according to the present embodiment includes a parallel circuit unit 1 and an encoder 2 (corresponding to the encode circuit unit of the present invention).

The parallel circuit unit 1 is configured by connecting a plurality of transistors N ₀ , N ₁ , N ₂ ,..., N _n having different threshold voltages in parallel between a power supply VDD and a ground GND. Resistors R _{0 to} R _n are connected between the transistors N _{0 to} N _n and the power supply VDD. Here, the plurality of transistors N _{0 to} N _n are N-channel MOS transistors. In addition, the threshold voltage of each of the transistors N _{0 to} N _n is adjusted by changing circuit parameters relating to the transistor, for example, the gate length L and the gate width W.

_V T0 threshold voltage of each transistor _N 0 to N _{n respectively, V T1, V T2, ···} , when the _{V Tn,} for example, _{V T0 <V T1 <V T2} < so as to be · · · _{<V Tn} The threshold voltage of each of the transistors N _{0 to} N _n is adjusted. Then, an analog input signal is supplied to each gate of the transistors N _{0 to} N _n having different threshold voltages. In this manner, the transistor analog input voltage V _in supplied to the gate is less than the threshold voltage off, is turned on larger transistors than the threshold voltage.

The encoder 2 encodes the output signal of each of the transistors N _{0 to} N _n to obtain a digital output signal. That is, the voltage value _V 0 ~V _n of the signal output from the transistors _N 0 to N _n, the transistor _N 0 to N _n is in either the high level or low level in response to the on or off. The encoder 2 generates a digital signal of a predetermined bit according to which voltage value of the output signal of each of the transistors N _{0 to} N _n is high level and which voltage value is low level.

As described above in detail, in this embodiment, a plurality of transistors N _{0 to} N _n having different threshold voltages are arranged in parallel, and an analog input signal is supplied to each gate of the plurality of transistors N _{0 to} N _n . A digital output signal is obtained by encoding the output signal of each of the transistors N _{0 to} N _n . According to such a configuration, the number of transistors used is half that of a conventional flash A / D converter in which a comparator composed of at least two transistors is connected in parallel, and a reference voltage generation circuit is also required. Absent. For this reason, the circuit scale and power consumption can be reduced.

In the above embodiment, the example in which the resistors R _{0 to} R _n are used as the load has been described. However, a constant current circuit may be used.

  In the above embodiment, an example in which N-channel MOS transistors are used as the plurality of transistors has been described. However, P-channel MOS transistors may be used. The threshold voltage of the PMOS transistor in this case can also be adjusted by changing circuit parameters relating to the transistor, for example, the gate length L and the gate width W. Alternatively, the threshold voltage of each transistor can be made different by changing the voltage value supplied to the back gate of the P-channel MOS transistor.

  FIG. 2 is a diagram showing a configuration example of a flash A / D converter using a P-channel MOS transistor. The flash A / D converter shown in FIG. 2 includes a parallel circuit unit 11, an encoder 12 (corresponding to the encode circuit unit of the present invention), and a reference voltage generation circuit 13.

The parallel circuit unit 11 is configured by connecting a plurality of PMOS transistors P ₀ , P ₁ , P ₂ ,..., P _n having different threshold voltages in parallel between the power supply VDD and the ground GND. . Resistors R _{0 to} R _n are connected between the transistors P _{0 to} P _n and the ground GND. _V T0 threshold voltage of each transistor _P 0 to P _{n, respectively, V T1, V T2, ···} , when the _{V Tn,} for example, _{V T0 <V T1 <V T2} < so as to be · · · _{<V Tn} The threshold voltages of the transistors P _{0 to} P _n are adjusted.

Here, the threshold voltage of each transistor P ₀ to P _n is adjusted by varying the transistor P ₀ to P voltage value supplied to the back gate of the _n. The voltage value supplied to the back gate is generated by the reference voltage generation circuit 13. The reference voltage generation circuit 13 is configured by connecting a plurality of resistors R in series, and voltages having different values are taken out from input / output taps of the resistors and supplied to the back gates of the transistors P _{0 to} P _n , respectively. It has come to be.

An analog input signal is supplied to each gate of the transistors P _{0 to} P _n having different threshold voltages. In this way, the transistor analog input voltage V _in supplied to the gate is less than the threshold voltage is turned off, it is turned on larger transistors than the threshold voltage. The encoder 12 encodes the output signals of the transistors P _{0 to} P _n to obtain a digital output signal.

  When configured as shown in FIG. 2, the number of transistors used can be halved compared to a conventional flash A / D converter in which a comparator composed of at least two transistors is connected in parallel. For this reason, the circuit scale and power consumption can be reduced.

  In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. In other words, the present invention can be implemented in various forms without departing from the spirit or main features thereof.

  The present invention is suitable for use in a flash-type A / D converter that simultaneously compares the voltage value of an analog input signal with a plurality of different voltage values by a plurality of transistors.

It is a figure which shows the structural example of the flash type A / D converter by this embodiment. It is a figure which shows the other structural example of the flash type A / D converter by this embodiment. It is a figure which shows the structure of the conventional flash type A / D converter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,11 Parallel circuit part 2,12 Encoder 13 Reference voltage generation circuit

Claims (5)

A plurality of transistors having different threshold voltages connected in parallel between a power source and a ground, and a parallel circuit unit configured to supply an analog input signal to each gate of the plurality of transistors;
An analog-to-digital converter, comprising: an encoding circuit unit that encodes output signals of the plurality of transistors to obtain a digital output signal. 2. The analog-digital converter according to claim 1, wherein the plurality of transistors are N-channel MOS transistors. 3. The analog-to-digital converter according to claim 2, wherein the threshold voltages of the plurality of transistors are varied by varying circuit parameters relating to the N-channel MOS transistor. 2. The analog-to-digital converter according to claim 1, wherein the plurality of transistors are P-channel MOS transistors. 5. The analog-digital converter according to claim 4, wherein the threshold voltages of the plurality of transistors are made different by making the voltage values supplied to the back gates of the P-channel MOS transistors different.