JP2008182156A - Metal oxide device and manufacturing method thereof - Google Patents

Abstract

To provide a memory capable of more stable memory retention, a metal oxide element in which a metal oxide layer exhibiting ferroelectric characteristics is arranged on a semiconductor substrate, and a method for manufacturing the same are provided.
An intermediate electrode layer is formed on a semiconductor substrate, and a metal oxide layer having a thickness of, for example, 100 nm formed of bismuth (Bi), titanium (Ti), and oxygen is formed thereon. The upper electrode 104 is provided, and an ohmic contact 105 is provided on a part of the semiconductor substrate 101. For example, the metal oxide layer 104 may be ₃ nm of Bi ₄ Ti ₃ O ₁₂ stoichiometric composition in a base layer containing excess Ti compared to the stoichiometric composition of Bi ₄ Ti ₃ O _12. It is composed of a plurality of fine crystal grains of about 15 nm. The metal oxide layer 104 is formed by sputtering at a low temperature of 30 to 180 ° C.
[Selection] Figure 1

Description

  The present invention relates to a metal oxide element in which, for example, a metal oxide layer exhibiting ferroelectric characteristics is disposed on a substrate (substrate) made of a semiconductor, and a method for manufacturing the same.

  Conventionally, semiconductor materials have been mainly used for devices (memory) that are mounted on network devices and information terminals and store information. As one of the memories using a semiconductor, a DRAM (Dynamic Random Access Memory) is widely used (see Non-Patent Document 1). A unit storage element (hereinafter referred to as a memory cell) of a DRAM is composed of one storage capacitor and one MOSFET (Metal-oxide-semiconductor field effect transistor), and the charge stored in the storage capacitor of the selected memory cell. The voltage corresponding to the state is taken out as “on” or “off” of the electrical digital signal from the bit line, so that the stored data is read out.

  However, in the DRAM, when the power is turned off, it is impossible to maintain the state of the storage capacity, and the stored information is erased. In other words, DRAM is a volatile memory element. As is well known, a DRAM requires a refresh operation for rewriting data, and has a drawback that the operation speed is reduced.

  In order to realize the recent expansion of the multimedia information society, and further to realize ubiquitous services, more sophisticated memories are required. For example, the functions required of the memory installed in ubiquitous terminals include high speed, long-term retention period, environmental resistance, low power consumption, and non-volatility that keeps stored information even when the power is turned off. It is said that. ROM (Read only Memory) is well known as a non-volatile memory, but once stored (written) data cannot be erased, and has a major disadvantage that it cannot be rewritten. Yes.

  On the other hand, although it is a kind of ROM, a flash memory using an EEPROM (Electrically Erasable Programmable Read Only Memory) capable of erasing and writing a limited number of times has been developed (patent) Reference 1, Non-Patent Documents 1 and 2). This flash memory is used in many fields as a practical non-volatile memory.

  In a memory cell of a typical flash memory, a gate electrode portion of a MOSFET has a stack gate structure including a plurality of layers each having a control gate electrode and a floating gate electrode. In the flash memory, data can be recorded by utilizing the fact that the threshold value of the MOSFET changes depending on the amount of charge accumulated in the floating gate.

  Writing data in the flash memory is performed by hot carriers generated by applying a high voltage to the drain region overcoming the energy barrier of the gate insulating film. In addition, data is written by injecting electric charges (generally electrons) from the semiconductor substrate to the floating gate by applying a high electric field to the gate insulating film to flow an FN (Fowler-Nordheim) tunnel current. Is done. Data is erased by extracting charges from the floating gate by applying a high electric field in the opposite direction to the gate insulating film.

  A flash memory does not require a refresh operation like a DRAM, but requires a high voltage of about 18 V in order to use the FN tunnel phenomenon, and the time required for writing and erasing data is orders of magnitude higher than that of a DRAM. There is a problem of becoming longer. Further, when data writing / erasing is repeated, the gate insulating film deteriorates, so that the number of rewrites is limited to some extent.

  In contrast to the flash memory described above, as a new non-volatile memory, a ferroelectric memory using ferroelectric polarization (hereinafter referred to as FeRAM (Ferroelectric RAM)) or a ferromagnetic memory using ferromagnetic resistance ( MRAM (Magnetoresist RAM) has been attracting attention and has been actively researched.FeRAM has already been put into practical use, and if it can solve various problems, it will be a portable memory. It is expected that not only logic DRAMs can be replaced.

  Thus, FeRAM expected as a substitute for flash memory is mainly classified into a stack type and an FET type. The stack type is also called a one-transistor one-capacitor FeRAM, and there are a stack type capacitor, a planar type capacitor, and a three-dimensional type capacitor. The stack type includes a one-transistor one-capacitor FeRAM and a two-transistor two-capacitor FeRAM in which two are stacked for stable operation.

  For example, as shown in FIG. 14, the stack type FeRAM includes a MOS transistor including a gate electrode 1405 provided on a semiconductor substrate 1401 via a source 1402, a drain 1403, and a gate insulating film 1404. A capacitor composed of a lower electrode 1411, a dielectric layer 1412 made of a ferroelectric material, and an upper electrode 1413 is connected to the source 1402. In the example of FeRAM shown in FIG. 14, the capacitor is connected to the source 1402 by the source electrode 1406. A drain electrode 1407 is connected to the drain 1403, and an ammeter is connected to the drain 1403.

  This FeRAM has a function of extracting “on” or “off” data by detecting the direction of polarization of the dielectric layer 1412 made of a ferroelectric material as a current flowing between the source and the drain (channel 1421). Yes. The ferroelectric polarization is non-volatile because it can be maintained without applying a voltage, but with the above structure, data is destroyed when data is read, and it is necessary to rewrite the data, resulting in high speed. There is a problem and a disadvantage that it is not suitable for high integration due to a large area occupied by one element.

  In contrast to the above-described stack type FeRAM, the FET type FeRAM is expected as the next-generation FeRAM. The FET type FeRAM is capable of nondestructive reading because the amount of polarization of the ferroelectric material does not change even when data is read from the operation principle, and high speed operation is expected. In addition, since the exclusive area can be reduced, it is advantageous for high integration.

JP-A-8-031960 Simon G., Physics of Semiconductor Devices, 1981 (S.M.Sze, "Physics of Semiconductor Devices", John Wiley and Sons, Inc.) Fujio Tsujioka, “Current Status and Prospects of Non-Volatile Memory”, Applied Physics, Vol. 73, No. 9, pp. 1166-1171, 2004.

  Actually, however, the MFIS type FeRAM among the FET type FeRAMs has a gate insulating film between the ferroelectric film and the semiconductor, so that a depolarizing electric field that cancels the polarization amount of the ferroelectric substance is generated. Furthermore, a high-quality high-dielectric material having polarization characteristics and orientation must be formed on an insulating film that is generally amorphous. However, it has been difficult to form a highly oriented ferroelectric on the insulating film by using an existing film formation method described later.

  For this reason, in the conventional FET type FeRAM, the polarization cannot be sustained by the depolarizing electric field, and the data cannot be retained for a long time. Furthermore, when the quality of the insulating film formed on the semiconductor is low, the amount of polarization of the ferroelectric material further decreases due to the leakage current generated by the electric field. For these reasons, in the conventional MFIS type FeRAM, the data retention period (data life) of the operation as a memory is only about 10 days, which is far from practical use.

By the way, among the FET type FeRAMs, in the MFMIS type FeRAM, since a ferroelectric can be formed on a crystalline metal electrode (Pt, SrRuO ₂ or the like is generally used), an insulating film like the MFIS type FeRAM structure is used. A high-quality ferroelectric layer can be formed without the need for forming a ferroelectric layer thereon. However, a stable film formation method has not yet been proposed for metal, and long-term memory retention has been realized due to the problem of polarization degradation due to a depolarizing electric field caused by an insulating film on a semiconductor. Absent.

  On the other hand, the MFS type FeRAM among the FET type FeRAMs does not require an insulating film on the semiconductor, so that a decrease in polarization due to a depolarizing electric field can be avoided in principle. However, since the ferroelectric layer is formed by the sol-gel method or MOCVD method, a high film formation temperature is required, and the surface of a semiconductor such as silicon (Si) is not oxidized or denatured. Many films and defects are formed. As a result, when an oxide film (interface oxide film) is formed at the interface between the semiconductor and the ferroelectric, a depolarizing electric field is generated as in the MFIS type FeRAM.

  Even if the interfacial oxide film is not formed, if many defect levels are formed at the interface, the influence of the electric charge of charge accumulation becomes large, and an accurate memory operation cannot be performed. Further, it is often reported that when the quality of the film is low, a leakage current flows in the film and the polarization characteristics for a long time cannot be maintained.

  The present invention has been made to solve the above-described problems, and an object thereof is to realize a memory capable of more stable storage and holding.

  The metal oxide device according to the present invention includes a semiconductor substrate composed of a semiconductor, an intermediate electrode layer formed on the semiconductor substrate, and a metal oxide formed on the intermediate electrode layer and having a variable electric resistance. At least a top layer formed on the metal oxide layer, wherein the metal oxide layer includes a base layer composed of at least a first metal and oxygen, and a first metal and a second metal. And a plurality of fine particles composed of oxygen and dispersed in the base layer. In the metal oxide element configured as described above, a predetermined voltage is applied between the semiconductor substrate and the upper electrode to change the resistance value of the metal oxide layer, thereby switching between a stable high resistance mode and a low resistance mode. For example, two different states can be obtained. For example, two different states can be read by measuring a current value when an appropriate voltage is applied to the upper electrode.

  In the metal oxide element, the fine particles are amorphous. Further, the base layer may be composed of the first metal, the second metal, and oxygen, and may have a smaller composition ratio of the second metal compared to the stoichiometric composition. The base layer may be made of a first metal, a second metal, and oxygen and may be amorphous. The metal oxide layer is in a first state having a first resistance value when a voltage exceeding the first voltage value is applied, and from the first resistance value when a voltage exceeding a second voltage value having a polarity different from that of the first voltage is applied. A second state having a high second resistance value is obtained. In this case, the metal oxide layer has different resistance values in the first state by application of voltages having different polarities. The metal oxide layer is preferably formed at 30 ° C. or higher and lower than 180 ° C. by sputtering. The first metal is titanium, the second metal is bismuth, and the base layer may be in an amorphous state composed of a layer containing excess titanium as compared with the stoichiometric composition.

  The method for manufacturing a metal oxide element according to the present invention includes a first step of forming an intermediate electrode layer on a semiconductor substrate, and plasma comprising an inert gas and an oxygen gas supplied at a predetermined composition ratio. A negative bias is applied to a target composed of at least a first metal and a second metal to cause particles generated from the plasma to collide with the target to cause a sputtering phenomenon, and a material constituting the target is formed on the semiconductor substrate. By depositing on the semiconductor substrate, a metal oxide layer comprising at least a base layer composed of a first metal and oxygen and a plurality of fine particles composed of the first metal, the second metal, and oxygen is brought into contact with the semiconductor substrate. And a second step of forming an upper electrode on the metal oxide layer, and the plasma is generated by electron cyclotron resonance and kinetic energy is generated by a divergent magnetic field. Ghee in which is as is an electron cyclotron resonance plasma given. In the second step, the temperature of the semiconductor substrate is set to 30 to 180 ° C. The first metal may be titanium and the second metal may be bismuth.

  As described above, according to the present invention, a semiconductor substrate composed of a semiconductor, an intermediate electrode layer formed on the semiconductor substrate, and an electric resistance that is formed on the intermediate electrode layer changes. A metal oxide element was composed of a metal oxide layer and an upper electrode formed on the metal oxide layer. As a result, according to the present invention, it is possible to change the resistance value of the metal oxide layer by applying a predetermined electric signal between the semiconductor substrate and the upper electrode, and stable high resistance mode and low resistance mode. Can be switched and two different states can be stably obtained, so that an excellent effect of realizing a memory capable of more stable storage and holding can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration example of a metal oxide element 100 according to an embodiment of the present invention. A metal oxide element 100 shown in FIG. 1 includes an intermediate electrode layer 102, a metal oxide layer 103, and an upper electrode 104 on the main surface of a semiconductor substrate 101. A part is provided with an ohmic contact 105. The metal oxide layer 103 is composed of bismuth (Bi), titanium (Ti), and oxygen, and is formed to have a thickness of 30 to 200 nm, for example, and is in contact with the intermediate electrode layer 102.

  The semiconductor substrate 101 is, for example, single crystal silicon. Further, the semiconductor substrate 101 is not limited to silicon, and may be composed of any of semiconductors such as germanium (Ge) and diamond, and compound semiconductors such as GaAs, InP, and GaN. The ohmic contact 105 is a region where an alloy layer such as silicide is formed. By applying a voltage from a power source between the upper electrode 104 and the ohmic contact 105, a voltage can be applied to the metal oxide layer 103 sandwiched between the semiconductor substrate 101 and the upper electrode 104. Therefore, the semiconductor substrate 101 becomes one electrode paired with the upper electrode 104.

The upper electrode 104 may be made of a noble metal such as platinum (Pt), Ru, gold (Au), silver (Ag), or a transition metal including tungsten (W). In addition, titanium nitride (TiN), hafnium nitride (HfN), tantalum nitride (TaN), strontium ruthenate (SrRuO ₂ ), zinc oxide (ZnO), tin lead oxide (IZO), lanthanum fluoride (LaF ₃ ), etc. Compounds such as transition metal nitrides, oxides, and fluorides, and composite layers obtained by laminating these may also be used.

  Further, like the metal oxide element 200 shown in FIG. 2, an ohmic contact 205 is provided on the back surface of the semiconductor substrate 101, and one lower electrode 206 that contacts the ohmic contact 205 and is paired with the upper electrode 104 is provided. Also good. Note that, similarly to the metal oxide element 100, the metal oxide element 200 includes an intermediate electrode layer 102, a metal oxide layer 103, and an upper electrode 104 on the main surface of the semiconductor substrate 101. Also in the metal oxide element 200, the metal oxide layer 103 is composed of bismuth (Bi), titanium (Ti), and oxygen, and may be formed to a thickness of, for example, 30 to 200 nm.

  Although the intermediate electrode layer 102, the metal oxide layer 103, and the upper electrode 104 described above will be described in detail later, an ECR sputtering apparatus as shown in FIG. ECR plasma composed of gas, xenon gas, oxygen gas, and nitrogen gas may be generated by a plasma source and sputtered using particles in the generated plasma.

  Here, the ECR sputtering apparatus will be described with reference to the schematic cross-sectional view of FIG. The ECR sputtering apparatus shown in FIG. 3 first includes a processing chamber 301 and a plasma generation chamber 302 that communicates therewith. The processing chamber 301 communicates with an evacuation device (not shown), and the inside of the processing chamber 301 is evacuated together with the plasma generation chamber 302 by the evacuation device.

  The processing chamber 301 is provided with a substrate holder 304 to which the semiconductor substrate 101 to be formed is fixed. The substrate holder 304 is inclined at a desired angle by a rotation mechanism (not shown) and can be rotated. By tilting and rotating the substrate holder 304, it is possible to improve the in-plane uniformity of the film and the step coverage with the material to be deposited. Further, a ring-shaped target 305 is provided so as to surround the opening region in the opening region into which the plasma from the plasma generation chamber 302 in the processing chamber 301 is introduced.

  The target 305 is placed in a container 305 a made of an insulator, and the inner surface is exposed in the processing chamber 301. In addition, a high frequency power source 322 is connected to the target 305 via a matching unit 321 so that, for example, a high frequency of 13.56 MHz can be applied. When the target 305 is a conductive material, direct current may be applied. The target 305 may be not only circular but also polygonal when viewed from above.

  The plasma generation chamber 302 communicates with the vacuum waveguide 306, and the vacuum waveguide 306 is connected to the waveguide 308 through the quartz window 307. The waveguide 308 communicates with a microwave generator (not shown). In addition, a magnetic coil (magnetic field forming means) 310 is provided around the plasma generation chamber 302 and at the top of the plasma generation chamber 302. These microwave generator, waveguide 308, quartz window 307, and vacuum waveguide 306 constitute a microwave supply means. There is also a configuration in which a mode converter is provided in the middle of the waveguide 308.

The operation example of the ECR sputtering apparatus in FIG. 3 will be described. First, after the processing chamber 301 and the plasma generation chamber 302 are evacuated, Ar gas or Xe gas, which is an inert gas, is introduced from an inert gas introduction unit 311. In addition, a reactive gas is introduced from the reactive gas introduction unit 312 to bring the inside of the plasma generation chamber 302 to a pressure of about 10 ⁻⁵ to 10 ⁻⁴ Pa, for example. In this state, a magnetic field of 0.0875 T (Tesla) is generated in the plasma generation chamber 302 from the magnetic coil 310, and then the plasma generation chamber 302 is passed through the waveguide 308, the quartz window 307, and the vacuum waveguide 306. A 2.45 GHz microwave is introduced into the inside, and an electron cyclotron resonance (ECR) plasma is generated. Note that 1T = 10000 Gauss.

  The ECR plasma forms a plasma flow in the direction of the substrate holder 304 by the divergent magnetic field from the magnetic coil 310. Among the generated ECR plasma, electrons penetrate through the target 305 by the divergent magnetic field formed by the magnetic coil 310 and are extracted to the semiconductor substrate 101 side and irradiated onto the surface of the semiconductor substrate 101. At the same time, positive ions in the ECR plasma are drawn out to the semiconductor substrate 101 side so as to neutralize the negative charge due to electrons, that is, to weaken the electric field, and are irradiated on the surface of the layer being formed. . Thus, while each particle is irradiated, some of the positive ions are combined with electrons to become neutral particles.

  In the thin film forming apparatus of FIG. 3, microwave power supplied from a microwave generation unit (not shown) is once branched in the waveguide 308, and plasma is supplied to the vacuum waveguide 306 above the plasma generation chamber 302. The generation chamber 302 is coupled from the side through a quartz window 307. By doing so, it becomes possible to prevent the scattered particles from adhering to the quartz window 307 from the target 305, and the running time can be greatly improved. In addition, a shutter or the like may be provided between the substrate to be processed and the target 305 to control the arrival of the raw material with respect to the substrate.

  Next, an example of a method for manufacturing the metal oxide element 100 having the configuration shown in FIG. 1 in this embodiment will be described with reference to FIGS. First, as shown in FIG. 4A, a semiconductor substrate 101 made of p-type silicon having a main surface of plane orientation (100) and a resistivity of 1 to 2 Ω-cm is prepared, and the surface of the semiconductor substrate 101 is made of sulfuric acid. And a mixture of pure water and hydrogen peroxide, and a mixture of pure water and dilute hydrogen fluoride water, followed by drying.

  Next, as shown in FIG. 4B, the above-described metal thin film 402 to be the intermediate electrode layer 102 is formed on the cleaned and dried semiconductor substrate 101. In forming the metal thin film 402, the above-described ECR sputtering apparatus is used, the semiconductor substrate 101 is fixed to the substrate holder 304 in the processing chamber 301, pure ruthenium (Ru) is used as the target 305, and xenon (Xe) is used as the plasma gas. The Ru film (metal thin film 402) is formed to cover the surface by the ECR sputtering method used.

The formation of the Ru film will be described in detail. In the ECR sputtering apparatus described above, first, the inside of the plasma generation chamber 302 is evacuated to a high vacuum state of the order of 10 ⁻⁴ to 10 ⁻⁵ Pa, and then the inside of the plasma generation chamber 302. In addition, for example, Xe gas is introduced at a flow rate of 26 sccm from the inert gas introduction unit 311, and the pressure in the plasma generation chamber 302 is set to, for example, about 10 ⁻¹ to 10 ⁻² Pa. Note that sccm is a unit of flow rate and indicates that 1 cm ³ of fluid at 1 atm flows at 0 ° C. per minute. Further, in the plasma generation chamber 302, a magnetic field of an electron cyclotron resonance condition is applied by supplying a coil current to the magnetic coil 310 at, for example, 26A.

  In addition, for example, a 2.45 GHz microwave (for example, 800 W) is supplied from a microwave generation unit (not shown), and this is supplied to the plasma generation chamber via the waveguide 308, the quartz window 307, and the vacuum waveguide 306. It introduce | transduces in 302, It is set as the state by which the plasma (ECR plasma) was produced | generated in the plasma production chamber 302 by introduction of this microwave.

  The generated plasma is emitted from the plasma generation chamber 302 to the processing chamber 301 side by the divergent magnetic field of the magnetic coil 310. Further, high frequency power (for example, 500 W) is supplied from a high frequency power source 322 to a target 305 made of Ru disposed at the outlet of the plasma generation chamber 302. As a result, Xe particles collide with the target 305 to cause a sputtering phenomenon, and Ru particles jump out of the target 305. The Ru particles that have jumped out of the target 305 reach the semiconductor substrate 101, whereby Ru is deposited on the semiconductor substrate 101 to form a metal thin film 402.

  By the Ru deposition by the ECR sputtering method described above, for example, a state in which the metal thin film 402 with a film thickness of about 20 nm is formed (FIG. 4B). Thereafter, the film formation is stopped by preventing the sputtered raw material from reaching the semiconductor substrate 101 with the aforementioned shutter closed. Thereafter, the plasma irradiation is stopped by stopping the supply of microwave power, the supply of each gas is stopped, the temperature of the semiconductor substrate 101 is lowered to a predetermined value, and a metal thin film is formed from the inside of the processing chamber 301. The semiconductor substrate 101 on which the 402 is formed is unloaded. The film thickness of the metal thin film 402 is not limited to 20 nm. Further, the metal thin film 402 that forms the intermediate electrode layer 102 is not limited to Ru, and may be composed of other metal materials or conductive materials such as gold, platinum, and titanium nitride.

  By the way, in the formation of the Ru film by the above-described ECR sputtering method, the substrate is not heated. However, the present invention is not limited to this, and a metal thin film such as a Ru film may be formed while the substrate is overheated. For example, when the Ru film is formed without heating, the adhesion of the Ru film to the silicon oxide may be reduced and the Ru film may be peeled off. The problem can be suppressed.

As described above, after the metal thin film 402 was formed in a desired thickness, the metal oxide layer 103 was formed on and in contact with the metal thin film 402 as shown in FIG. State. In the formation of the metal oxide layer 103, the ECR sputtering apparatus similar to the above is used, the semiconductor substrate 101 is fixed to the substrate holder 304 in the processing chamber 301, and the sintered body having a Bi: Ti ratio of 4: 3 is used as the target 305. The metal oxide layer 103 is formed so as to cover the surface of the metal thin film 402 by ECR sputtering using (Bi—Ti—O) and using Ar and oxygen (O ₂ ) as plasma gases.

The formation of the metal oxide layer 103 will be described in detail. In the ECR sputtering apparatus described above, first, the inside of the plasma generation chamber 302 is evacuated to a high vacuum state of 10 ⁻⁴ to 10 ⁻⁵ Pa, and then the semiconductor substrate 101. Is heated to 30 ° C. to 700 ° C., and, for example, Ar gas is introduced at a flow rate of 20 sccm from the inert gas introduction unit 311 into the plasma generation chamber 302, and the pressure in the plasma generation chamber 302 is set to 10 ^−, for example. Set to ² to 10 ^-3 Pa. In addition, a magnetic field under electron cyclotron resonance conditions is provided in the plasma generation chamber 302 by supplying a coil current to the magnetic coil 310 at 27 A, for example.

  In addition, a 2.45 GHz microwave (for example, 500 W) is supplied from a microwave generation unit (not shown), and this is supplied to the plasma generation chamber via the waveguide 308, the quartz window 307, and the vacuum waveguide 306. It introduce | transduces in 302, It is set as the state by which the plasma (ECR plasma) was produced | generated in the plasma production chamber 302 by introduction of this microwave.

  The generated plasma is emitted from the plasma generation chamber 302 to the processing chamber 301 side by the divergent magnetic field of the magnetic coil 310. Further, high frequency power (for example, 500 W) is supplied from a high frequency power source 322 to the target 305 disposed at the outlet of the plasma generation chamber 302. As a result, Ar particles collide with the target 305 to cause a sputtering phenomenon, and Bi particles and Ti particles jump out of the target 305.

  Bi particles and Ti particles jumping out from the target 305 reach the surface of the metal thin film 402 together with the plasma released from the plasma generation chamber 302 and the oxygen gas introduced from the reactive gas introduction unit 312 and activated by the plasma. And oxidized by the activated oxygen. The oxygen gas may be introduced at about 1 sccm from the reactive gas introduction unit 312, for example. The target 305 is a sintered body and contains oxygen. However, supply of oxygen can prevent oxygen deficiency in the deposited film.

  By forming the film by the ECR sputtering method described above, for example, a state in which the metal oxide layer 103 with a film thickness of about 30 nm is formed on the metal thin film 402 is obtained (FIG. 4B). Thereafter, the film formation is stopped by preventing the sputtered raw material from reaching the semiconductor substrate 101 with the aforementioned shutter closed. Thereafter, the plasma irradiation is stopped by stopping the supply of microwave power, the supply of each gas is stopped, the temperature of the semiconductor substrate 101 is lowered to a predetermined value, and the metal oxide is supplied from the inside of the processing chamber 301. The semiconductor substrate 101 on which the layer 103 is formed is unloaded. As will be described later, the temperature condition of the semiconductor substrate 101 may be 30 ° C. to 180 ° C.

  Next, as shown in FIG. 4C, the upper electrode 104 made of Ru having a predetermined area is formed on the metal oxide layer 103. For example, the upper electrode 104 having a predetermined area can be formed by processing the Ru film by patterning using a well-known photolithography technique and etching technique. Note that the upper electrode 104 is not limited to Ru, and may be made of another metal material such as gold, platinum, titanium nitride, or a conductive material.

  Thereafter, a part of the metal oxide layer 103 and the metal thin film 402 is removed to expose a part of the semiconductor substrate 101, and an intermediate electrode layer 102 is formed thereon as shown in FIG. The metal oxide layer 103 is disposed, and an ohmic contact 105 for connecting a wiring or the like is formed on the semiconductor substrate 101 serving as one electrode. As described above, the metal oxide element 100 using the metal oxide layer 103 is obtained.

  Next, an example of a method for manufacturing the metal oxide element 200 having the configuration shown in FIG. 2 in this embodiment will be described with reference to FIGS. First, as shown in FIG. 5A, a semiconductor substrate 101 made of p-type silicon having a main surface of plane orientation (100) and a resistivity of 1 to 2 Ω-cm is prepared, and the surface of the semiconductor substrate 101 is made of sulfuric acid. And a mixture of pure water and hydrogen peroxide, and a mixture of pure water and dilute hydrogen fluoride water, followed by drying.

  Next, as shown in FIG. 5B, the intermediate electrode layer 102 is formed on the main surface of the cleaned and dried semiconductor substrate 101. The intermediate electrode layer 102 is the same as the formation of the metal thin film 402 described above. Next, similarly to the formation of the metal oxide layer 103 on the metal thin film 402 described above, the metal oxide layer 103 was formed on the intermediate electrode layer 102 as shown in FIG. State. The metal oxide layer 103 is formed in contact with the intermediate electrode layer 102.

  Next, as shown in FIG. 5D, the upper electrode 104 made of Ru having a predetermined area is formed on the metal oxide layer 103. The formation of the upper electrode 104 here is the same as that of the upper electrode 104 in the metal oxide element 100 described above.

  Next, after removing the natural oxide film and the like on the back surface of the semiconductor substrate 101, the ohmic contact 205 is formed on the back surface of the semiconductor substrate 101 as shown in FIG. The lower electrode 206 to be connected to is formed. As described above, the metal oxide element 200 using the metal oxide layer 103 is obtained.

  Next, the metal oxide layer 103 formed by ECR sputtering as described above will be described in more detail. The inventors have found that the film characteristics of the metal oxide layer formed by temperature can be controlled by carefully observing the formation of the metal oxide layer composed of Bi, Ti, and oxygen using the ECR sputtering method. . In this sputtering film formation, an oxide sintered body target formed so that Bi and Ti have a composition of 4: 3 is used.

  The characteristics shown in FIG. 6 show changes in the deposition rate and refractive index with respect to the substrate temperature in the sputter deposition. FIG. 6 shows a case where the film is formed under the same gas conditions as those for forming the metal oxide layer 103 by the ECR sputtering method described above. As shown in FIG. 6, it can be seen that the deposition rate and the refractive index change with temperature.

First, paying attention to the refractive index, the refractive index is as small as about 2 in the low temperature region up to about 250 ° C., and shows amorphous characteristics. In the intermediate region at 300 ° C. to 600 ° C., the refractive index is about 2.6, which is close to the bulk reported in the paper, and it can be seen that the crystallization of Bi ₄ Ti ₃ O ₁₂ is progressing. Regarding these figures, for example, Yamaguchi et al., Japanese Journal Applied Physics, No. 37, 5166-5170, 1998, (M. Yamaguchi, et al. “Effect of Grain Size on Bi ₄ Ti ₃ O ₁₂ Thin Film Properties ", Jpn. J. Appl. Phys., 37, pp. 5166-5170, (1998)).

However, in a temperature region exceeding about 600 ° C., the refractive index increases, the surface morphology (surface irregularities) increases, and the crystallinity seems to change. This temperature is lower than the Bi ₄ Ti ₃ O ₁₂ Curie temperature of 675 ° C., but energy is supplied by irradiating the surface of the substrate on which the film is formed with ECR plasma, and the temperature of the substrate surface rises. If crystallinity such as oxygen deficiency is deteriorated, it is considered that there is no contradiction in the above results.

  Looking at the temperature dependence of the deposition rate, the deposition rate increases with temperature up to about 180 ° C. However, the film formation rate rapidly decreases in the region of about 180 ° C. to 300 ° C. When the temperature reaches about 300 ° C., the deposition rate becomes constant up to 600 ° C. The film formation rate in each oxygen region at this time was about 3 nm / min in the oxygen region C.

  Next, the crystallinity of the film formed in each temperature region was analyzed by X-ray diffraction. In a low temperature range from room temperature of about 30 ° C. to 180 ° C., it was confirmed to be amorphous. Further, it was confirmed that the crystal was composed of microcrystals in a temperature range of 180 ° C. to 300 ° C. It was also found that the film was oriented in the (117) direction in the temperature range of 300 ° C. or higher.

  When the cross-sectional shape of the state of the metal oxide layer in the temperature region of 300 ° C. or higher was observed with a transmission electron microscope, the results shown in the configuration diagram of FIG. 7 and the micrograph of FIG. 8 were obtained. In forming the film, a metal oxide composed of Bi, Ti, and oxygen was directly deposited on the silicon substrate 701 at a deposition temperature of 420 ° C.

From the results shown in FIGS. 7 and 8, the metal oxide layer 704 is formed, in the base layer containing excess Ti as compared to the stoichiometric composition of _{Bi 4 Ti 3 O 12, Bi} 4 Ti It was found to be composed of a plurality of fine crystal grains having a stoichiometric composition of ₃ O ₁₂ of about ₃ nm to 15 nm. Electron diffraction on the fine crystal grains confirmed that the fine crystal grains had a (117) plane of Bi ₄ Ti ₃ O ₁₂ . Note that the metal oxide layer 704 corresponds to the metal oxide layer 100 of the metal oxide element 100 and the metal oxide element 200 in this embodiment. In other words, the metal oxide layer 103 also, in the base layer containing excess Ti as compared to the stoichiometric composition of Bi ₄ Ti ₃ O _12, of Bi ₄ Ti ₃ O ₁₂ stoichiometry It consists of a plurality of fine crystal grains of about 3 nm to 15 nm.

  However, by observing the photograph of FIG. 8 in detail, an interface oxide layer 702 formed by oxidizing the silicon substrate 701 and Bi and Ti are formed on the interface between the metal oxide layer 704 and the silicon substrate 701. It was found that there was an interface reaction layer 703 formed by the reaction. When interface layers such as the interface oxide layer 702 and the interface reaction layer 703 are formed, a film having a low dielectric constant is formed, which may cause a large amount of leakage current to deteriorate the device performance. There is.

  Therefore, the inventors examined the formation of a metal oxide layer in a sufficiently low temperature region such that the interface oxide layer and the interface reaction layer are not formed. Specifically, it is a low-temperature region of 30 ° C. to 180 ° C. shown in FIG. 6, that is, a region where the refractive index is about 2.0 to 2.1 and the film formation rate increases as the temperature rises. However, when the substrate temperature is 30 ° C., that is, when the substrate is not heated, the actual temperature of the substrate surface on which the film is formed may rise to about 100 ° C. because the ECR plasma with energy is irradiated. It has been confirmed. However, when the substrate temperature is set to 100 ° C. to 150 ° C., the substrate heating temperature and the plasma heating temperature are approximately the same, and the substrate heating is suppressed by the control of the temperature controller. It becomes about 180 ° C to 180 ° C.

  In this low temperature region, a metal oxide layer made of Bi, Ti, and oxygen was formed on the silicon substrate using ECR sputtering. A cross-sectional observation of the transmission electron microscope at this time is shown in the photomicrograph of FIG. Specifically, the substrate was not heated, and the film was formed using the gas conditions of the metal oxide layer using the ECR sputtering method described above. As shown in FIG. 9, it can be seen that fine particles of 3 nm to 5 nm are present in the formed metal oxide layer despite being deposited without heating the substrate.

As a result of analyzing the composition of the fine particles and the peripheral portion by a technique in which characteristic X-rays generated from the irradiated portion by direct irradiation with an electron beam are directly detected by a semiconductor detector and converted into an electrical signal, the base layer ( Where the particles are not fine particles), Ti is contained more excessively than the stoichiometric composition of Bi ₄ Ti ₃ O ₁₂ , and the fine particles contain more Bi than the base layer, and Bi ₄ Ti ₃ it was found close to the stoichiometric composition of O _12. The measured fine particles are very small, 3nm to 5nm, so it is difficult to identify the exact composition by electron diffraction, but the same structure as the base layer and microcrystals observed in the high temperature region above 300 ° C is confirmed. did it.

  As described above with reference to FIG. 6, the XRD result confirms that the film formed at a low temperature is in an amorphous (non-crystalline) state. It is considered that the fine particles have not been confirmed in such a low temperature film formation, and it was observed because the film was formed by the ECR sputtering method having an appropriate energy of about 10 to 30 eV. When a metal oxide layer composed of Bi, Ti, and oxygen is formed on a silicon substrate in a low temperature region of 30 ° C. to 180 ° C., the interface oxide layer 702 and the interface reaction as seen in FIGS. Layer 703 is not observed. When the film was formed at such a low temperature, the interface between the silicon 1001 and the formed metal oxide layer 1004 was in a good state as shown in the schematic cross-sectional view of FIG.

Furthermore, the inventors discovered that a new phenomenon appears by examining the electrical characteristics of a device using a metal oxide layer composed of Bi, Ti and oxygen formed in a low temperature region as described above. did. In other words, the chemistry of Bi ₄ Ti ₃ O ₁₂ is formed in the base layer formed by the low-temperature sputtering method as described above and containing excess Ti compared to the stoichiometric composition of Bi ₄ Ti ₃ O ₁₂ . According to an element (metal oxide element 100) using a metal oxide layer composed of a plurality of fine crystal grains having a stoichiometric composition of about 3 nm to 15 nm, two states are maintained as will be described later. It was found that a functional element can be realized.

  Hereinafter, the characteristics of the metal oxide element 100 in the present embodiment will be described. This characteristic has been investigated by applying an appropriate voltage between the semiconductor substrate 101 (ohmic contact 105) and the upper electrode 104. When a voltage was applied between the ohmic contact 105 and the upper electrode 104 by a power source and the current when the voltage was applied was observed with an ammeter, the result shown in FIG. 11 was obtained. In FIG. 11, the horizontal axis represents the voltage value applied to the upper electrode 104, and the vertical axis represents the absolute value of the current value in logarithm.

  Hereinafter, the characteristics of the metal oxide element 100 shown in FIG. 1 will be described with reference to FIG. 11, but the voltage values and current values described here are used as examples observed in actual elements. Therefore, this phenomenon is not limited to the following numerical values. Other numerical values may be observed depending on the material and thickness of the film actually used for the element and other conditions. In the following, positive voltage application and negative voltage application are described with reference to voltage application to the upper electrode 104. However, when voltage application to the semiconductor substrate 101 is used as a reference, the relationship between positive and negative is described. Is reversed.

First, in the initial state when the metal oxide element 100 is manufactured (initially), the resistance of the metal oxide layer 103 is high. As shown in [1] in FIG. 11, the measured voltage value is about 10 ⁻¹¹ A when a voltage of −0.1 V is applied to the upper electrode 104. However, when a negative voltage exceeding −1 V is applied to the upper electrode 104, a current suddenly flows as indicated by [2] in FIG. This is a phenomenon called “electrofoaming” and “foaming”. After this rapid current flow occurs, a reversible resistance change phenomenon appears.

When a negative voltage is applied to the upper electrode 104 after the above-described “electrofoaming” phenomenon has occurred, as shown by [3] in FIG. 11, 10 ⁻⁵ vs. −0.1 V at 0 to −2 V. It can be seen that a current of about A flows and is in a low resistance state (first state having a first resistance value). Further, even when a positive voltage is applied to the upper electrode 104, as shown in [4] in FIG.

However, as shown in [5] in FIG. 11, when a positive voltage exceeding 0.8 V (a voltage exceeding the second voltage value) is applied to the upper electrode 104, the positive current hardly suddenly flows and the high resistance state. (Second state). However, in a state where a voltage of 0 to 0.8 V is applied, the metal oxide layer 103 maintains a low resistance state as indicated by [4] in FIG. When a positive voltage exceeding 0.8 V is applied to achieve a high resistance state and then a positive voltage is applied to the upper electrode 104 again, as shown in [6] in FIG. 11, 1 × 10 ^{− It} can be seen that a current of about ⁶ A flows (measured) and is in a high resistance state.

Subsequently, when a negative voltage is applied to the upper electrode 104 as indicated by [7] in FIG. 11, a high resistance state is maintained up to about 0 to −0.8 V, but −0. When a negative voltage exceeding 9 V (a voltage exceeding the first voltage value) is applied, as shown in [8] in FIG. 11, a current flows suddenly and transitions to the low resistance state (first state). Thereafter, even when a negative voltage is applied to the upper electrode 104 as indicated by [3] in FIG. 11, a low resistance state of about 10 ⁻⁵ A is maintained at about −0.1V.

  Subsequently, when a positive voltage is applied to the upper electrode 104, as shown in [4] in FIG. 11, the applied voltage is in a low resistance state up to about + 0.8V, but the applied voltage exceeds + 0.8V. (Application of a voltage exceeding the second voltage value) makes a transition to the high resistance state (second state) as indicated by [5] in FIG. Thus, according to the metal oxide element 100 of the present embodiment, a phenomenon in which the high resistance state and the low resistance state are switched reversibly is stably observed.

  In addition, according to the metal oxide element 100 of the present embodiment shown in FIG. 1, the intermediate electrode layer 102 is provided, and the metal oxide layer 103 is formed thereon. In addition, the formation of a low dielectric constant film such as the above-described interface layer is substantially suppressed. For this reason, the above-described change in resistance value is expressed in a more stable state.

  It should be noted here that the current value in the low resistance state when a negative voltage is applied to the upper electrode 104 and the current value in the low resistance state when a positive voltage is applied are greatly different. . As shown in FIG. 11, the current value in the low resistance state ([4] low resistance mode) when a positive voltage is applied is the current value in the low resistance state ([3] low resistance mode) when a negative voltage is applied. You can see that it is bigger than In other words, the resistance value in the low resistance state when the negative voltage is applied is larger than the resistance value in the low resistance state when the positive voltage is applied. Thus, the metal oxide layer 103 has different resistance values in the low resistance state (first state) by application of voltages having different polarities.

  The phenomenon described above can be described with reference to the band diagrams shown in FIGS. 12 and 13 are band diagrams schematically showing band gaps in the respective layers of the metal oxide element 100 shown in FIG. 1, and FIG. 12 shows a case where the metal oxide layer 103 is in a low resistance state. FIG. 13 shows a case where the metal oxide layer 103 is in a high resistance state.

First, the case where the metal oxide layer 103 is in a low resistance state will be described. As shown in FIG. 12A, when a negative voltage is applied to the upper electrode 104, the Fermi level (E _F ) of the upper electrode 104 increases corresponding to the applied voltage, and a barrier is formed between the upper electrode 104 and the metal oxide layer 103. It is formed. For this reason, the current flowing from the upper electrode 104 to the semiconductor substrate 101 is limited, and the current hardly flows. This state in which current does not easily flow can be explained by either an electron current in which carriers are electrons or a hole current in which carriers are holes.

  On the other hand, when a positive voltage is applied to the upper electrode 104, the height of the barrier between the metal oxide layer 103 is lowered as shown in FIG. .

Next, the case where the metal oxide layer 103 is in a high resistance state will be described. As shown in FIG. 13A, when a negative voltage is applied to the upper electrode 104, the Fermi level (E _F ) of the upper electrode 104 increases with respect to the applied voltage, and a barrier is formed between the upper electrode 104 and the metal oxide layer 103. Is done. Further, since the resistance value of the metal oxide layer 103 is very high, the current flowing from the upper electrode 104 to the semiconductor substrate 101 is limited, and the current hardly flows. This state in which current does not easily flow can be explained by either an electron current in which carriers are electrons or a hole current in which carriers are holes.

  In this case, even when a positive voltage is applied to the upper electrode 104, the resistance value of the metal oxide layer 103 is very high as shown in FIG. Is limited, and the current hardly flows.

In the above-described example, the metal oxide layer 103 is composed of Bi, Ti, and oxygen mainly composed of Bi ₄ Ti ₃ O ₁₂ (bismuth titanate), but is not limited thereto. . For example, a material with a perovskite structure, a material with a pseudo-ilmenite structure, a material with a tungsten bronze structure, a material with a bismuth layer structure, or a metal oxide containing at least two metals with a pyrochlore structure It may be done.

Specifically, a metal oxide composed of lanthanum, titanium, and oxygen (La ₂ Ti ₂ O ₇ ), a metal oxide composed of barium, titanium, and oxygen (BaTiO ₃ ), a metal oxide composed of lead, titanium, and oxygen (PbTiO ₃ ). ₃ ), a metal oxide composed of lead, zirconia, titanium and oxygen (Pb (Zr _1-x Ti _x ) O ₃ ), a metal oxide composed of lead, lanthanum, zirconia, titanium and oxygen ((Pb _1-y La _y ) (Zr _1-x Ti _x ) O ₃ ) and the like.

  In the description of the manufacturing method using FIG. 4, after forming the metal oxide layer 103, the processing chamber for forming the metal oxide layer 103 and the layer to be the upper electrode 104 was once taken out to the atmosphere. You may connect with a vacuum conveyance chamber by continuous processing. As a result, the semiconductor substrate 101 to be processed can be transported in a vacuum, and is less susceptible to disturbances such as moisture, leading to improved film quality and interface characteristics.

  Further, as disclosed in Japanese Patent Application Laid-Open No. 2003-077911, after each layer is formed, the surface of the formed layer may be irradiated with ECR plasma to improve the characteristics. Further, after forming each layer, as shown in Japanese Patent Application Laid-Open No. 2004-273730, annealing may be performed in an appropriate gas atmosphere to improve the characteristics of the formed layer. The metal oxide layer 103 is preferably used as an optimal film thickness as appropriate. For example, considering the resistance value of the metal oxide layer 103, the film thickness may be about 10 nm to 100 nm. As a result of the experiments by the inventors, when the thickness of the metal oxide layer 103 is 10 to 100 nm, the function (memory operation) of maintaining two states in the metal oxide element 100 in the embodiment is confirmed. It was.

It is sectional drawing which shows typically the structural example of the metal oxide element 100 which concerns on embodiment of this invention. It is sectional drawing which shows typically the structural example of the metal oxide element 100 which concerns on embodiment of this invention. It is a block diagram which shows the structural example of an ECR sputtering apparatus. It is process drawing for demonstrating the example of the manufacturing method of the metal oxide element 100 in embodiment. It is process drawing for demonstrating the example of the manufacturing method of the metal oxide element 200 in embodiment. 3 shows changes in the deposition rate and refractive index of the metal oxide layer with respect to the substrate temperature in sputter deposition. It is a block diagram which shows typically the result of having observed the cross-sectional shape with the transmission electron microscope about the state of the metal oxide layer formed in the temperature range of 300 degreeC or more. It is a microscope picture which shows the result of having observed the cross-sectional shape with the transmission electron microscope about the state of the metal oxide layer formed in the temperature range of 300 degreeC or more. It is the microscope picture obtained by the cross-sectional observation by the transmission electron microscope of the metal oxide layer which consists of Bi, Ti, and oxygen formed on the silicon substrate using the ECR sputtering method in a low temperature region of 180 ° C. or lower. It is a block diagram for demonstrating the state of the microscope picture shown in FIG. It is a characteristic view which shows the result of having observed the electric current when a voltage is applied between the semiconductor substrate 101 of the metal oxide element 100 in embodiment, and the upper electrode 104 with the ammeter. It is the band figure which showed typically the band gap in each layer of the metal oxide element 100 in this Embodiment. It is the band figure which showed typically the band gap in each layer of the metal oxide element 100 in this Embodiment. It is a block diagram which shows the structural example of stack type FeRAM.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate, 102 ... Intermediate electrode layer, 103 ... Metal oxide layer, 104 ... Upper electrode, 105 ... Ohmic contact.

Claims (12)

A semiconductor substrate composed of a semiconductor;
An intermediate electrode layer formed on the semiconductor substrate;
A metal oxide layer that is formed on the intermediate electrode layer and changes its electrical resistance;
And at least an upper electrode formed on the metal oxide layer,
The metal oxide layer is composed of a first metal, a second metal, and oxygen. The metal oxide device according to claim 1, wherein
The metal oxide layer includes a base layer composed of at least the first metal and oxygen, and a plurality of layers composed of the first metal, the second metal, and oxygen and dispersed in the base layer. A metal oxide device comprising fine particles. The metal oxide device according to claim 2, wherein
The metal oxide element, wherein the fine particles are non-crystalline. The metal oxide element according to claim 2 or 3,
The base layer is composed of the first metal, the second metal, and oxygen, and the composition ratio of the second metal is smaller than the stoichiometric composition. The metal oxide element. The metal oxide element according to claim 2 or 3,
The base layer is composed of the first metal, the second metal, and oxygen and is amorphous. In the metal oxide element according to any one of claims 1 to 5,
The metal oxide layer is
When a voltage exceeding the first voltage value is applied, the first state having the first resistance value is obtained.
The metal oxide element, wherein a second state having a second resistance value higher than the first resistance value is obtained by applying a voltage exceeding a second voltage value having a polarity different from that of the first voltage. The metal oxide device according to claim 6, wherein
The metal oxide layer is
In the first state, the metal oxide element is provided with different resistance values by applying voltages of different polarities. In the metal oxide element according to any one of claims 1 to 7,
The metal oxide layer is formed at 30 ° C. or higher and lower than 180 ° C. by a sputtering method. In the metal oxide element according to any one of claims 1 to 8,
The first metal is titanium, the second metal is bismuth, and the base layer is in an amorphous state composed of a layer containing excess titanium compared to the stoichiometric composition. Metal oxide element. A first step of forming an intermediate electrode layer on the semiconductor substrate;
A plasma composed of an inert gas and an oxygen gas supplied at a predetermined composition ratio is generated, and a negative bias is applied to a target composed of at least a first metal and a second metal to generate particles generated from the plasma. A base layer composed of at least the first metal and oxygen, the first metal, and the first metal, by causing a sputtering phenomenon by colliding with the target and depositing a material constituting the target on the intermediate electrode layer A second step of forming a metal oxide layer comprising a second metal and a plurality of fine particles composed of oxygen on the intermediate electrode layer;
A third step of forming an upper electrode on the metal oxide layer,
The method of manufacturing a metal oxide device, wherein the plasma is an electron cyclotron resonance plasma generated by electron cyclotron resonance and given kinetic energy by a divergent magnetic field. In the manufacturing method of the metal oxide element according to claim 10,
In the second step, the temperature of the semiconductor substrate is set to 30 to 180 ° C. The method for manufacturing a metal oxide element. In the manufacturing method of the metal oxide element of Claim 10 or 11,
The method for manufacturing a metal oxide element, wherein the first metal is titanium and the second metal is bismuth.