JP2008181978A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

To provide a non-volatile semiconductor memory device in which memory elements are three-dimensionally arranged, which can reduce a chip area.
A nonvolatile semiconductor memory device according to the present invention includes a plurality of memory element groups each including a plurality of memory elements in which resistance change elements and diodes are connected in series, and one end of each of the plurality of memory elements in the memory element group. A plurality of connected source lines. Each of the plurality of source lines of the plurality of memory element groups is a plate-like conductor layer that extends two-dimensionally.
[Selection] Figure 1

Description

The present invention relates to a semiconductor memory device capable of electrically rewriting data and a manufacturing method thereof.

In order to increase the integration and capacity of a semiconductor memory device, it is necessary to reduce the design rule. In order to reduce the design rule, further fine processing such as a wiring pattern is required. In order to realize further fine processing of wiring patterns and the like, a very advanced processing technique is required, so that it is difficult to reduce the design rule.

Therefore, in recent years, many semiconductor memory devices in which memory elements are arranged three-dimensionally have been proposed in order to increase the degree of memory integration (Patent Documents 1 to 4 and Non-Patent Document 1).

Many of the conventional semiconductor memory devices in which memory cells are arranged three-dimensionally simply stack memory cells, and an increase in cost due to an increase in the number of stacked layers is inevitable.

Further, in a conventional stacked nonvolatile semiconductor memory device, a word line, a bit line, and a source line exist independently for each layer. Therefore, as the number of stacked layers increases, the number of driver transistors for driving word lines, bit lines, and source lines increases, and an increase in chip area is inevitable.

JP 2003-078044 US Pat. No. 5,599,724 US Pat. No. 5,707,885 Endoh et al., “Novel Ultrahigh-Density Flash Memory With aStacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEEE TRANSACTIONSON ELECTRON DEVICES, VOL. 50, NO4, pp945-951, April 2003

The present invention provides a nonvolatile semiconductor memory device having a novel structure in which nonvolatile memory elements are three-dimensionally stacked, and capable of reducing the chip area, and a method for manufacturing the same.

According to one embodiment of the invention,
A plurality of memory element groups each including a plurality of memory elements in which a resistance change element and a diode are connected in series;
A plurality of source lines respectively connected to one end of each of the plurality of memory elements of the memory element group;
Have
There is provided a nonvolatile semiconductor memory device, wherein each of the plurality of source lines of the plurality of memory element groups is a plate-like conductor layer extending two-dimensionally.

According to one embodiment of the invention,
A plurality of memory element groups each including a plurality of memory elements in which a resistance change element and a diode are connected in series;
A plurality of select transistors each having one of a source and a drain connected to one end of each of the plurality of memory elements of the memory element group;
A plurality of source lines respectively connected to the other ends of the plurality of memory elements of the memory element group;
A plurality of bit lines to which the other of the sources and drains of the plurality of selection transistors is connected;
A plurality of word lines to which gates of the plurality of selection transistors are respectively connected;
Have
Each of the plurality of source lines is a plate-shaped conductor layer that extends two-dimensionally, and a nonvolatile semiconductor memory device is provided.

According to the nonvolatile semiconductor memory device and the manufacturing method thereof according to the embodiment of the present invention, a nonvolatile semiconductor memory device with a reduced chip area can be realized.

Hereinafter, embodiments of the nonvolatile semiconductor memory device and the manufacturing method thereof according to the present invention will be described. However, the present invention is not limited to the following embodiments. Moreover, in each embodiment, the same code | symbol is attached | subjected about the same structure and it may not explain anew.

(Embodiment 1)
(Nonpolar Semiconductor Nonvolatile Semiconductor Memory Device 1)
(OxRRAM: Oxide Resistive RAM)
FIG. 1 shows a schematic configuration diagram of a nonvolatile semiconductor memory device 1 according to Embodiment 1 of the present invention. The nonvolatile semiconductor memory device 1 according to this embodiment includes a memory element region 3, a plurality of bit lines 5, a bit line driving circuit 7, a plurality of source lines 9, a plurality of word lines 11, and a word line driving circuit 13. Etc. The plating wiring portion 17 of the nonvolatile semiconductor memory device 1 according to the first embodiment of the present invention shows a portion that has been removed after the plating process of the nonvolatile semiconductor memory device 1. As shown in FIG. 1, in the nonvolatile semiconductor memory device 1 of the present invention according to this embodiment, the memory element 15 constituting the memory element region 3 is formed by stacking a plurality of semiconductor layers. As shown in FIG. 1, the source line 9 of each layer extends two-dimensionally in a certain region. The source line 9 of each layer has a plate-like planar structure made of the same layer. In the nonvolatile semiconductor memory device 1 according to this embodiment, the direction of the current flowing through the memory element 15 is constant. The nonvolatile semiconductor memory device 1 according to this embodiment may be referred to as “a unipolar nonvolatile semiconductor memory device”.

The nonvolatile semiconductor memory device 1 according to the present embodiment may be referred to as OxRRAM (Oxide Resistive RAM) since the memory element 15 includes a resistance change element having a metal oxide.

2A, 2B, and 2C are schematic configuration diagrams of a part of the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 2C is a top view of the memory element region 3. In FIG. 2C, for convenience of explanation, a part of the upper structure is shown peeled off. 2A is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line AA ′ shown in FIG. FIG. 2B is a cross-sectional view of the memory element region 3, and corresponds to a cross-section BB ′ shown in FIG. As shown in FIG. 2, the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment has a configuration in which memory element strings 28 having a plurality of memory elements 15 stacked in the vertical direction are arranged in a matrix. is doing. In the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment, when the minimum processing dimension is F, the length of the memory element 15 in the AA ′ direction is 3F, and BB ′. The length in the direction is 2F, and when one memory string has n memory elements 15 (when n memory elements are stacked), the area of the memory element 15 is 6F ² / n.

FIG. 3A is a cross-sectional view of a part of the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment, as in FIG. 3D is a partially enlarged view of the memory element 15, and FIG. 3E is an equivalent circuit diagram of the memory element 15. FIG. 3F is an equivalent circuit of a part of the nonvolatile semiconductor memory device 1 according to this embodiment. As shown in FIG. 3A, the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment has a vertical transistor 20. A plurality of (four in the present embodiment) memory elements 15 are stacked on the vertical transistor 20. In the present embodiment, a configuration including a plurality of (four in the present embodiment) memory elements 15 stacked on the vertical transistor 20 is referred to as a memory element string 28. The memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment has 10 × 20 = 200 memory element strings 28 as shown in FIG.

In the present embodiment, the memory string 28 includes memory elements 15a to 15d. The memory element 15a includes a metal layer 163a, an oxidation transition metal layer 160a, a metal silicide layer 158a, a shallow p-type polysilicon layer 156a, and an n-type polysilicon layer 144a. The memory element 15b includes a metal layer 163a, an oxidation transition metal layer 160b, a metal silicide layer 158b, a shallow p-type polysilicon layer 156b, and an n-type polysilicon layer 144b. The memory element 15c includes a metal layer 163a, an oxidation transition metal layer 160c, a metal silicide layer 158c, a shallow p-type polysilicon layer 156c, and an n-type polysilicon layer 144c. The memory element 15d includes a memory element 15d having a metal layer 163a, an oxidation transition metal layer 160d, a metal silicide layer 158d, a shallow p-type polysilicon layer 156d, and an n-type polysilicon layer 144d.

Each of the memory elements 15a to 15d constituting the memory string 28 shown in FIG. 3 has a common metal layer 163a, and one end of each of the memory elements 15a to 15d is electrically connected to the metal layer 163a. It is connected. The n-type polysilicon layers 144a, 144b, 144c, and 144d are formed in a plate shape and constitute the source line 9, respectively. In the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment, all memory strings 28 have n-type polysilicon layers 144a, 144b, 144c, and 144d in common. A plurality of memory elements connected by the same source line 9 is called a memory element group. Note that the source line 9 becomes a drain line depending on the direction of current flowing in the memory element. Therefore, the source line 9 may be simply referred to as wiring.

As shown in FIG. 3D, the memory element 15a of the nonvolatile semiconductor memory device 1 according to this embodiment includes a resistance change element 15a1 including a metal layer 163a, an oxidation transition metal layer 160a, and a metal silicide layer 158a, and a resistance. A diode 15a2 composed of a shallow p-type polysilicon layer 156a and an n-type polysilicon layer 144a is connected to one end of the change element 15a1. That is, in the memory element 15a of the nonvolatile semiconductor memory device 1 according to this embodiment, the resistance change element 15a1 and the diode 15a2 are connected in series. It may be considered that the memory element 15a is composed of the resistance change element 15a1, and the diode 15a2 is connected to one end of the memory element 15a composed of the resistance change element 15a1. The other memory elements 15b to 15d have the same configuration as that of the memory element 15a. Note that the memory element 15a of the nonvolatile semiconductor memory device 1 according to the present embodiment includes the diode 15a2 whose forward direction is from the resistance change element 15a1 toward the source line SL. The shallow p-type polysilicon layer 156a and n-type polysilicon layer 144a may be formed so that the directions are opposite.

In the nonvolatile semiconductor memory device 1 according to this embodiment, one end of the memory element 15 is connected to the source line 9 (SL) via the source line selection transistor 26. As described above, the source line 9 has a plate-like planar structure, each composed of the same layer. The other end of the memory element 15 is connected to the bit line 5 (BL) via the vertical transistor 20. A bit line selection transistor 24 is connected to one end of the bit line 5 (BL). A signal is applied to the bit line 5 (BL) by the bit line selection transistor 24. The word line 11 (WL) is connected to the gate of the vertical transistor 20. A signal is applied to the word line 11 (WL) by the word line selection transistor 22.

In the nonvolatile semiconductor memory device 1 according to the present embodiment, as shown in FIG. 3, one ends of a plurality of memory elements 15 stacked in the vertical direction are connected to each other, and the word line 11 is connected via the vertical transistor 20. (WL).

2 and 3, one memory element string 28 has been described. However, in the nonvolatile semiconductor memory device 1 according to this embodiment, all the memory strings 28 have the same configuration. Further, the number of the memory strings 28 and the number of the memory elements 15 constituting the memory strings 28 can be appropriately changed to any number according to the memory capacity.

The “read operation”, “write operation”, and “erase operation” in the nonvolatile semiconductor memory device 1 according to the present embodiment will be described with reference to FIGS. As shown in FIGS. 4 to 9, for explaining the “read operation”, “write operation”, and “erase operation” in the nonvolatile semiconductor memory device 1 of the present invention according to the present embodiment, for convenience of explanation, The memory element region 3 including 27 memory elements 15 selected by the bit lines BL1 to BL3, the three word lines WL1 to WL3, and the three source lines SL1 to SL3 will be described as an example. Here, 27 memory elements 15 are indicated by M (i, j, k). “I” corresponds to the word line Wi, “j” corresponds to the bit line Bi, and “k” corresponds to the source line Sk. Note that the memory element region 3 of the nonvolatile semiconductor memory device 1 of the present invention is not limited to that shown in FIGS. 4 to 6, each memory element 15 is connected to a resistance change element and one end of the resistance change element, and the direction of current flowing from the resistance change element to the source line is defined as a forward direction. Have a diode. In addition, as shown in FIGS. 7-9, you may reverse the connection of this diode. In the present embodiment, the memory element M may be referred to as a “bit”.

The parameters of the memory element in the nonvolatile semiconductor memory device 1 according to the present embodiment are assumed to be as follows, but are not limited thereto.
Write voltage V_set = 0.5V
Erase voltage V_reset = 1V
Diode breakdown voltage VBD = 2V

Here, FIG. 82 is an example of a graph showing the magnitude of a current that flows when a voltage is applied to a unipolar memory element. In FIG. 82, the applied voltage (bias voltage) is on the horizontal axis and the current is on the vertical axis. A dotted line is a graph at the time of data writing (at the time of Set), and a solid line is a graph at the time of erasing data (at the time of Reset). As shown in FIG. 82, the applied voltage-current characteristics in a unipolar memory element have a difference in current flowing between data writing and data erasing.

(Read Operation of Nonvolatile Semiconductor Memory Device According to this Embodiment (Unipolar Read Operation (Read Operation)))
Regarding the “read operation” of data (information) in the nonvolatile semiconductor memory device 1 of the present invention related to this embodiment, the read operation of data stored in the memory element M (2, 1, 2) is taken as an example in FIG. Will be described with reference to FIG. In the nonvolatile semiconductor memory device 1 of the present invention according to this embodiment, the word lines WL1 to WL3, the bit lines BL1 to BL3, and the transistors connected to the source lines SL1 to SL3 are turned on or off, respectively. Signals are applied to WL1 to WL3, bit lines BL1 to BL3, and source lines SL1 to SL3. The bias relationship of the voltages applied to the word lines, bit lines, source lines, etc. during the data read operation in the nonvolatile semiconductor memory device 1 of the present invention related to this embodiment described here is an example, and It is not limited.

First, Von (for example, Von = 3 V) is applied to the word line WL2 connected to the selected memory element M (2, 1, 2) for reading data, and Voff (for example, Voff is applied to the other word lines WL1 and WL3). = 0V). Further, VSLread (for example, VSLread = 0 V) is applied to the source line SL2 connected to the selected memory element M (2, 1, 2) from which data is read, and the other source lines SL1 and SL3 are brought into a floating state. Then, VBLread (for example, VBLread = 0.2 V) is applied to the bit line BL1 connected to the selected memory element M (2, 1, 2) for reading data, and the other bit lines BL2 and BL3 are floated. . Here, by detecting the current flowing through the bit line BL1, the information stored in the memory element M (2, 1, 2) can be read. That is, the current value flowing through the bit line BL1 varies depending on the resistance value of the selected memory element M (2, 1, 2), and the current value is detected, so that the memory element M (2, 1, 2) stores the current value. Can be read. Here, with respect to the non-selected memory element M, there is always a diode set to a reverse bias voltage between the bit line BL and the source line SL sandwiching the non-selected memory element M. Current does not flow.

Even when data stored in another memory element M (i, j, k) is read, the word line, bit line and source connected to the memory element M (i, j, k) to be read Data stored in the memory element M (i, j, k) can be read by applying a signal similar to the signal applied to the memory element M (2, 1, 2) described above to the line.

In the present embodiment, each memory element 15 includes a resistance change element and a diode connected to one end of the resistance change element and having a forward direction of a current flowing from the resistance change element to the source line. . The signals applied to the word lines WL1 to WL3, the bit lines BL1 to BL3, and the source lines SL1 to SL3 in the data read operation of the selected memory element M (2, 1, 2) in the example in which the connection of the diodes is reversed. Bias conditions are shown in FIG. In the example shown in FIG. 7, the data of the selected memory cell M can be read by inverting the polarities of the signals applied to the bit lines BL1 to BL3 and the source lines SL1 to SL3 in the example shown in FIG.

(Write Operation of Nonvolatile Semiconductor Memory Device According to This Embodiment (Unipolar Write Operation (Set Operation)))
A data “write operation” in the nonvolatile semiconductor memory device 1 according to the present embodiment will be described with reference to FIG. 5 by taking a data write operation to the memory element M (2, 1, 2) as an example. . The bias relationship of the voltages applied to the word lines, bit lines, source lines, etc. during the data write operation in the nonvolatile semiconductor memory device 1 of the present invention related to the present embodiment described here is an example, and It is not limited.

First, Von (for example, Von = 3 V) is applied to the word line WL2 connected to the selected memory element M (2, 1, 2) to which data is written, and Voff (for example, Voff is applied to the other word lines WL1 and WL3). = 0V). In addition, VSLset (for example, VSLset = 0 V) is applied to the source line SL2 connected to the selected memory element M (2, 1, 2) to which data is written, and the other source lines SL1 and SL3 are floated. Then, VBLset (for example, VBLset = 0.7 V) is applied to the bit line BL1 connected to the selected memory element M (2, 1, 2) to which data is written, and the other bit lines BL2 and BL3 are floated. . At this time, a current flows through the bit line BL1, and the resistance value of the resistance change element of the selected memory element M (2, 1, 2) changes according to the amount of current flowing through the resistance change element. In this way, data can be written to the selected memory element M (2, 1, 2) by changing the resistance value of the selected memory element M (2, 1, 2). Here, as for the non-selected memory element M, there is always a diode set to a reverse bias voltage between the bit line BL and the source line SL sandwiching the non-selected memory element M. Current does not flow.

Even when data is written to another memory element M (i, j, k), the word line, bit line, and source line connected to the memory element M (i, j, k) to which data is to be written By applying a signal similar to the signal applied to the memory element M (2, 1, 2) described above, data can be written to the memory element M (i, j, k).

In the present embodiment, each memory element 15 includes a resistance change element and a diode connected to one end of the resistance change element and having a forward direction of a current flowing from the resistance change element to the source line. . The signals applied to the word lines WL1 to WL3, the bit lines BL1 to BL3, and the source lines SL1 to SL3 in the data write operation of the selected memory element M (2, 1, 2) in the example in which the connection of the diodes is reversed. The bias condition is shown in FIG. In the example shown in FIG. 8, data can be written to the selected memory cell M by inverting the polarities of the signals applied to the bit lines BL1 to BL3 and the source lines SL1 to SL3 in the example shown in FIG.

(Erase Operation of Nonvolatile Semiconductor Memory Device According to This Embodiment (Unipolar Erase Operation (Reset Operation)))
The “erasing operation” of data in the nonvolatile semiconductor memory device 1 of the present invention according to this embodiment will be described with reference to FIG. 6 by taking the erasing operation of the memory element M (2, 1, 2) as an example.

First, Von (for example, Von = 3 V) is applied to the word line WL2 connected to the selected memory element M (2, 1, 2) for erasing data, and Voff (for example, for example) is applied to the other word lines WL1 and WL3. Voff = 0V) is applied. Further, VSLreset (for example, VSLreset = 0 V) is applied to the source line SL2 connected to the selected memory element M (2, 1, 2) from which data is erased, and the other source lines SL1 and SL3 are brought into a floating state. Then, VBLreset (for example, VBLreset = 1.5V) is applied to the bit line BL1 connected to the selected memory element M (2, 1, 2) for erasing data, and the other bit lines BL2 and BL3 are floated. To do.

By forming such a bias state, a current larger than the current flowing during the data write operation flows to the selected memory element M (2, 1, 2), and the resistance change element of the memory element M (2, 1, 2). The resistance value of the memory device M changes, and the data of the memory element M (2, 1, 2) is erased. The selected memory element M (2, 1, 2) for erasing data is in a forward bias state with respect to the diode of the memory element M (2, 1, 2). ) Current. On the other hand, with respect to the non-selected memory element M, there is always a diode set to a reverse bias voltage between the bit line BL and the source line SL sandwiching the non-selected memory element M. Does not flow.

Even when data of other memory elements M (i, j, k) is erased, word lines, bit lines and source lines connected to the memory elements M (i, j, k) for erasing data In addition, the data of the memory element M (i, j, k) can be erased by applying a signal similar to the signal applied to the memory element M (2, 1, 2) described above.

In the present embodiment, each memory element 15 includes a resistance change element and a diode connected to one end of the resistance change element and having a forward direction of a current flowing from the resistance change element to the source line. . The signals applied to the word lines WL1 to WL3, the bit lines BL1 to BL3, and the source lines SL1 to SL3 in the data erasing operation of the selected memory element M (2, 1, 2) in the example in which the connection of the diodes is reversed. The bias condition is shown in FIG. In the example shown in FIG. 9, data can be erased from the selected memory cell M by inverting the polarities of the signals applied to the bit lines BL1 to BL3 and the source lines SL1 to SL3 in the example shown in FIG.

Next, another example of the nonvolatile semiconductor memory device of the present invention according to this embodiment is shown in FIGS. 10 to 12 are examples in which selection transistors, word lines, and bit lines are provided both above and below the memory element portion. The transistors connected to the lower side word lines WL11 to WL13 and the upper side word lines WL21 to WL23, the lower side bit lines BL11 to BL13, the upper side bit lines BL21 to BL23, and the source lines SL1 to SL3 are turned on or off. Thus, signals are applied to the lower word lines WL11 to WL13 and the upper word lines WL21 to WL23, the lower bit lines BL11 to BL13, the upper bit lines BL21 to BL23, and the source lines SL1 to SL3. In the example shown in FIGS. 10 to 12, there are the following three methods for setting the bias voltage applied to each memory element M (i, j, k) at the time of reading, writing, and erasing data. .
(1) Lower word lines WL11 to WL13, lower bit lines BL11 to BL13 and source lines SL1 to SL3 are selected. (2) Upper word lines WL21 to WL23, upper bit lines BL21 to BL23 and source lines SL1 to SL1. Select SL3 (3) Select lower side word lines WL11 to WL13 and upper side word lines WL21 to WL23, lower side bit lines BL11 to BL13 and upper side bit lines BL21 to BL23, and source lines SL1 to SL3

The example shown in FIG. 10 shows a bias relationship when reading data from the memory element M (2, 1, 2). The example shown in FIG. 11 shows a bias relationship when data is written to the memory element M (2, 1, 2). The example shown in FIG. 12 shows a bias relationship when erasing data in the memory element M (2, 1, 2). The bias relationship of the voltages applied to the word lines, bit lines, source lines, etc. during the data read operation in the nonvolatile semiconductor memory device 1 of the present invention related to this embodiment described here is an example, and It is not limited. The “read operation”, “write operation”, and “erase operation” of the nonvolatile semiconductor memory device according to the present embodiment shown in FIGS. 10 to 12 are the same as those of the first embodiment described above, respectively. Since this is the same as the “read operation”, “write operation”, and “erase operation” of the nonvolatile semiconductor memory device 1, it will not be described again here.

10 to 12, each memory element 15 is connected to the resistance change element and one end of the resistance change element, and the direction of the current flowing from the resistance change element to the source line is defined as the forward direction. Have a diode. As described above, this diode connection may be reversed.

(Manufacturing Process of Nonvolatile Semiconductor Memory Device with Unipolar Operation According to Embodiment 1)
(OxRRAM: Oxide Resistive RAM)
A manufacturing process of the nonvolatile semiconductor memory device 1 according to the present embodiment will be described below with reference to FIGS. 13 to 37 show a part of the memory element region 3 of the nonvolatile semiconductor memory device 1 of the present invention according to this embodiment. FIG. 13C to FIG. 37C are top views of the memory element region 3. FIGS. 13A to 37A are cross-sectional views of the memory element region 3, and correspond to the cross section AA ′ shown in FIGS. 13C to 37C. FIGS. 13B to 37B are cross-sectional views of the memory element region 3 and correspond to the cross-section BB ′ shown in FIGS. 13C to 37C. Further, in FIGS. 13A to 37A and FIGS. 13C to 37C, the right portion indicated by a broken line indicates a wiring portion for plating processing to be described later. The manufacturing process of the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment described here is the same as that of the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment. It is only an example of a manufacturing process and is not limited to this.

As shown in FIG. 13, an insulating film 102 is formed on the silicon substrate 100. Instead of a silicon substrate, a glass substrate or a quartz substrate on which polysilicon or a metal film is formed may be used. In the present embodiment, a silicon oxide film (SiO ₂ ) formed by plasma CVD is used as the insulating film 102. Further, a silicon nitride film (SixNy) or the like may be used as the insulating film 102. Next, the metal layer 104 is formed (FIG. 13). In this embodiment, tungsten (W) is formed as the metal layer 104 by a sputtering method.

Next, a resist mask is formed (not shown), and dry etching is performed to pattern the metal layer 104 and the insulating film 102 to form a pattern composed of 102a and 104a, a pattern composed of 102b and 104b, and a pattern composed of 102c and 104c. And a pattern consisting of 102d and 104d is formed (FIG. 14). 104a, 104b, 104c and 104d become the bit lines BL.

Next, an interlayer insulating film 106 is formed and planarized to form interlayer insulating films 106a, 106b, 106c, and 106d (FIG. 15). In this embodiment, a silicon oxide film (SiO ₂ ) formed by a plasma CVD method is used for the interlayer insulating film 106. When a silicon oxide film (SiO ₂ ) is formed by a plasma CVD method, TEOS (tetraethoxysilane) may be used. For the planarization of the interlayer insulating film 106, for example, a CMP (Chemical Mechanical Polishing) method is used.

Next, a silicon nitride film 108 as an etching stopper film when holes are formed later, a silicon oxide film 110 as an insulating film, a conductive polysilicon film 112 doped with impurities, and a silicon oxide film 114 as an insulating film are formed in this order. (FIG. 16). In this embodiment, a p-type polysilicon film 112 is formed as the polysilicon film 112.

Next, a resist mask is formed (not shown), and the silicon oxide film 114, the polysilicon film 112, the silicon oxide film 110, and the silicon nitride film 108 are dry etched to form holes 116a to 116h (FIG. 17). ). In the present embodiment, the cylindrical holes 116a to 116h are formed. However, the present invention is not limited to this, and holes having various shapes such as a prismatic shape and an elliptical cylindrical shape may be formed.

Next, a silicon oxide film 118 is formed as the insulating film 118 (FIG. 18). A part of the silicon oxide film 118 becomes a gate insulating film of the vertical transistor 20.

Next, a part of the silicon oxide film 118 is etched by reactive ion etching (RIE) method until the surfaces of the metal layers 104a to 104d are exposed to form silicon oxide films 118a to 118h (FIG. 19).

Next, a conductive polysilicon film 120 to which impurities are added is formed and planarized to form polysilicon films 120a to 120h (FIG. 20). In the present embodiment, n-type polysilicon films are formed as the polysilicon films 120a to 120h. For planarization, a CMP method or an etch back method may be used. The polysilicon films 120 a to 120 h later become channel formation regions of the vertical transistor 20.

Next, a resist mask is formed (not shown), and parts of the insulating film 110, the polysilicon film 112, and the insulating film 114 are etched (122a and 122b), thereby patterning the polysilicon films 124a to 124c. (FIG. 21). The patterned polysilicon films 124a to 124c will later become word lines WL.

Next, an interlayer insulating film 126 is formed and planarized to form interlayer insulating films 126a and 126b (FIG. 22). In the present embodiment, a silicon oxide film (SiO ₂ ) formed by plasma CVD is used for the interlayer insulating film 126. When a silicon oxide film (SiO ₂ ) is formed by a plasma CVD method, TEOS may be used. For example, a CMP method is used to planarize the interlayer insulating film 126.

Next, a silicon nitride film 128 is formed as an etching stopper film when holes are formed later (FIG. 23). Then, a silicon oxide film and a conductive polysilicon film doped with n-type impurities are alternately formed as an insulating film, and a silicon oxide film 130, an n-type polysilicon film 132, a silicon oxide film 134, and an n-type polysilicon are formed. A film 136, a silicon oxide film 138, an n-type polysilicon film 140, a silicon oxide film 142, an n-type polysilicon film 144, and a silicon oxide film 146 are formed (FIG. 23). Note that an n-type amorphous silicon film may be formed instead of the n-type polysilicon film 132, the n-type polysilicon film 136, the n-type polysilicon film 140, and the n-type polysilicon film 144.

Next, a resist mask is formed (not shown), and the groove 148 is formed by etching up to the substrate 100 (FIG. 24).

Next, a conductive polysilicon film 150 to which an n-type impurity is added is formed (FIG. 25).

Next, a part of the n-type polysilicon film 150 is etched by a reactive ion etching method until the surface of the substrate 100 is exposed to form an n-type polysilicon film 150a (FIG. 26). The n-type polysilicon film 150a formed in the trench 148 serves as a plating wiring when forming the memory element.

Next, an interlayer insulating film 152 is formed and planarized (FIG. 27). In the present embodiment, a silicon oxide film (SiO ₂ ) formed by a plasma CVD method is used for the interlayer insulating film 152. When a silicon oxide film (SiO ₂ ) is formed by a plasma CVD method, TEOS may be used. For planarization of the interlayer insulating film 152, a CMP method or an etch back method may be used.

Next, a resist mask is formed (not shown), and portions of the silicon oxide films 130, 134, 138, 142, and 146 and the n-type polysilicon films 132, 136, 140, and 144 are etched to form holes 154a. ~ 154h are formed (FIG. 28). At this time, the silicon nitride film 128 functions as an etching stopper film. In the present embodiment, the cylindrical holes 154a to 154h are formed. However, the present invention is not limited to this, and various shapes such as a prismatic shape and an elliptical shape may be formed. Good.

Next, by performing isotropic dry etching, for example, the n-type polysilicons 132, 136, 140, and 144 on the side surfaces of the holes 154a to 154h are retracted to form the n-type polysilicons 132a, 136a, 140a, and 144a. (FIG. 29).

Next, the substrate 100 is processed at a high temperature in a gas atmosphere containing p-type impurities to cause the p-type impurities 132a, 136a, 140a, and 144a to form shallow p-type diffusion regions 156a to 156t (FIG. 30). These shallow p-type diffusion regions 156a to 156t and n-type polysilicons 132a, 136a, 140a, and 144a form PN junctions to form a diode.

Next, the surface of the shallow p-type diffusion regions 156a to 156t is silicided with platinum (Pt) to form platinum silicide (PtSi) 158a to 158t (FIG. 31).

Next, the substrate 100 is one electrode, platinum silicide (PtSi) 158a to 158t is the other electrode, and platinum (Pt) is formed on the surface of the platinum silicide (PtSi) 158a to 158t by electroplating (FIG. 32). ). When the electroplating method is used, a metal is deposited on a portion that becomes an electrode for exchanging electrons with the plating solution. Here, platinum silicide (PtSi) 158a to 158t serves as an electrode for exchanging electrons with the plating solution, and platinum (Pt) is formed on the surface of platinum silicide (PtSi) 158a to 158t. In order to use the substrate 100 as an electrode, a current may be supplied to the back side or the bevel portion of the substrate 100. At this time, as indicated by an arrow (current path) in FIG. 32, a current flows from the substrate 100 to the platinum silicide (PtSi) 158a to 158t through the n-type polysilicon layer 150a. In this embodiment, an electrode protection film made of platinum (Pt) is formed on the surface of platinum silicide (PtSi) 158a to 158t by electroplating, but platinum silicide (PtSi) 158a is formed by electroless plating. An electrode may be formed on the surface of ˜158 t. According to the electroless plating method, wiring such as the n-type polysilicon layer 150a for passing a current from the substrate 100 to the platinum silicide (PtSi) 158a to 158t becomes unnecessary.

Next, a transition metal layer is formed on the entire surface of the substrate 100, and the transition metal layer is oxidized to form an oxidized transition metal layer 160 (FIG. 33). In this embodiment, nickel oxide (NiO) is used as the oxide transition metal layer 160. The transition metal oxide layer _{160, NiO, MnO, Cr 2} O 3, Mn 2 O 3, Fe 2 O 3, Al 2 O 3, CuO 2, TiO 2, may be used ZrO 2, ZnO and the like.

Next, by reactive ion etching, a part of the oxide transition metal layer 160 and a part of the silicon nitride film 128 are removed by etching to form holes 162a to 162h (FIG. 34).

Next, a platinum layer 163 is formed as a metal layer (FIG. 35). Thereafter, a titanium nitride (TiN) layer 164 is formed so as to fill the holes 162a to 162h (FIG. 35). In addition to platinum, ReO ₃ , IrO ₂ , OsO ₂ , RhO ₂ , NMoO ₂ , RuO ₂ , TiN, or the like may be used as the metal layer. Further, W or the like may be used instead of the titanium nitride layer 164. Thereafter, the platinum layer 163 and the titanium nitride layer 164 are planarized by CMP, etch back, or the like, so that the surface of the silicon oxide film 146 is exposed.

When the memory element region 3 of the nonvolatile semiconductor memory device 1 of the present invention according to this embodiment is completed, if the polysilicon layer 150a remains, all the source lines become conductive. Therefore, a resist mask is formed (not shown), and a portion indicated by D in FIG. 36A is removed by etching (FIG. 36). Through this step, the wiring (polysilicon layer 150a) used to form the electrode protective film is removed by electroplating, and the source lines are electrically insulated from each other.

Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment is completed (FIG. 1).

In addition, after the step shown in FIG. 35, a resist mask may be formed (not shown), and a portion indicated by E in FIG. 37A may be removed by etching so that the source lines are electrically insulated from each other ( FIG. 37). In this case, the wiring (polysilicon layer 150a) for plating remains. Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment is completed (FIG. 38).

(Embodiment 2)
(Nonvolatile semiconductor memory device 1 with bipolar operation)
(OxRRAM: Oxide Resistive RAM)
In the nonvolatile semiconductor memory device 1 according to the second embodiment, the direction of the current flowing through the memory element 15 is bidirectional. Here, the nonvolatile semiconductor memory device 1 according to the present embodiment in which the direction of the current flowing through the memory element 15 is bidirectional may be referred to as a “bipolar operation nonvolatile semiconductor memory device”.

The nonvolatile semiconductor memory device 1 according to the second embodiment will be described taking an example of an OxRRAM (Oxide Resistive RAM) in which the memory element 15 includes a resistance change element having a metal oxide. Since the nonvolatile semiconductor memory device 1 according to the second embodiment and the nonvolatile semiconductor memory device 1 according to the first embodiment have the same structure, they will not be described again here. However, in the nonvolatile semiconductor memory device 1 according to the second embodiment, the direction of the current flowing through the memory element 15 is bidirectional, and the bias condition of the signal applied to the word line WL, the bit line BL, and the source line SL Is different.

The “erase operation” in the nonvolatile semiconductor memory device 1 according to the present embodiment will be described with reference to FIG. The “read operation” and “write operation” in the nonvolatile semiconductor memory device 1 of the present invention related to the present embodiment are the nonvolatile semiconductor memory device 1 of the present invention related to the first embodiment described above (the unipolar operation nonvolatile semiconductor device). This is the same as the “read operation” and “write operation” of the storage device, and will not be described again here.

As shown in FIG. 39, as in the first embodiment, the “read operation”, “write operation”, and “erase operation” in the nonvolatile semiconductor memory device 1 according to the second embodiment will be described for convenience of explanation. A memory element region 3 composed of 27 memory elements 15 selected by three bit lines BL1 to BL3, three word lines WL1 to WL3 and three source lines SL1 to SL3 will be described as an example. . Here, 27 memory elements 15 are indicated by M (i, j, k). In the second embodiment shown in FIG. 39, each memory element 15 is connected to a resistance change element and one end of the resistance change element, and a diode whose forward direction is the direction of current flowing from the resistance change element to the source line. have. The memory element, the resistance change element, and the diode 15 of the nonvolatile semiconductor memory device 1 according to the present embodiment are connected in series. As shown in FIG. 40, this diode connection may be reversed.

The parameters of the memory element in the nonvolatile semiconductor memory device 1 according to the present embodiment are assumed to be as follows, but are not limited thereto.
Write voltage V_set = 0.5V
Erase voltage V_reset = -0.5V
Diode breakdown voltage VBD = 1V

(Erase Operation of Bipolar Operation Nonvolatile Semiconductor Memory Device According to the Present Embodiment)
The “erasing operation” of data in the nonvolatile semiconductor memory device 1 of the present invention according to the present embodiment will be described taking the data erasing operation of the memory element M (2, 1, 2) as an example.

In the nonvolatile semiconductor memory device 1 according to the second embodiment of the present invention, the memory element M is a bipolar memory element M in which the direction of the current flowing through the resistance change element changes. In order to erase the data in the bipolar memory element M, it is necessary to pass a current in the reverse direction through a diode connected to the selected memory element M from which data is erased. That is, it is necessary to breakdown the diode connected to the selected memory element M. At this time, in order to prevent current from flowing from the non-selected memory element M other than the selected memory element M to the selected bit line BL, it is necessary to prevent current from flowing through the diode of the non-selected memory element M. That is, even if a reverse bias voltage is applied to the diode of the non-selected memory element M, it is necessary to set a bias condition that does not cause breakdown. In order to realize this bias condition, for example, voltages are applied to the word lines WL1 to WL3, the bit lines BL1 to BL3, and the source lines SL1 to SL3 as follows.

First, Von (for example, Von = 3 V) is applied to the word line WL2 connected to the selected memory element M (2, 1, 2) for erasing data, and Voff (for example, for example) is applied to the other word lines WL1 and WL3. Voff = 0V) is applied. Further, VSLreset1 (for example, VSLreset1 = 1.2 V) is applied to the source line SL2 connected to the selected memory element M (2, 1, 2), and VSLreset2 (for example, VSLreset2 = 0.6V.) Is applied. Then, VBLreset (for example, VBLreset = 0 V) is applied to the bit line BL1 connected to the selected memory element M (2, 1, 2), and the other bit lines BL2 and BL3 are made floating. At this time, it is assumed that the breakdown voltage of the selected memory element and the non-selected memory element M is VBD (for example, assuming that VBD = 1V).

By forming such a bias state, a current larger than the current flowing during the data write operation flows to the selected memory element M (2, 1, 2), and the resistance change element of the memory element M (2, 1, 2). The resistance value of the memory device M changes, and the data of the memory element M (2, 1, 2) is erased. In the selected memory element M (2, 1, 2) for erasing data, a reverse bias state is applied to the diode of the memory element M (2, 1, 2), but a voltage higher than the breakdown voltage is applied to the diode. Therefore, a current flows through the selected memory element M (2, 1, 2). On the other hand, the non-selected memory element M (i, j, k) is reverse-biased with respect to the diode of the non-selected memory element M (i, j, k). Current does not flow through the breakdown voltage, so that no current flows through the non-selected memory element M (i, j, k).

Even when data of other memory elements M (i, j, k) is erased, word lines, bit lines and source lines connected to the memory elements M (i, j, k) for erasing data In addition, the data of the memory element M (i, j, k) can be erased by applying a signal similar to the signal applied to the memory element M (2, 1, 2) described above.

In the present embodiment, each memory element 15 includes a resistance change element and a diode connected to one end of the resistance change element and having a forward direction of a current flowing from the resistance change element to the source line. . The signals applied to the word lines WL1 to WL3, the bit lines BL1 to BL3, and the source lines SL1 to SL3 in the data erasing operation of the selected memory element M (2, 1, 2) in the example in which the connection of the diodes is reversed. The bias conditions are shown in FIG. In the example shown in FIG. 40, data can be erased from the selected memory cell M by inverting the polarities of the signals applied to the bit lines BL1 to BL3 and the source lines SL1 to SL3 in the example shown in FIG.

In the bipolar operation nonvolatile semiconductor memory device according to this embodiment of the present invention as well, as shown in FIGS. 10 to 12, select transistors, word lines, and bit lines are provided above and below the memory element portion. You may do it.

(Embodiment 3)
(Manufacturing process of unipolar non-volatile semiconductor memory device)
(OxRRAM: Oxide Resistive RAM)
Another manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment will be described below with reference to FIGS. In the present embodiment, when the variable resistance element constituting the memory element 15 is formed, the surface of titanium nitride (TiN) silicide constituting the variable resistance element is oxidized. Further, in the present embodiment, since the plating process as described in the first embodiment is not required, it is not necessary to form a plated wiring.

41 to 48 show a part of the memory element region 3 of the nonvolatile semiconductor memory device 1 according to the present embodiment as in the first embodiment. FIG. 41C to FIG. 48C are top views of the memory element region 3. 41A to FIG. 48A are cross-sectional views of the memory element region 3, and correspond to the cross-section A-A ′ shown in FIG. 41C to FIG. FIGS. 41B to 48B are cross-sectional views of the memory element region 3 and correspond to the cross-section B-B ′ shown in FIGS. 41C to 48C. The manufacturing process of the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment described here is the same as that of the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment. It is only an example of a manufacturing process and is not limited to this.

Regarding the manufacturing process of the nonvolatile semiconductor memory device 1 of the present invention according to the present embodiment, the description of the same part as the manufacturing process of the nonvolatile semiconductor memory device 1 of the present invention according to the first embodiment is omitted here. To do.

Similar to the process shown in FIG. 28 of the first embodiment, a resist mask is formed (not shown), and one of the silicon oxide films 130, 134, 138, 142, and 146 and the n-type polysilicon films 132, 136, 140, and 144 is formed. The holes 154a to 154h are formed by etching the part. In the present embodiment, the cylindrical holes 154a to 154h are formed. However, the present invention is not limited to this, and holes having various shapes such as a prismatic shape and an elliptical cylindrical shape may be formed.

Next, as shown in FIG. 41, for example, by performing isotropic dry etching, the n-type polysilicons 132, 136, 140, and 144 on the side surfaces of the holes 154a to 154h are retracted, and the n-type polysilicons 132a, 136a are retreated. , 140a and 144a are formed (FIG. 41).

Next, the substrate 100 is processed at a high temperature in a gas atmosphere containing p-type impurities to diffuse the p-type impurities into the n-type polysilicons 132a, 136a, 140a, and 144a, thereby forming shallow p-type diffusion regions 156a to 156t. (FIG. 42). These shallow p-type diffusion regions 156a to 156t and n-type polysilicons 132a, 136a, 140a, and 144a form PN junctions to form diodes.

Next, titanium nitride (TiN) 158a to 158t is formed on the surfaces of the shallow p-type diffusion regions 156a to 156t (FIG. 43). Thereafter, by performing heat treatment, the titanium nitrides 158a to 158t are silicided to form titanium nitride silicides (TiNSi) 158a to 158t (FIG. 43).

Next, the entire substrate is heated in an oxygen atmosphere to oxidize the surfaces of the titanium nitride silicides 158a to 158t to form titanium oxide layers 159a to 159t (FIG. 44).

Next, a transition metal layer 160 is formed as a protective film of the memory element (FIG. 46). In this embodiment, platinum (Pt) is used as the protective film of the memory element. However, other than platinum, ReO ₃ , IrO ₂ , OsO ₂ , RhO ₂ , NMoO ₂ , RuO ₂ , TiN, and the like are used. Can be used.

Next, a part of the transition metal layer 160 and a part of the silicon nitride film 128 are removed by reactive ion etching to form holes 162a to 162h (FIG. 46).

Next, a titanium nitride (TiN) layer 164 is formed so as to fill the holes 162a to 162h (FIG. 47). Instead of the titanium nitride layer 164, W or the like may be used.

Next, the titanium nitride layer 164 is planarized using CMP or an etch back method (FIG. 48).

Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment is completed (FIG. 1).

According to the manufacturing process of the nonvolatile semiconductor memory device 1 of the present invention in the present embodiment, the plating process as used in the first embodiment is not necessary, and therefore the nonvolatile semiconductor memory device 1 of the present invention can be performed by a simpler manufacturing method. Can be manufactured.

(Embodiment 4)
(PRAM: Phase Change RAM)
In the fourth embodiment, as an example of the nonvolatile semiconductor memory device of the present invention that operates unipolarly, a phase change nonvolatile semiconductor memory device (PRAM: Phase Change RAM) using a phase change film such as GST (GeSbTe) is used. ).

FIG. 49 shows a schematic configuration diagram of the nonvolatile semiconductor memory device 200 according to Embodiment 4 of the present invention. The nonvolatile semiconductor memory device 200 according to the fourth embodiment includes a memory element region 3, a plurality of bit lines 5, a bit line driving circuit 7, a plurality of source lines 9, a plurality of word lines 11, and a word line driving circuit. 13 etc. The wiring part 17 for plating of the nonvolatile semiconductor memory device 200 according to the fourth embodiment of the present invention shows a portion removed after the plating process performed when manufacturing the nonvolatile semiconductor memory device 200 according to the present embodiment. Yes. As shown in FIG. 49, in the nonvolatile semiconductor memory device 200 of the present invention according to this embodiment, the memory element 15 constituting the memory element region 3 is formed by stacking a plurality of semiconductor layers.

The nonvolatile semiconductor memory device 200 of the present invention according to the present embodiment is the same as the nonvolatile semiconductor memory device 1 of the present invention according to the first embodiment described above, except for the configuration of the memory element region 3. Therefore, each component of the nonvolatile semiconductor memory device 200 according to the present embodiment may not be described again.

In the nonvolatile semiconductor memory device 200 according to this embodiment, each memory element 15 has a phase change film such as GST (GeSbTe). The phase change film is a film in which the crystal state is changed by the current flowing therethrough and the resistance value thereof is changed. In the nonvolatile semiconductor memory device 200 according to the present embodiment, a current is passed through each memory element 15 to change the crystal state of the phase change film and change the resistance value of the memory element 15. Information is stored by utilizing the change in the resistance value of the memory element 15.

50A, 50B, and 50C are schematic configuration diagrams of a part of the memory element region 3 of the nonvolatile semiconductor memory device 200 according to this embodiment. FIG. 50C is a top view of the memory element region 3. In FIG. 50C, like FIG. 2, for convenience of explanation, a part of the upper structure is shown separated. FIG. 50A is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line AA ′ shown in FIG. FIG. 50B is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line BB ′ shown in FIG. As shown in FIG. 50, the memory element region 3 of the nonvolatile semiconductor memory device 200 according to this embodiment has a configuration in which memory element strings 28 having a plurality of memory elements 15a to 15d stacked in the vertical direction are arranged in a matrix. have. In the memory element region 3 of the nonvolatile semiconductor memory device 200 according to the present embodiment, when the minimum processing dimension is F, the length of the memory element 15 in the AA ′ direction is 3F, and BB ′. Since the length in the direction is 2F, when one memory string has n memory elements 15 (when n memory elements are stacked), the area of the memory element 15 is 6F ² / n. .

FIG. 51A is a cross-sectional view of a part of the memory element region 3 of the nonvolatile semiconductor memory device 200 according to this embodiment, similarly to FIG. FIG. 51D is a partially enlarged view of the memory element 15, and FIG. 51E is an equivalent circuit diagram of the memory element 15. FIG. 51F is a partial equivalent circuit of the nonvolatile semiconductor memory device 200 according to this embodiment. As shown in FIG. 51A, the memory element region 3 of the nonvolatile semiconductor memory device 200 according to this embodiment includes a vertical transistor 20. A plurality (four in this embodiment) of memory elements 15 a to 15 d are stacked on the vertical transistor 20. Also in the present embodiment, a configuration including a plurality of (four in the present embodiment) memory elements 15 a to 15 d stacked on the vertical transistor 20 is referred to as a memory element string 28. The memory element region 3 of the nonvolatile semiconductor memory device 200 according to this embodiment has 10 × 20 = 200 memory element strings 28 as shown in FIG.

In the present embodiment, the memory string 28 includes memory elements 15a to 15d. The memory element 15a includes a metal layer 212a, a GST layer 210a, a metal silicide layer 158a, a shallow p-type polysilicon layer 156a, and an n-type polysilicon layer 144a. The memory element 15b includes a metal layer 212a, a GST layer 210a, a metal silicide layer 158b, a shallow p-type polysilicon layer 156b, and an n-type polysilicon layer 144b. The memory element 15c includes a metal layer 212a, a GST layer 210a, a metal silicide layer 158c, a shallow p-type polysilicon layer 156c, and an n-type polysilicon layer 144c. The memory element 15d includes a metal layer 212a, a GST layer 210a, a metal silicide layer 158d, a shallow p-type polysilicon layer 156d, and an n-type polysilicon layer 144d.

The memory elements 15a to 15d constituting the memory string 28 have a common metal layer 212a, and one end of each of the memory elements 15a to 15d is electrically connected to the metal layer 212a. The n-type polysilicon layers 144a, 144b, 144c, and 144d constitute the source line 9 and are each formed in a plate shape. In the memory element region 3 of the nonvolatile semiconductor memory device 200 according to this embodiment, all memory strings 28 have n-type polysilicon layers 144a, 144b, 144c, and 144d in common.

As shown in FIG. 51D, the memory element 15a of the nonvolatile semiconductor memory device 200 according to this embodiment includes a resistance change element 15a1 including a metal layer 212a, a GST layer a that is a phase change film, and a metal silicide layer 158a. In addition, a diode 15a2 composed of a shallow p-type polysilicon film 156a and an n-type polysilicon film 144a connected to one end of the variable resistance element 15a1 is provided. As in the other embodiments, in the memory element 15a of the nonvolatile semiconductor memory device 200 according to this embodiment, the resistance change element 15a1 and the diode 15a2 are connected in series. It may be considered that the memory element 15a is composed of the resistance change element 15a1, and the diode 15a2 is connected to one end of the memory element 15a composed of the resistance change element 15a1. The other memory elements 15b to 15d have the same configuration as the memory element 15a. Note that the memory element 15a of the nonvolatile semiconductor memory device 200 according to this embodiment includes the diode 15a2 whose forward direction is from the resistance change element 15a1 toward the source line SL. The shallow p-type polysilicon layer 156a and n-type polysilicon layer 144a may be formed so that the directions are opposite.

In the nonvolatile semiconductor memory device 200 according to this embodiment, one end of the memory element 15 is connected to the source line 9 (SL) via the source line selection transistor 26 as in the first embodiment. As described above, each source line 9 has a plate-like planar structure made of the same layer. The other end of the memory element 15 is connected to the bit line 5 (BL) via the vertical transistor 20. A bit line selection transistor 24 is connected to one end of the bit line 5 (BL). A signal is applied to the bit line 5 (BL) by the bit line selection transistor 24. The word line 11 (WL) is connected to the gate of the vertical transistor 20. A signal is applied to the word line 11 (WL) by the word line selection transistor 22.

In the nonvolatile semiconductor memory device 200 according to the present embodiment, as in the first embodiment, as shown in FIG. 51, one ends of the plurality of memory elements 15 stacked in the vertical direction are connected to each other, and the vertical transistor 20 Is connected to the word line 11 (WL).

50 and 51, one memory element string 28 has been described. However, in the nonvolatile semiconductor memory device 200 according to this embodiment, all the memory strings 28 have the same configuration. Further, the number of the memory strings 28 and the number of the memory elements 15 constituting the memory strings 28 can be appropriately changed to any number according to the memory capacity.

The nonvolatile semiconductor memory device 200 of the present invention according to the present embodiment is a unipolar operation nonvolatile semiconductor memory device. Since the data read operation, write operation, and erase operation in the nonvolatile semiconductor memory device 200 of the present invention according to this embodiment are the same as those described in the first embodiment, they will not be described again here. Hereinafter, in the nonvolatile semiconductor memory device 200 of the present invention according to the present embodiment, as in the first embodiment, examples of parameters of the memory element M and word lines when the memory element M (2, 1, 2) is selected Examples of voltages applied to WL1 to WL3, source lines SL1 to SL3, and bit lines BL1 to BL3 are shown.
(Memory element parameters)
Write voltage V_set = 0.5V
Erase voltage V_reset = 1V
Diode breakdown voltage VBD = 2V
(During read operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLread = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLread = 0 .2V
Bit line potentials other than bit lines connected to the selected memory element M (2, 1, 2): floating (during write operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLset = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLset = 0 .7V
Bit line potentials other than bit lines connected to the selected memory element M (2, 1, 2): floating (during erase operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLset = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLset = 1 .5V
Bit line potential other than bit line connected to selected memory element M (2, 1, 2): floating

Hereinafter, a manufacturing process of the nonvolatile semiconductor memory device 200 according to the present embodiment will be described. In the manufacturing process of the nonvolatile semiconductor memory device 200 of the present invention according to this embodiment, the same parts as those of the manufacturing process of the nonvolatile semiconductor memory device 1 of the present invention according to Embodiment 1 will be described again here. Omitted.

Similar to the process shown in FIG. 25 of the first embodiment, a resist mask is formed (not shown), and one of the silicon oxide films 130, 134, 138, 142, and 146 and the n-type polysilicon films 132, 136, 140, and 144 is formed. The holes 154a to 154h are formed by etching the part. Also in the present embodiment, the cylindrical holes 154a to 154h are formed. However, the present invention is not limited to this, and holes having various shapes such as a prismatic shape and an elliptical column shape may be formed.

Next, similarly to the process shown in FIG. 26 of the first embodiment, by performing wet etching using hydrofluoric acid or the like, the n-type polysilicons 132, 136, 140, and 144 on the side surfaces of the holes 154a to 154h are retracted, N-type polysilicon 132a, 136a, 140a, and 144a are formed.

Next, similarly to the process shown in FIG. 27 of the first embodiment, the substrate 100 is then subjected to high-temperature treatment in a gas atmosphere containing p-type impurities, thereby removing the p-type impurities into n-type polysilicon 132a, 136a, 140a, and 144a. Then, shallow p-type diffusion regions 156a to 156t are formed. These shallow p-type diffusion regions 156a to 156t and n-type polysilicons 132a, 136a, 140a, and 144a form PN junctions to form diodes.

Next, the surface of the shallow p-type diffusion regions 156a to 156t is silicided with platinum (Pt) to form platinum silicide (PtSi) 158a to 158t (FIG. 52).

Next, similarly to the electroplating method described in FIG. 32 of the first embodiment, the substrate 100 is used as one electrode, platinum silicide (PtSi) 158a to 158t is used as the other electrode, and platinum (Pt) is converted into platinum by the electroplating method. It is formed on the surface of silicide (PtSi) 158a to 158t (FIG. 52). Here, platinum silicide (PtSi) 158a to 158t serves as an electrode for exchanging electrons with the plating solution, and platinum (Pt) is formed on the surface of platinum silicide (PtSi) 158a to 158t. In this embodiment, electrodes made of platinum (Pt) are formed on the surfaces of platinum silicides (PtSi) 158a to 158t by electroplating, but platinum silicides (PtSi) 158a to 158t are formed by electroless plating. An electrode may be formed on the surface. As described in the first embodiment, the electroless plating method eliminates the need for wiring such as the n-type polysilicon layer 150a for flowing a current from the substrate 100 to the platinum silicide (PtSi) 158a to 158t.

Next, a phase change film 210 is formed on the entire surface of the substrate 100 (FIG. 53). In the present embodiment, a GST (GeSbTe) film is used as the phase change film 210. As the phase change film 210, GeTe, Ag—In—Sb—Te, Tb—Sb—Te—Ge, or the like can be used in addition to GST.

Next, part of phase change film 210 and part of silicon nitride film 128 are removed by reactive ion etching to form phase change films 210a to 210e (FIG. 54).

Next, a titanium nitride (TiN) layer is formed so as to fill the holes surrounded by the phase change films 210a to 210e, and planarized using CMP or an etch back method to form titanium nitride layers 212a to 212e. (FIG. 55).

Next, a resist mask is formed (not shown), and the portion indicated by G in FIG. 56A is removed by etching (FIG. 56). Through this step, the wiring (polysilicon layer 150a) used to form the electrode protection film is removed by electroplating, and the platinum silicides (PtSi) 158a to 158t are electrically insulated from each other. Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 200 according to this embodiment is completed (FIG. 49).

Further, after the step shown in FIG. 55, a resist mask may be formed (not shown), and a portion indicated by H in FIG. 57A may be removed by etching so that the source lines are electrically insulated from each other ( FIG. 57). Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 200 according to the present embodiment is completed.

(Embodiment 5)
(MRAM: Magnetic RAM)
In Embodiment 5, a non-volatile semiconductor memory device (MRAM: magnetic RAM) using a ferromagnetic layer such as CoFe will be described as an example of the non-volatile semiconductor memory device of the present invention having bipolar operation.

The nonvolatile semiconductor memory device 300 of the present invention according to the fifth embodiment is the same as the nonvolatile semiconductor memory device 200 of the present invention according to the first or fourth embodiment described above, except for the configuration of the memory element region 3. . Therefore, each component of the nonvolatile semiconductor memory device 300 according to the present embodiment may not be described again.

In the nonvolatile semiconductor memory device 300 according to the present embodiment, each memory element 15 has a pair of ferromagnetic layers (films) such as CoFe with an insulator interposed therebetween. In the nonvolatile semiconductor memory device 300 according to this embodiment, in each memory element 15, the magnetization direction of one layer of the pair of ferromagnetic layers is constant, and the magnetization direction of the other is changed from the ferromagnetic material. It can be changed by the emitted spin-biased electrons. As the magnetization direction of one ferromagnetic layer changes, the electrical resistance value of the ferromagnetic layer constituting each memory element 15 changes depending on the magnetization direction. Information is stored using the change in the electrical resistance value of the memory element 15.

58A, 58B, and 58C are schematic configuration diagrams of a part of the memory element region 3 of the nonvolatile semiconductor memory device 300 according to this embodiment. FIG. 58C is a top view of the memory element region 3. In FIG. 58C, as in FIG. 2, for convenience of explanation, a part of the upper structure is shown separated. 58A is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line AA ′ shown in FIG. 58C. FIG. 58B is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line BB ′ shown in FIG. As shown in FIG. 58, as in the first to fourth embodiments described above, the memory element region 3 of the nonvolatile semiconductor memory device 300 according to this embodiment includes a plurality of memory elements 15a to 15d stacked in the vertical direction. The element strings 28 are arranged in a matrix. In the memory element region 3 of the nonvolatile semiconductor memory device 300 according to this embodiment, when the minimum processing dimension is F, the length of the memory element 15 in the AA ′ direction is 3F, and BB ′. Since the length in the direction is 2F, when one memory string has n memory elements 15 (when n memory elements are stacked), the area of the memory element 15 is 6F ² / n. .

FIG. 59A is a partial cross-sectional view of the memory element region 3 of the nonvolatile semiconductor memory device 300 according to this embodiment. FIG. 59D is a partially enlarged view of the memory element 15, and FIG. 59E is an equivalent circuit diagram of the memory element 15. FIG. 59F is an equivalent circuit of a part of the nonvolatile semiconductor memory device 300 according to this embodiment. As shown in FIG. 59A, the memory element region 3 of the nonvolatile semiconductor memory device 300 according to this embodiment includes a vertical transistor 20. A plurality (four in this embodiment) of memory elements 15 a to 15 d are stacked on the vertical transistor 20. Also in this embodiment, a configuration including a plurality (four in this embodiment) of memory elements 15 a to 15 d stacked on the vertical transistor 20 is referred to as a memory element string 28. The memory element region 3 of the nonvolatile semiconductor memory device 300 according to the present embodiment has 10 × 20 = 200 memory element strings 28 as shown in FIG.

In the present embodiment, the memory string 28 includes memory elements 15a to 15d. The memory element 15a includes a ferromagnetic layer 186a, a metal oxide layer 184a, a ferromagnetic layer 182a, a metal silicide layer 158a, a shallow p-type polysilicon layer 156a, and an n-type polysilicon layer 144a. The memory element 15b includes a ferromagnetic layer 186a, a metal oxide layer 184b, a ferromagnetic layer 182b, a metal silicide layer 158b, a shallow p-type polysilicon layer 156b, and an n-type polysilicon layer 144b. The memory element 15c includes a ferromagnetic layer 186a, a metal oxide layer 184c, a ferromagnetic layer 182c, a metal silicide layer 158c, a shallow p-type polysilicon layer 156c, and an n-type polysilicon layer 144c. The memory element 15d includes a ferromagnetic layer 186a, a metal oxide layer 184d, a ferromagnetic layer 182d, a metal silicide layer 158d, a shallow p-type polysilicon layer 156d, and an n-type polysilicon layer 144d.

The memory elements 15a to 15d constituting the memory string 28 have a common ferromagnetic layer 186a. The memory elements 15a to 15d are electrically connected by a metal layer 190a. The n-type polysilicon layers 144a, 144b, 144c, and 144d constitute the source line 9 and are each formed in a plate shape. In the memory element region 3 of the nonvolatile semiconductor memory device 300 according to this embodiment, all the memory strings 28 have n-type polysilicon layers 144a, 144b, 144c, and 144d in common.

As shown in FIG. 59D, the memory element 15a of the nonvolatile semiconductor memory device 300 according to this embodiment includes a resistance change element 15a1 including a ferromagnetic layer 186a, a spin filter 184a, and a ferromagnetic layer 182a, and A diode 15a2 composed of a shallow p-type polysilicon film 156a and an n-type polysilicon film 144a is connected to one end of the resistance change element 15a1. As in the other embodiments, in the memory element 15 of the nonvolatile semiconductor memory device 300 according to this embodiment, the resistance change element 15a1 and the diode 15a2 are connected in series. It may be considered that the memory element 15a is composed of the resistance change element 15a1, and the diode 15a2 is connected to one end of the memory element 15a composed of the resistance change element 15a1. The other memory elements 15b to 15d have the same configuration as the memory element 15a. Note that the memory element 15a of the nonvolatile semiconductor memory device 300 according to the present embodiment includes the diode 15a2 whose forward direction is the direction from the resistance change element 15a1 toward the source line SL. The shallow p-type polysilicon layer 156a and n-type polysilicon layer 144a may be formed so that the directions are opposite.

In the nonvolatile semiconductor memory device 300 according to this embodiment, one end of the memory element 15 is connected to the source line 9 (SL) via the source line selection transistor 26 as in the first embodiment. As described above, each source line 9 has a planar structure composed of the same layer, and has a plate-like planar structure. The other end of the memory element 15 is connected to the bit line 5 (BL) via the vertical transistor 20. A bit line selection transistor 24 is connected to one end of the bit line 5 (BL). A signal is applied to the bit line 5 (BL) by the bit line selection transistor 24. The word line 11 (WL) is connected to the gate of the vertical transistor 20. A signal is applied to the word line 11 (WL) by the word line selection transistor 22.

In the nonvolatile semiconductor memory device 300 according to the present embodiment, as in the first embodiment, as shown in FIG. 59, one ends of the plurality of memory elements 15 stacked in the vertical direction are connected to each other, and the vertical transistor 20 Is connected to the word line 11 (WL).

58 and 59, one memory element string 28 has been described. However, in the nonvolatile semiconductor memory device 300 according to this embodiment, all the memory strings 28 have the same configuration. Further, the number of the memory strings 28 and the number of the memory elements 15 constituting the memory strings 28 can be appropriately changed to any number according to the memory capacity.

The nonvolatile semiconductor memory device 300 of the present invention according to this embodiment is a bipolar semiconductor nonvolatile semiconductor memory device. Since the data read operation, write operation, and erase operation in the nonvolatile semiconductor memory device 300 of the present invention according to this embodiment are the same as those described in the second embodiment, they will not be described again here. Hereinafter, in the nonvolatile semiconductor memory device 300 according to the present embodiment, as in the second embodiment, examples of parameters of the memory element M and word lines when the memory element M (2, 1, 2) is selected Examples of voltages applied to WL1 to WL3, source lines SL1 to SL3, and bit lines BL1 to BL3 are shown.
(Memory element parameters)
Write voltage V_set = 1V
Erase voltage V_reset = -1V
Diode breakdown voltage VBD = 2V
(During read operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLread = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLread = 0 .2V
Bit line potentials other than bit lines connected to the selected memory element M (2, 1, 2): floating (during write operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLset = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLset = 1 .2V
Bit line potentials other than bit lines connected to the selected memory element M (2, 1, 2): floating (during erase operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLset = 2.5V
Potentials of source lines other than the source line connected to the selected memory element M (2, 1, 2): 1.5V
The potential of the bit line connected to the selected memory element M (2, 1, 2): VBLset = 0V
Bit line potential other than bit line connected to selected memory element M (2, 1, 2): floating

Hereinafter, a manufacturing process of the nonvolatile semiconductor memory device 300 according to the present embodiment will be described. In the manufacturing process of the nonvolatile semiconductor memory device 300 of the present invention according to the present embodiment, the nonvolatile semiconductor memory device 1 of the present invention according to the first embodiment or the nonvolatile semiconductor memory device 200 of the present invention according to the fourth embodiment. The description of the same part as the manufacturing process is omitted here.

Similar to the process shown in FIG. 25 of the first embodiment, a resist mask is formed (not shown), and one of the silicon oxide films 130, 134, 138, 142, and 146 and the n-type polysilicon films 132, 136, 140, and 144 is formed. The holes 154a to 154h are formed by etching the part. Also in the present embodiment, the cylindrical holes 154a to 154h are formed. However, the present invention is not limited to this, and various shapes of holes such as prismatic and elliptical pillars may be formed.

Next, as in the step shown in FIG. 26 of the first embodiment, for example, isotropic dry etching is performed to recede the n-type polysilicons 132, 136, 140, and 144 on the side surfaces of the holes 154a to 154h. Type polysilicons 132a, 136a, 140a and 144a are formed (FIG. 60).

Next, the substrate 100 is subjected to high-temperature processing in a gas atmosphere containing p-type impurities to diffuse the p-type impurities into the n-type polysilicons 132a, 136a, 140a, and 144a, thereby forming shallow p-type diffusion regions 156a to 156t. (FIG. 61). These shallow p-type diffusion regions 156a to 156t and n-type polysilicons 132a, 136a, 140a, and 144a form PN junctions to form diodes.

Next, a part of the silicon nitride film 128 is removed by reactive ion etching to expose the polysilicon films 120a to 120e (FIG. 62).

Next, the surface of the shallow p-type diffusion regions 156a to 156t is silicided with platinum (Pt) to form platinum silicide (PtSi) 158a to 158t (FIG. 63).

Next, similarly to the electroplating method described with reference to FIG. 29 of the first embodiment, the substrate 100 is used as one electrode, platinum silicide (PtSi) 158a to 158t is used as the other electrode, and platinum (Pt) is converted into platinum by electroplating. It is formed on the surface of silicide (PtSi) 158a to 158t (FIG. 64). Here, electrons are exchanged between the platinum silicides (PtSi) 158a to 158t and the plating solution, and platinum (Pt) is formed on the surfaces of the platinum silicides (PtSi) 158a to 158t. In this embodiment, electrodes made of platinum (Pt) are formed on the surfaces of latina silicide (PtSi) 158a to 158t by electroplating, but platinum silicide (PtSi) 158a to 158t are formed by electroless plating. An electrode may be formed on the surface. As described in the first embodiment, the electroless plating method eliminates the need for wiring such as the n-type polysilicon layer 150a for flowing a current from the substrate 100 to the platinum silicide (PtSi) 158a to 158t.

Next, ferromagnetic layers 182a to 182t are formed on the surface of platinum formed on the surfaces of platinum silicide (PtSi) 158a to 158t by an electroless plating method. In this embodiment, cobalt iron (CoFe) is used as the ferromagnetic layers 182a to 182t, but the present invention is not limited to this, and CoFeB or the like may be used as the ferromagnetic layers 182a to 182t. In this embodiment, the CoFe layer, which is a ferromagnetic layer, is formed by electroless plating. However, the present invention is not limited to this.

Next, after a metal layer is formed on the surfaces of the ferromagnetic layers 182a to 182t by an electroless plating method, metal oxide layers 184a to 184t serving as spin filters are formed by heating in an oxygen atmosphere.

Next, a ferromagnetic layer 186 is formed on the entire surface of the substrate by a sputtering method. In this embodiment, cobalt iron (CoFe) is used as the ferromagnetic layer 186, but the present invention is not limited to this, and CoFeB or the like may be used as the ferromagnetic layer 186.

Next, a part of the ferromagnetic layer 186 is removed by reactive ion etching to expose the polysilicon films 120a to 120e, thereby forming the ferromagnetic layers 186a to 186e (FIG. 68).

Next, a titanium nitride (TiN) layer is formed so as to fill the holes 188a to 188e surrounded by the ferromagnetic layers 186a to 186e, and a CMP process is performed to form titanium nitride layers 190a to 190e (FIG. 69).

Next, a resist mask is formed (not shown), and a portion indicated by H in FIG. Through this step, the wiring (polysilicon layer 150a) used to form the electrodes is removed by electroplating, and the source lines are electrically insulated from each other. Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 300 according to the present embodiment is completed.

In addition, after the step shown in FIG. 69, a resist mask is formed (not shown), and an etching step similar to the step described in FIG. 57 of the fourth embodiment is performed to electrically isolate the source lines. May be. Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 300 according to the present embodiment is completed.

(Embodiment 6)
(RRAM: Resistive RAM)
In the sixth embodiment, as an example of the non-volatile semiconductor memory device of the present invention having bipolar operation, a non-volatile semiconductor memory device using a material having a field induced resistance change (CER) effect such as Pr _0.7 Ca _0.3 MnO ₃ is used. (RRAM: Resistive RAM) will be described.

The nonvolatile semiconductor memory device 400 of the present invention according to the sixth embodiment is the present invention according to the nonvolatile semiconductor memory device 1 or the fourth embodiment of the present invention according to the above-described first embodiment, except for the configuration of the memory element region 3. This is the same as the nonvolatile semiconductor memory device 200 of FIG. Therefore, each component of the nonvolatile semiconductor memory device 400 according to the present embodiment may not be described again.

In the nonvolatile semiconductor memory device 400 according to the present embodiment, each memory element 15 includes a material having a field induced resistance change (CER) effect such as Pr _0.7 Ca _0.3 MnO ₃ (hereinafter referred to as “CER material”). ing. The electric field induced resistance change (CER) effect is a phenomenon in which the electric resistance value is changed by applying an electric field, and the nonvolatile semiconductor memory device 400 according to the present embodiment has the memory element 15 of the memory element 15. Information is stored using changes in the electrical resistance value. Note that the electric resistance of the CER material constituting each memory element 15 does not change after the electric field is removed. Thus, each memory element continues to store that information even after the electric field is removed.

The nonvolatile semiconductor memory device 400 of the present invention according to this embodiment is a bipolar semiconductor memory device.

71A, 71B, and 71C are schematic configuration diagrams of a part of the memory element region 3 of the nonvolatile semiconductor memory device 400 according to this embodiment. FIG. 71C is a top view of the memory element region 3. In FIG. 71 (C), as in FIG. 2, for convenience of explanation, a part of the upper structure is shown separated. 71A is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line AA ′ shown in FIG. 71C. 71B is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line BB ′ shown in FIG. 71C. As shown in FIG. 71, as in the first to fifth embodiments described above, the memory element region 3 of the nonvolatile semiconductor memory device 400 according to this embodiment includes a plurality of memory elements 15a to 15d stacked in the vertical direction. The element strings 28 are arranged in a matrix. In the memory element region 3 of the nonvolatile semiconductor memory device 400 according to the present embodiment, when the minimum processing dimension is F, the length of the memory element 15 in the AA ′ direction is 3F, and BB ′. Since the length in the direction is 2F, when one memory string has n memory elements 15 (when n memory elements are stacked), the area of the memory element 15 is 6F ² / n. .

FIG. 72A is a cross-sectional view of a part of the memory element region 3 of the nonvolatile semiconductor memory device 400 according to this embodiment. FIG. 72D is a partially enlarged view of the memory element 15, and FIG. 72E is an equivalent circuit diagram of the memory element 15. FIG. 72F is an equivalent circuit of a part of the nonvolatile semiconductor memory device 400 according to this embodiment. As shown in FIG. 72A, the memory element region 3 of the nonvolatile semiconductor memory device 400 according to this embodiment includes a vertical transistor 20. A plurality (four in this embodiment) of memory elements 15 a to 15 d are stacked on the vertical transistor 20. Also in the present embodiment, a configuration including a plurality of (four in the present embodiment) memory elements 15 a to 15 d stacked on the vertical transistor 20 is referred to as a memory element string 28. The memory element region 3 of the nonvolatile semiconductor memory device 300 according to the present embodiment has 10 × 20 = 200 memory element strings 28.

In the present embodiment, the memory string 28 includes memory elements 15a to 15d. The memory element 15a includes a metal layer 171a, a CER layer 170a, a metal silicide layer 158a, a shallow p-type polysilicon layer 156a, and an n-type polysilicon layer 144a. The memory element 15b includes a metal layer 171a, a CER layer 170a, a metal silicide layer 158b, a metal silicide layer 158b, a shallow p-type polysilicon layer 156b, and an n-type polysilicon layer 144b. The memory element 15c includes a metal layer 171a, a CER layer 170a, a metal silicide layer 158c, a metal silicide layer 158c, a shallow p-type polysilicon layer 156c, and an n-type polysilicon layer 144c. The memory element 15d includes a metal layer 171a, a CER layer 170a, a metal silicide layer 158d, a shallow p-type polysilicon layer 156d, and an n-type polysilicon layer 144d.

The memory elements 15a to 15d constituting the memory string 28 have a common metal layer 171a and CER layer 170a. The memory elements 15a to 15d are electrically connected by a metal layer 171a. The n-type polysilicon layers 144a, 144b, 144c, and 144d constitute the source line 9 and are each formed in a plate shape. In the memory element region 3 of the nonvolatile semiconductor memory device 400 according to this embodiment, all the memory strings 28 have n-type polysilicon layers 144a, 144b, 144c, and 144d in common.

As shown in FIG. 72D, the memory element 15a of the nonvolatile semiconductor memory device 400 according to this embodiment includes a metal layer 171a, a CER layer 170a, a resistance change element 15a1 made of a metal silicide layer, and a resistance change element 15a1. And a diode 15a2 made of a shallow p-type polysilicon film 156a and an n-type polysilicon film 144a, which are connected to one end thereof. As in the other embodiments, in the memory element 15 of the nonvolatile semiconductor memory device 400 according to this embodiment, the resistance change element 15a1 and the diode 15a2 are connected in series. It may be considered that the memory element 15a is composed of the resistance change element 15a1, and the diode 15a2 is connected to one end of the memory element 15a composed of the resistance change element 15a1. The other memory elements 15b to 15d have the same configuration as the memory element 15a. Note that the memory element 15a of the nonvolatile semiconductor memory device 400 according to the present embodiment includes the diode 15a2 whose forward direction is from the resistance change element 15a1 toward the source line SL. The shallow p-type polysilicon layer 156a and n-type polysilicon layer 144a may be formed so that the directions are opposite.

In the nonvolatile semiconductor memory device 400 according to this embodiment, one end of the memory element 15 is connected to the source line 9 (SL) via the source line selection transistor 26 as in the first embodiment. As described above, each source line 9 has a plate-like planar structure made of the same layer. The other end of the memory element 15 is connected to the bit line 5 (BL) via the vertical transistor 20. A bit line selection transistor 24 is connected to one end of the bit line 5 (BL). A signal is applied to the bit line 5 (BL) by the bit line selection transistor 24. The word line 11 (WL) is connected to the gate of the vertical transistor 20. A signal is applied to the word line 11 (WL) by the word line selection transistor 22.

In the nonvolatile semiconductor memory device 400 according to the present embodiment, as in the first embodiment, as shown in FIG. 72, one ends of the plurality of memory elements 15 stacked in the vertical direction are connected to each other, and the vertical transistor 20 Is connected to the word line 11 (WL).

71 and 72, one memory element string 28 has been described. However, in the nonvolatile semiconductor memory device 400 according to this embodiment, all the memory strings 28 have the same configuration. Further, the number of the memory strings 28 and the number of the memory elements 15 constituting the memory strings 28 can be appropriately changed to any number according to the memory capacity.

The nonvolatile semiconductor memory device 400 of the present invention according to this embodiment is a bipolar semiconductor memory device. Since the data read operation, write operation, and erase operation in the nonvolatile semiconductor memory device 400 of the present invention according to this embodiment are the same as those described in Embodiment 2, they will not be described again here. Hereinafter, in the nonvolatile semiconductor memory device 400 of the present invention according to the present embodiment, as in the second embodiment, examples of parameters of the memory element M and word lines when the memory element M (2, 1, 2) is selected Examples of voltages applied to WL1 to WL3, source lines SL1 to SL3, and bit lines BL1 to BL3 are shown.
(Memory element parameters)
Write voltage V_set = 0.5V
Erase voltage V_reset = -0.5V
Diode breakdown voltage VBD = 1V
(During read operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLread = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLread = 0 .2V
Bit line potentials other than bit lines connected to the selected memory element M (2, 1, 2): floating (during write operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLset = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLset = 0 .7V
Bit line potentials other than bit lines connected to the selected memory element M (2, 1, 2): floating (during erase operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLset = 1.2V
Potentials of source lines other than the source line connected to the selected memory element M (2, 1, 2): 0.6V
The potential of the bit line connected to the selected memory element M (2, 1, 2): VBLset = 0V
Bit line potential other than bit line connected to selected memory element M (2, 1, 2): floating

Hereinafter, a manufacturing process of the nonvolatile semiconductor memory device 400 according to the embodiment will be described. In the manufacturing process of the nonvolatile semiconductor memory device 400 of the present invention according to the present embodiment, the nonvolatile semiconductor memory device 1 of the present invention according to the first embodiment or the nonvolatile semiconductor memory device 200 of the present invention according to the fourth embodiment. The description of the same part as the manufacturing process is omitted here.

After the process similar to the process shown in FIG. 32 of Embodiment 1, a CER layer 170 is formed on the entire surface of the substrate (FIG. 73).

Next, a part of the CER layer 170 and a part of the silicon nitride film 128 are removed by reactive ion etching. By this step, the polysilicon films 120a to 120e are exposed, and CER layers 170a to 170e are formed (FIG. 74).

Next, a platinum (Pt) layer 171 is formed as a metal layer on the entire surface of the substrate. Thereafter, a titanium nitride (TiN) layer 172 is formed so as to fill the holes 162a to 162h (FIG. 75). In addition to platinum, ReO ₃ , IrO ₂ , OsO ₂ , RhO ₂ , NMoO ₂ , RuO ₂ , TiN, or the like may be used as the metal layer. In place of the titanium nitride layer 172, W may be used. Next, the entire surface of the substrate is flattened by using CMP or an etch back method to form platinum layers 171a to 171h and titanium nitride layers 172a to 172h (FIG. 76).

Thereafter, a resist mask is formed (not shown), and a portion indicated by F in FIG. 76A is removed by etching (FIG. 76). Through this step, the wiring (polysilicon layer 150a) used to form the electrode protection film is removed by electroplating, and the platinum silicides (PtSi) 158a to 158t are electrically insulated from each other.

Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment is completed.

In addition, after the step shown in FIG. 75, a resist mask may be formed (not shown), and a portion indicated by G in FIG. 75A may be removed by etching so that the source lines are electrically insulated from each other ( FIG. 75). In this case, the wiring (polysilicon layer 150a) for plating remains. Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 1 according to this embodiment is completed.

(Embodiment 7)
(PMCRAM: Programmable Metallization RAM)
In the seventh embodiment, a nonvolatile semiconductor memory device (PMMCRAM: Programmable Metallization RAM) using an electrolyte material such as CuS, AgGeS, CuGeS, or AgGeSe is shown as an example of the nonvolatile semiconductor memory device of the present invention that performs bipolar operation. explain.

The nonvolatile semiconductor memory device 500 according to the seventh embodiment of the present invention is the nonvolatile semiconductor memory device 1 according to the first embodiment of the present invention or the fourth embodiment of the present invention except for the configuration of the memory element region 3. This is the same as the nonvolatile semiconductor memory device 200 of FIG. Therefore, each component of the nonvolatile semiconductor memory device 500 according to this embodiment may not be described again.

In the nonvolatile semiconductor memory device 500 according to this embodiment, each memory element 15 has an electrolyte material such as CuS, AgGeS, CuGeS, or AgGeSe. In the nonvolatile semiconductor memory device 500 according to this embodiment, by applying a voltage to each memory element 15, metal ions such as Ag ⁺ and Cu ⁺ move in the electrolyte material (colloid), and the metal is contained in the electrolyte material. The resistance value of the memory element 15 is changed by forming a typical “bridge”. Information is stored by utilizing the change in the resistance value of the memory element 15.

78A, 78B, and 78C are schematic configuration diagrams of a part of the memory element region 3 of the nonvolatile semiconductor memory device 500 according to this embodiment. FIG. 78C is a top view of the memory element region 3. In FIG. 78C, as described in Embodiment 1 above, for convenience of explanation, part of the upper structure is shown separated. FIG. 78A is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line AA ′ shown in FIG. 78C. FIG. 78B is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line BB ′ shown in FIG. As shown in FIG. 78, the memory element region 3 of the nonvolatile semiconductor memory device 500 according to this embodiment has a configuration in which memory element strings 28 having a plurality of memory elements 15a to 15d stacked in the vertical direction are arranged in a matrix. have. In the memory element region 3 of the nonvolatile semiconductor memory device 500 according to this embodiment, when the minimum processing dimension is F, the length in the AA ′ direction of the memory element 15 is 3F, and BB ′. Since the length in the direction is 2F, when one memory string has n memory elements 15 (when n memory elements are stacked), the area of the memory element 15 is 6F ² / n. .

FIG. 79A is a cross-sectional view of a part of the memory element region 3 of the nonvolatile semiconductor memory device 500 according to this embodiment, similarly to FIG. FIG. 79D is a partially enlarged view of the memory element 15, and FIG. 79E is an equivalent circuit diagram of the memory element 15. FIG. 79F is an equivalent circuit of a part of the nonvolatile semiconductor memory device 500 according to this embodiment. As shown in FIG. 79A, the memory element region 3 of the nonvolatile semiconductor memory device 500 according to this embodiment includes a vertical transistor 20. A plurality (four in this embodiment) of memory elements 15 a to 15 d are stacked on the vertical transistor 20. Also in the present embodiment, a configuration including a plurality of (four in the present embodiment) memory elements 15 a to 15 d stacked on the vertical transistor 20 is referred to as a memory element string 28. The memory element region 3 of the nonvolatile semiconductor memory device 500 according to this embodiment has 10 × 20 = 200 memory element strings 28 as shown in FIG.

In the present embodiment, the memory string 28 includes memory elements 15a to 15d. The memory element 15a includes an electrolyte material 202a, a metal silicide layer 158a, a shallow p-type polysilicon layer 156a, and an n-type polysilicon layer 144a. The memory element 15b includes an electrolyte material 202a, a metal silicide layer 158b, a shallow p-type polysilicon layer 156b, and an n-type polysilicon layer 144b. The memory element 15c includes an electrolyte material 202a, an electrolyte material 202a, a metal silicide layer 158c, a shallow p-type polysilicon layer 156c, and an n-type polysilicon layer 144c. The memory element 15d includes an electrolyte material 202a, a metal silicide layer 158d, a shallow p-type polysilicon layer 156d, and an n-type polysilicon layer 144d.

The memory elements 15a to 15d constituting the memory string 28 have a common electrolyte material 202a. The n-type polysilicon layers 144a, 144b, 144c, and 144d constitute the source line 9 and are each formed in a plate shape. In the memory element region 3 of the nonvolatile semiconductor memory device 500 according to this embodiment, all the memory strings 28 have n-type polysilicon layers 144a, 144b, 144c, and 144d in common.

As shown in FIG. 79D, the memory element 15a of the nonvolatile semiconductor memory device 500 according to this embodiment includes a resistance change element 15a1 made of an electrolyte material 202a and a metal silicide layer 158a, and one end of the resistance change element 15a1. A diode 15a2 made of a shallow p-type polysilicon film 156a and an n-type polysilicon film 144a is connected. As in the other embodiments, in the memory element 15 of the nonvolatile semiconductor memory device 500 according to this embodiment, the resistance change element 15a1 and the diode 15a2 are connected in series. As in the other embodiments, it may be considered that the memory element 15a includes the resistance change element 15a1, and the diode 15a2 is connected to one end of the memory element 15a including the resistance change element 15a1. The other memory elements 15b to 15d have the same configuration as the memory element 15a. Note that the memory element 15a of the nonvolatile semiconductor memory device 500 according to the present embodiment includes the diode 15a2 whose forward direction is the direction from the resistance change element 15a1 toward the source line SL. Similarly, the shallow p-type polysilicon layer 156a and n-type polysilicon layer 144a may be formed so that the direction of the diode 15a2 is opposite.

In the nonvolatile semiconductor memory device 500 according to this embodiment, one end of the memory element 15 is connected to the source line 9 (SL) via the source line selection transistor 26 as in the first embodiment. As described above, each source line 9 has a plate-like planar structure made of the same layer. The other end of the memory element 15 is connected to the bit line 5 (BL) via the vertical transistor 20. A bit line selection transistor 24 is connected to one end of the bit line 5 (BL). A signal is applied to the bit line 5 (BL) by the bit line selection transistor 24. The word line 11 (WL) is connected to the gate of the vertical transistor 20. A signal is applied to the word line 11 (WL) by the word line selection transistor 22.

In the nonvolatile semiconductor memory device 500 according to the present embodiment, as in the first embodiment, as shown in FIG. 79, one ends of the plurality of memory elements 15 stacked in the vertical direction are connected to each other, and the vertical transistor 20 Is connected to the word line 11 (WL).

78 and 79, one memory element string 28 has been described. However, in the nonvolatile semiconductor memory device 500 according to this embodiment, all the memory strings 28 have the same configuration. Further, the number of the memory strings 28 and the number of the memory elements 15 constituting the memory strings 28 can be appropriately changed to any number according to the memory capacity.

The nonvolatile semiconductor memory device 500 of the present invention according to this embodiment is a bipolar semiconductor memory device. Since the data read operation, write operation, and erase operation in the nonvolatile semiconductor memory device 500 of the present invention according to this embodiment are the same as those described in the second embodiment, they will not be described again here. Hereinafter, in the nonvolatile semiconductor memory device 500 of the present invention according to the present embodiment, as in the second embodiment, examples of parameters of the memory element M and word lines when the memory element M (2, 1, 2) is selected Examples of voltages applied to WL1 to WL3, source lines SL1 to SL3, and bit lines BL1 to BL3 are shown.
(Memory element parameters)
Write voltage V_set = 0.5V
Erase voltage V_reset = -0.5V
Diode breakdown voltage VBD = 1V
(During read operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLread = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLread = 0 .2V
Bit line potentials other than bit lines connected to the selected memory element M (2, 1, 2): floating (during write operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLset = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLset = 0 .7V
Bit line potentials other than bit lines connected to the selected memory element M (2, 1, 2): floating (during erase operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLset = 1.2V
Potentials of source lines other than the source line connected to the selected memory element M (2, 1, 2): 0.6V
The potential of the bit line connected to the selected memory element M (2, 1, 2): VBLset = 0V
Bit line potential other than bit line connected to selected memory element M (2, 1, 2): floating

Hereinafter, a manufacturing process of the nonvolatile semiconductor memory device 500 according to the present embodiment will be described. In the manufacturing process of the nonvolatile semiconductor memory device 500 of the present invention according to the present embodiment, the nonvolatile semiconductor memory device 1 of the present invention according to the first embodiment or the nonvolatile semiconductor memory device 200 of the present invention according to the fourth embodiment. The description of the same part as the manufacturing process is omitted here.

Similar to the electroplating method described in FIG. 32 of the first embodiment, platinum (Pt) is formed on the surfaces of platinum silicides (PtSi) 158a to 158t by the electroplating method. Here, electrons are exchanged between the platinum silicides (PtSi) 158a to 158t and the plating solution, and platinum (Pt) is formed on the surfaces of the platinum silicides (PtSi) 158a to 158t. In this embodiment, electrodes made of platinum (Pt) are formed on the surfaces of platinum silicides (PtSi) 158a to 158t by electroplating, but platinum silicides (PtSi) 158a to 158t are formed by electroless plating. An electrode may be formed on the surface. As described in the first embodiment, the electroless plating method eliminates the need for wiring such as the n-type polysilicon layer 150a for flowing a current from the substrate 100 to the platinum silicide (PtSi) 158a to 158t.

Next, an electrolyte material 202 is deposited on the entire surface of the substrate 100, and electrolyte layers 202a to 202h are formed by using CMP or an etch back method (FIG. 80). In this embodiment, CuS is used as the electrolyte material 202. As the electrolyte material 202, CuS, AgGeS, CuGeS, AgGeSe, or the like can be used in addition to CuS.

Next, a resist mask is formed (not shown), and a portion indicated by G in FIG. 81A is removed by etching (FIG. 81). Through this step, the wiring (polysilicon layer 150a) used to form the electrode protective film is removed by electroplating, and the source lines are electrically insulated from each other. Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 200 according to the present embodiment is completed.

Further, after the step shown in FIG. 80, a resist mask may be formed (not shown), and the portion indicated by E in FIG. 34 of Embodiment 1 may be removed by etching to electrically insulate the source lines. . In this case, the wiring (polysilicon layer 150a) for plating remains. Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 500 according to the present embodiment is completed.

(Embodiment 8)
(OTP Memory: One Time Programmable Memory)
In the eighth embodiment, as an example of the nonvolatile semiconductor memory device of the present invention, each memory element 15 includes an insulating film such as an oxide film between PN junctions (OTP Memory: One Time Programmable Memory). ).

The nonvolatile semiconductor memory device 600 according to the eighth embodiment of the present invention is the nonvolatile semiconductor memory device 1 according to the first embodiment of the present invention or the fourth embodiment of the present invention except for the configuration of the memory element region 3. This is the same as the nonvolatile semiconductor memory device 200 of FIG. Therefore, each component of the nonvolatile semiconductor memory device 600 according to the present embodiment may not be described again.

In the nonvolatile semiconductor memory device 600 according to this embodiment, each memory element 15 has an insulating film such as an oxide film between PN junctions. In the nonvolatile semiconductor memory device 600 according to this embodiment, when writing data, a large current is passed through the memory element 15 to break down the insulating film existing between the PN junctions of the memory element 15. As the insulating film breaks down, the memory element 15 operates as a diode. On the other hand, almost no current flows through the memory element 15 in which the insulating film is not broken down. In this way, a large amount of current flows through the memory element 15 depending on whether or not the insulating film is broken down. Data stored in the memory element is read by detecting the amount of current flowing through the memory element 15.

83A, 83B, and 83C are schematic configuration diagrams of a part of the memory element region 3 of the nonvolatile semiconductor memory device 600 according to this embodiment. FIG. 83C is a top view of the memory element region 3. In FIG. 83C, as described in Embodiment 1 above, for convenience of explanation, part of the upper structure is shown separated. FIG. 83A is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line AA ′ shown in FIG. 83C. FIG. 83B is a cross-sectional view of the memory element region 3, and corresponds to a cross section taken along line BB ′ shown in FIG. 83C. As shown in FIG. 83, the memory element region 3 of the nonvolatile semiconductor memory device 600 according to this embodiment has a configuration in which memory element strings 28 having a plurality of memory elements 15a to 15d stacked in the vertical direction are arranged in a matrix. have. In the memory element region 3 of the nonvolatile semiconductor memory device 600 according to this embodiment, when the minimum processing dimension is F, the length of the memory element 15 in the AA ′ direction is 3F, and BB ′. Since the length in the direction is 2F, when one memory string has n memory elements 15 (when n memory elements are stacked), the area of the memory element 15 is 6F ² / n. .

FIG. 84A is a cross-sectional view of a part of the memory element region 3 of the nonvolatile semiconductor memory device 600 according to this embodiment, similarly to FIG. 83A. FIG. 84D is a partially enlarged view of the memory element 15, and FIG. 84E is an equivalent circuit diagram of the memory element 15. FIG. 84F is a partial equivalent circuit of the nonvolatile semiconductor memory device 600 according to this embodiment. As shown in FIG. 84A, the memory element region 3 of the nonvolatile semiconductor memory device 600 according to this embodiment includes a vertical transistor 20. A plurality (four in this embodiment) of memory elements 15 a to 15 d are stacked on the vertical transistor 20. Also in the present embodiment, a configuration including a plurality of (four in the present embodiment) memory elements 15 a to 15 d stacked on the vertical transistor 20 is referred to as a memory element string 28. The memory element region 3 of the nonvolatile semiconductor memory device 600 according to the present embodiment has 10 × 20 = 200 memory element strings 28 as shown in FIG. 1 or FIG.

In the present embodiment, the memory string 28 includes memory elements 15a to 15d. The memory element 15a includes an n-type polysilicon layer 212a, an insulating film 210a, and a p-type polysilicon layer 144a. The memory element 15b includes an n-type polysilicon layer 212a, an insulating film 210a, and a p-type polysilicon layer 144b. The memory element 15c includes an n-type polysilicon layer 212a, an insulating film 210a, and a p-type polysilicon layer 144c. The memory element 15a includes an n-type polysilicon layer 212a, an insulating film 210a, and a p-type polysilicon layer 144d.

Each of the memory elements 15a to 15d constituting the memory string 28 has a common n-type polysilicon layer 212a and an insulating film 210a. The p-type polysilicon layers 144a, 144b, 144c, and 144d constitute the source line 9 and are each formed in a plate shape. In the memory element region 3 of the nonvolatile semiconductor memory device 600 according to this embodiment, all the memory strings 28 have p-type polysilicon layers 144a, 144b, 144c, and 144d in common.

As shown in FIG. 84D, the memory element 15a of the nonvolatile semiconductor memory device 600 according to this embodiment is provided between the PN junction composed of the n-type polysilicon layer 212a, the insulating film 210a, and the p-type polysilicon film 144a. It has a structure in which an insulating film such as an oxide film is sandwiched. As described above, the memory element 15a has a structure in which the insulating film 210a is sandwiched between the n-type polysilicon layer 212a and the p-type polysilicon layer 144a. Note that, in the memory element 15a of the nonvolatile semiconductor memory device 600 according to the present embodiment, the polysilicon layer 212a is p-type and the polysilicon layer 144a is formed so that the PN junction is opposite, as in the other embodiments. It may be formed as an n-type.

In the nonvolatile semiconductor memory device 600 according to this embodiment, one end of the memory element 15 is connected to the source line 9 (SL) via the source line selection transistor 26 as in the first embodiment. As described above, each source line 9 has a planar structure composed of the same layer, and has a plate-like planar structure. The other end of the memory element 15 is connected to the bit line 5 (BL) via the vertical transistor 20. A bit line selection transistor 24 is connected to one end of the bit line 5 (BL). A signal is applied to the bit line 5 (BL) by the bit line selection transistor 24. The word line 11 (WL) is connected to the gate of the vertical transistor 20. A signal is applied to the word line 11 (WL) by the word line selection transistor 22.

In the nonvolatile semiconductor memory device 600 according to the present embodiment, as in the first embodiment, as shown in FIG. 84, one ends of the plurality of memory elements 15 stacked in the vertical direction are connected to each other, and the vertical transistor 20 Is connected to the word line 11 (WL).

83 and 84, one memory element string 28 has been described. However, in the nonvolatile semiconductor memory device 600 according to this embodiment, all the memory strings 28 have the same configuration. Further, the number of the memory strings 28 and the number of the memory elements 15 constituting the memory strings 28 can be appropriately changed to any number according to the memory capacity.

The nonvolatile semiconductor memory device 500 of the present invention according to this embodiment is considered in the same manner as the nonvolatile semiconductor memory device of the unipolar operation described in the first embodiment, except that the erase operation cannot be performed. Can do. The data read operation and write operation in the nonvolatile semiconductor memory device 600 according to the present embodiment are the same as the operations described in the first embodiment, and therefore will not be described again here. Hereinafter, in the nonvolatile semiconductor memory device 600 of the present invention according to the present embodiment, as in the second embodiment, an example of parameters of the memory element M and a word line when selecting the memory element M (2, 1, 2) Examples of voltages applied to WL1 to WL3, source lines SL1 to SL3, and bit lines BL1 to BL3 are shown.
(Memory element parameters)
Write voltage V_set = 4.0V
Diode breakdown voltage VBD = 2V
(During read operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLread = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLread = 1 0.0V
Bit line potentials other than bit lines connected to the selected memory element M (2, 1, 2): floating (during write operation)
The potential of the word line connected to the selected memory element M (2, 1, 2): Von = 3V
Potentials of word lines other than word lines connected to the selected memory element M (2, 1, 2): Voff = 0V
The potential of the source line connected to the selected memory element M (2, 1, 2): VSLset = 0V
Potentials of source lines other than source lines connected to selected memory element M (2, 1, 2): Potentials of bit lines connected to floating selected memory element M (2, 1, 2): VBLset = 5 0.0V
Bit line potential other than bit line connected to selected memory element M (2, 1, 2): floating

Hereinafter, a manufacturing process of the nonvolatile semiconductor memory device 600 according to the present embodiment will be described. In the manufacturing process of the nonvolatile semiconductor memory device 600 of the present invention according to this embodiment, the same parts as those of the manufacturing process of the nonvolatile semiconductor memory device 1 of the present invention according to Embodiment 1 will be described again here. Omitted.

Similar to the process described in FIG. 28 of the first embodiment, a resist mask is formed (not shown), and the silicon oxide films 130, 134, 138, 142, and 146 and the p-type polysilicon films 132, 136, 140, and 144 are formed. By partially etching holes 154a to 154h and p-type polysilicon films 132a, 136a, 140a and 144a are formed (FIG. 85). At this time, the silicon nitride film 128 functions as an etching stopper film. In the present embodiment, the cylindrical holes 154a to 154h are formed. However, the present invention is not limited to this, and various shapes such as a prismatic shape and an elliptical shape may be formed. Good.

Next, an insulating film 210 is formed on the entire surface of the substrate 100. In this embodiment, a silicon oxide film of about 2 nm is formed, but the thickness and material of the insulating film are not limited to this.

Next, a part of the insulating film 210 and a part of the silicon nitride film 128 are removed by reactive ion etching (FIG. 87). Next, n-type polysilicon 212 is deposited on the entire surface of the substrate 100, and n-type polysilicon layers 210a to 210h are formed by using CMP or an etch back method (FIG. 87). In this embodiment, n-type polysilicon is formed. However, n-type amorphous silicon may be formed and annealed to form an n-type polysilicon layer.

Thereafter, various wirings are formed, and the memory element region 3 of the nonvolatile semiconductor memory device 600 according to this embodiment is completed.

(Embodiment 9)
In the above-described first to eighth embodiments, the example in which the select transistor 20 in the memory element region 3 is disposed below the memory element has been described. In the present embodiment, an example in which the selection transistor 20 in the memory element region 3 is arranged on the upper side of the memory element and an example in which the selection transistor 20 is arranged on both upper and lower sides will be described. The arrangement example of the selection transistor of this embodiment can be applied to all the above-described embodiments.

Refer to FIG. Here, the nonvolatile semiconductor memory device 1 according to the first embodiment will be described as an example. FIG. 88A shows a configuration example in which the select transistor 20 in the memory element region 3 is disposed below the memory element as described in the first to eighth embodiments.

FIG. 88B shows a configuration example in which the select transistor 20 in the memory element region 3 is arranged above the memory element. In the example shown in FIG. 88B, after the memory elements 15a to 15d are formed, the selection transistor 20 is formed.

FIG. 89A shows a configuration example in which the select transistor 20 in the memory element region 3 is arranged above the memory element. In the example shown in FIG. 89A, the lower selection 220 is formed, the memory elements 15a to 15d are formed, and then the upper selection transistor 20 is formed. By employing the structure shown in FIG. 89A, the circuit configuration described with reference to FIGS. 10 to 12 can be realized.

(Embodiment 10)
In the first to eighth embodiments described above, the memory element 15 and the selection transistor 20 in the memory element region 3 are smaller than the width of the word line WL, and when viewed from above, the memory element 15 and the selection transistor 20 are not connected to the word line. The example arrange | positioned in was demonstrated. In the present embodiment, an example in which the memory element 15 and the selection transistor 20 in the memory element region 3 are smaller than the width of the word line WL and the memory element 15 is arranged so as to protrude from the word line when viewed from above. To do. The arrangement example of the memory element 15 and the selection transistor 20 of the present embodiment can be applied to all the above-described embodiments.

Refer to FIG. Here, the nonvolatile semiconductor memory device 1 according to the first embodiment will be described as an example. FIG. 90A is a diagram corresponding to FIG. 2C described in the first embodiment. Also in FIG. 90 (A), for convenience of explanation, part of the upper structure is shown separated. FIG. 90B is a top view showing a structure of the selection transistor 20 portion. In the example shown in FIGS. 90A and 90B, when the minimum processing dimension is F, the length of the memory element 15 in the AA ′ direction is 3F and the length in the BB ′ direction. Is 2F, and when one memory string includes n memory elements 15 (when n memory elements are stacked), the area of the memory element 15 is 6F ² / n.

Refer to FIG. FIG. 91 (A) is a top view of the memory element region 3 of the nonvolatile semiconductor memory device 1 according to the first embodiment, as in FIG. 90 (A). Also in FIG. 91A, for convenience of explanation, a part of the upper structure is shown peeled off. FIG. 91B is a top view showing the structure of the select transistor 20 portion. In this case, the memory element 15 and the select transistor 20 in the memory element region 3 are smaller than the width of the word line WL, and when viewed from above, the memory element 15 is disposed so as to protrude from the word line. In the example shown in FIGS. 91A and 91B, when the minimum processing dimension is F, the length of the memory element 15 in the AA ′ direction is 2F, and the length in the BB ′ direction. Is 2F, and when one memory string includes n memory elements 15 (when n memory elements are stacked), the area of the memory element 15 is 4F ² / n. Therefore, by employing the arrangement structure of the memory elements and selection transistors shown in FIGS. 91A and 91B, a nonvolatile semiconductor memory device with more excellent area efficiency can be realized.

1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 1 according to an embodiment of the present invention. (A), (B), and (C) are some schematic block diagrams of the memory element area | region 3 of the non-volatile semiconductor memory device 1 which concerns on one Embodiment. FIG. 2A is a cross-sectional view of a part of a memory element region 3 of a nonvolatile semiconductor memory device 1 according to an embodiment. (D) is the elements on larger scale of the memory element 15 of the non-volatile semiconductor memory device 1 which concerns on one Embodiment. FIG. 4E is an equivalent circuit diagram of the memory element 15 of the nonvolatile semiconductor memory device 1 according to the embodiment. (F) is an equivalent circuit of a part of the nonvolatile semiconductor memory device 1 according to the embodiment. It is a figure which shows the bias conditions in read-out operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the bias conditions in the write-in operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the bias conditions in the erase | elimination operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the bias conditions in read-out operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the bias conditions in the write-in operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the bias conditions in the erase | elimination operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the bias conditions in the write-in operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the bias conditions in the erase | elimination operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the bias conditions in read-out operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. 1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 1 according to an embodiment of the present invention. 1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 1 according to an embodiment of the present invention. 1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 1 according to an embodiment of the present invention. 1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 1 according to an embodiment of the present invention. It is a figure which shows the bias conditions in the erase | elimination operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the bias conditions in the erase | elimination operation | movement of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. 1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 200 according to an embodiment of the present invention. (A), (B), and (C) are some schematic block diagrams of the memory element area | region 3 of the non-volatile semiconductor memory device 200 which concerns on one Embodiment. FIG. 4A is a partial cross-sectional view of a memory element region 3 of a nonvolatile semiconductor memory device 200 according to an embodiment. (D) is the elements on larger scale of the memory element 15 of the non-volatile semiconductor memory device 200 which concerns on one Embodiment. FIG. 5E is an equivalent circuit diagram of the memory element 15 of the nonvolatile semiconductor memory device 200 according to the embodiment. (F) is an equivalent circuit of a part of the nonvolatile semiconductor memory device 200 according to one embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. (A), (B), and (C) are the schematic block diagrams of a part of the memory element region 3 of the nonvolatile semiconductor memory device 300 according to one embodiment. FIG. 4A is a partial cross-sectional view of a memory element region 3 of a nonvolatile semiconductor memory device 300 according to an embodiment. (D) is the elements on larger scale of the memory element 15 of the non-volatile semiconductor memory device 300 which concerns on one Embodiment. FIG. 5E is an equivalent circuit diagram of the memory element 15 of the nonvolatile semiconductor memory device 300 according to the embodiment. (F) is an equivalent circuit of a part of the nonvolatile semiconductor memory device 300 according to the embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. (A), (B), and (C) are some schematic block diagrams of the memory element area | region 3 of the non-volatile semiconductor memory device 400 which concerns on one Embodiment. FIG. 4A is a cross-sectional view of a part of a memory element region 3 of a nonvolatile semiconductor memory device 400 according to an embodiment. (D) is the elements on larger scale of the memory element 15 of the non-volatile semiconductor memory device 400 concerning one Embodiment. FIG. 5E is an equivalent circuit diagram of the memory element 15 of the nonvolatile semiconductor memory device 400 according to the embodiment. (F) is an equivalent circuit of a part of the nonvolatile semiconductor memory device 400 according to the embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. (A), (B), and (C) are some schematic block diagrams of the memory element area | region 3 of the non-volatile semiconductor memory device 500 which concerns on one Embodiment. FIG. 4A is a cross-sectional view of a part of a memory element region 3 of a nonvolatile semiconductor memory device 500 according to an embodiment. (D) is the elements on larger scale of the memory element 15 of the non-volatile semiconductor memory device 500 concerning one Embodiment. FIG. 5E is an equivalent circuit diagram of the memory element 15 of the nonvolatile semiconductor memory device 500 according to the embodiment. (F) is an equivalent circuit of a part of the nonvolatile semiconductor memory device 500 according to the embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. 6 is a graph showing the magnitude of current that flows when a voltage is applied to a memory element of unipolar operation of the nonvolatile semiconductor memory device of the present invention according to one embodiment. (A), (B) and (C) are schematic configuration diagrams of a part of the memory element region 3 of the nonvolatile semiconductor memory device 600 according to the embodiment. FIG. 4A is a cross-sectional view of a part of a memory element region 3 of a nonvolatile semiconductor memory device 600 according to an embodiment. (D) is the elements on larger scale of the memory element 15 of the non-volatile semiconductor memory device 600 which concerns on one Embodiment. FIG. 5E is an equivalent circuit diagram of the memory element 15 of the nonvolatile semiconductor memory device 600 according to the embodiment. (F) is an equivalent circuit of a part of the nonvolatile semiconductor memory device 600 according to the embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. It is a figure which shows the manufacturing process of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. (A) And (B) is sectional drawing of the memory element area | region of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. (A) is sectional drawing of the memory element area | region of the non-volatile semiconductor memory device of this invention which concerns on one Embodiment. (A) is a top view of the memory element region 3 of the nonvolatile semiconductor memory device of the present invention according to one embodiment. FIG. 4B is a top view of the select transistor portion of the nonvolatile semiconductor memory device according to the embodiment. (A) is a top view of the memory element region 3 of the nonvolatile semiconductor memory device of the present invention according to one embodiment. FIG. 4B is a top view of the select transistor portion of the nonvolatile semiconductor memory device according to the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Nonvolatile semiconductor memory device 3 Memory element area | region 5 Bit line 7 Bit line drive circuit 9 Source line 11 Word line 13 Word line drive circuit 15 Memory element

Claims (5)

A plurality of memory element groups each including a plurality of memory elements in which a resistance change element and a diode are connected in series;
A plurality of source lines respectively connected to one end of each of the plurality of memory elements of the memory element group;
Have
The non-volatile semiconductor memory device, wherein each of the plurality of source lines of the plurality of memory element groups is a two-dimensional plate-like conductor layer. A plurality of memory element groups each including a plurality of memory elements in which a resistance change element and a diode are connected in series;
A plurality of select transistors each having one of a source and a drain connected to one end of each of the plurality of memory elements of the memory element group;
A plurality of source lines respectively connected to the other ends of the plurality of memory elements of the memory element group;
A plurality of bit lines to which the other of the sources and drains of the plurality of selection transistors is connected;
A plurality of word lines to which gates of the plurality of selection transistors are respectively connected;
Have
The non-volatile semiconductor memory device, wherein each of the plurality of source lines is a plate-like conductor layer extending two-dimensionally. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of memory elements of the memory element group are arranged in the same plane. The nonvolatile semiconductor memory device according to claim 1, wherein each of the plurality of memory element groups is stacked via an insulator. The nonvolatile semiconductor memory device according to claim 1, wherein the variable resistance element includes a metal oxide, a phase change film, a material having an electric field induced resistance change effect, or an electrolyte material.