JP2008181594A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device improving yield of selection. <P>SOLUTION: Read data read from a memory cell array 15 by a read command in a normal operation mode are readable from an external terminal 10. In a test mode, the timing adjustment part 40 adjusts the timing so that the read data read from the memory cell array 15 by the read command can be compared with expectation data input from the external terminal 10. A comparison circuit 23 compares the read data adjusted by the timing adjustment part 40 with the expectation data. When the result of the comparison by the comparison circuit 23 does not indicate matching, an address latch circuit 25 latches the address of the memory cell array 15 as an address for capacity fuse. The capacity fuse circuit 17 repairing a defective cell disconnects a capacity fuse element on the basis of the latched address for capacity fuse. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a function of relieving a defective cell.

  In a semiconductor memory device such as a DRAM, a large number of memory cells are provided, so that defective cells, which are memory cells that do not function normally, may occur. If even one such defective cell occurs, discarding the entire semiconductor memory device as a defective product increases the manufacturing cost of the semiconductor memory device. Therefore, there are various repair methods when a defective cell occurs. A method has been proposed.

  For example, in Patent Document 1, when a defective cell is detected in a test process for confirming the presence / absence of a defective cell, the address of the defective cell is latched inside the semiconductor memory device, and the capacitor fuse is cut in the manufacturing process. There has been disclosed a method for relieving a defective cell so that this is automatically performed.

JP 2003-338192 A

  In recent years, unstable defects are likely to occur due to miniaturization of device manufacturing technology and a reduction in the voltage of the power supply inside the device. How to reproduce such unstable defects in the relief process is an important yield measure. Occurrence of defects is determined by what occurs after the subsequent process and determines the yield, and may not be able to be reproduced by remediation in the previous process, which is extremely efficient. Capacitance fuses make it possible to relieve a post-process in which a defective cell that becomes unstable and becomes defective, and the reproducibility of the occurrence of a defect greatly affects the yield in the post-process. However, with the progress of device manufacturing technology, it is desired to further improve the selection yield, but no technology has been known that improves the reproducibility of the occurrence of defects and relieves defective cells.

  By the way, the present inventor has found that in the conventional defective cell remedy method, the operation failure according to the usage standard may not always be reproduced in the simultaneous read mode of the data of a plurality of addresses which is the test mode. The cause of this problem is that the address fetch for the relief by the capacitor fuse is performed in the simultaneous read test mode of the data of the plurality of addresses which is not the operation in accordance with the use standard, and the data of the plurality of addresses is read at the same time. In addition, it is assumed that the operating environment of the memory cell array is different from that in the operation according to the usage standard. In other words, when the operation different from the standard operation specifications is performed in this way, there is a possibility that a defective bit that is defective in the standard operation specification may not be defective, and a defect that does not fail in the simultaneous write mode of data of multiple addresses. It was found that the bit cannot take in the address of the capacitor fuse and the defective bit cannot be relieved, so that the sorting yield is lowered. In view of this, the inventors have considered that it is possible to improve the sorting yield by repairing a defective cell with a capacitive fuse in a state close to the standard use state, and have come up with the present invention.

  A semiconductor memory device according to one aspect of the present invention includes a capacitive fuse circuit that relieves a defective cell, and read data read from a memory cell by a read command in a normal operation mode can be read from an external terminal. A semiconductor memory device in which write data input from an external terminal by a write command in a normal operation mode can be written to a memory cell, which is active in a test mode and read from the memory cell by a read command And a timing adjustment unit that adjusts the timing so that the expected value data input from the external terminal can be compared, a comparison circuit that compares the read data and the expected value data whose timing is adjusted by the timing adjustment unit, Ratio in comparison circuit Results comprises an address latch circuit for latching the address of a memory cell as an address for capacity fuses If they do not match, and capacity fuse circuit which performs cutting of the capacitive fuse element based on the latched capacity fuse addresses, the.

  In the semiconductor memory device of the present invention, it is preferable that the timing at which the read data is read from the memory cell by the read command is the same in the test mode and the normal operation mode.

  In the semiconductor memory device of the present invention, the timing adjustment unit includes a first latch circuit that latches read data read from the memory cell by a read latch signal based on a read command, and expected value data input from an external terminal. A second latch circuit that latches with a write latch signal based on a read command; and a timing circuit that provides a comparison start timing obtained by delaying the write latch signal to the comparison circuit. It is preferable to compare the outputs of the second latch circuit.

  In the semiconductor memory device of the present invention, it is preferable that the timing adjustment unit adjusts the timing of the write latch signal by giving a time delay corresponding to the write latency to the read latch signal in the test mode.

  In the semiconductor memory device of the present invention, the timing adjustment unit does not give a time delay corresponding to the additive latency to the address signal for specifying the memory cell and the read latch signal for the read data of the memory cell in the test mode. In addition, it is preferable to adjust the timing without giving a time delay corresponding to the write latency to the read latch signal.

  According to the present invention, the read data whose timing is adjusted by the timing adjustment unit and the expected value data are compared, so that the address of the capacitor fuse can be taken in at the timing according to the standard operation specification. Therefore, since it becomes possible to relieve a defective bit that becomes defective in the standard operation specifications, the efficiency of relieving by the capacitive fuse is increased, and the sorting yield can be further improved.

  The semiconductor memory device according to the embodiment of the present invention includes a capacitive fuse circuit (17 in FIG. 1) for relieving a defective cell, and is read from the memory cell array (15 in FIG. 1) by a read command in the normal operation mode. Read data can be read from the external terminal (10 in FIG. 1), and write data input from the external terminal (10 in FIG. 1) by a write command in the normal operation mode can be written to the memory cell array (15 in FIG. 1). This is applied to a semiconductor memory device. In the test mode, when the read operation is performed by the read command, the write operation is performed up to the comparison circuit (23 in FIG. 1). Further, expected value data of output data by the read operation is input from an external terminal (10 in FIG. 1). Further, the comparison start timing circuit (26 in FIG. 1) generates a comparison start timing between the output data by the read operation and the expected value data by the write operation in the comparison circuit (23 in FIG. 1) based on the write latch signal. The address latch circuit (25 in FIG. 1) inputs the comparison result (correction determination) by the comparison circuit (23 in FIG. 1). In this case, the output data by the input read operation and the expected value data by the write operation are compared, and if they do not match (if they are incorrect), the address signal is latched, and the address that becomes defective in the standard operation is fetched The capacitor fuse element (17 in FIG. 1) is configured to cut the capacitor fuse element. By such cutting of the capacitive fuse element, a defective cell is designated as an alternative cell and is relieved. In this way, it is possible to perform relief in a form close to the actual operation in the subsequent process, and it is possible to reliably repair defects that occur in the operation in accordance with the standard in the subsequent process.

  In the conventional capacity fuse relief address fetching method, it is necessary to enter the simultaneous write mode for the data of multiple addresses, which is not the standard operation specification, and the operation specification of the cell array is the standard for simultaneous writing of the data of multiple addresses The operation is different from the operation specifications. When an operation different from the standard operation specification is performed, there is a possibility that a defective bit that is defective in the standard operation specification is not defective. For this reason, a defective bit that does not become defective in the simultaneous write mode of data at a plurality of addresses cannot fetch the address of the capacitive fuse, and the defective bit cannot be relieved.

  On the other hand, according to the semiconductor memory device of the present invention, it is possible to fetch the address of the capacitive fuse according to the standard operation specification. Therefore, it becomes possible to relieve a defective bit that becomes defective in the standard operation specification, leading to an improvement in yield.

  FIG. 1 is a block diagram showing a main part of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, the semiconductor memory device includes an external terminal 10, a parallel-serial conversion circuit 11, a write bus driver 12, a read bus latch circuit 13, a data amplifier 14, a memory cell array 15, a buffer 16, a capacitor fuse circuit 17, a redundant circuit 18, A redundancy switching circuit 19, an address AL selector circuit 20, a read AL selector circuit 21, a write WL selector circuit 22, a comparison circuit 23, a write data latch circuit 24, an address latch circuit 25, and a comparison start timing circuit 26 are provided. Here, the read bus latch circuit 13, the read AL selector circuit 21, the write WL selector circuit 22, the write data latch circuit 24, and the comparison start timing circuit 26 correspond to the timing adjustment unit 40.

  The address AL selector circuit 20 receives a COL (column) system address signal CA1, an AL-MRS (additive latency mode register setting) information signal ALM, and an internal clock signal CLK, and is synchronized with the timing of the internal clock signal CLK. Then, a delay corresponding to the additive latency set by the AL-MRS information signal ALM is given to the COL system address signal CA1, and is output to the buffer 16 and the address latch circuit 25 as the COL system address input signal CA2.

  The read AL selector circuit 21 receives the read signal RS, the AL-MRS information signal ALM, and the internal clock signal CLK, and synchronizes with the timing of the internal clock signal CLK in response to the read signal RS. A delay corresponding to the additive latency set in step (1) is given and output to the read bus latch circuit 13 and the parallel / serial conversion circuit 11 as a read latch signal RL.

  The write WL selector circuit 22 receives a write signal WS, a read signal RS, an internal clock signal CLK, a WL-MRS (write latency mode register setting) information signal WLM, and an address fetch mode signal MODE, and receives an internal clock signal CLK. In synchronization with this timing, a delay corresponding to the write latency set by the WL-MRS information signal WLM is given to the write signal WS, and the write bus driver 12, the write data latch circuit 24, and comparison start as the write latch signal WL The data is output to the timing circuit 26 and the parallel / serial conversion circuit 11.

  The parallel-serial conversion circuit 11 takes in the data signal DQ input from the external terminal 10 when the write latch signal WL is activated when the address take-in mode signal MODE is not active, that is, in the normal operation mode, and the write bus The signal WB is output to the write bus driver 12 and the write data latch circuit 24. Further, the read bus signal RB output from the read bus latch circuit 13 when the read latch signal RL is activated is output to the external terminal 10 as the data signal DQ. When the address fetch mode signal MODE is active, that is, in the test mode, the memory cell array 15 is in a read operation, but the parallel-serial conversion circuit 11 is connected to an external terminal when the write latch signal WL is activated. The data signal DQ input from 10 is taken in and output to the write bus driver 12 and the write data latch circuit 24 as the write bus signal WB.

  The write bus driver 12 receives an address fetch mode signal MODE, a write latch signal WL, and a write bus signal WB. When the address fetch mode signal MODE is not active and the write latch signal WL is active, the write bus signal WB is input. Is output to the data amplifier 14 as the data bus signal DB. On the other hand, when the address fetch mode signal MODE is active, the output is kept at high impedance. For the purpose of reducing the number of wirings, the data bus signal DB is used in common in the normal write operation and read operation. However, the write bus driver 12 does not rewrite the read data read as the data bus signal DB by the read operation when the address fetch mode is executed.

  When the read latch signal RL becomes active, the read bus latch circuit 13 latches the data bus signal DB and outputs it as a read bus signal RB to the comparison circuit 23 and the parallel serial conversion circuit 11.

  When data is read from a cell, the data amplifier 14 amplifies the main I / O signal IOS output from the memory cell array 15 or the redundancy circuit 18 via the redundancy switching circuit 19 to the read bus latch circuit 13 as a data bus signal DB. Output. When data is written to the cell, the data bus signal DB output from the write bus driver 12 is amplified and output to the memory cell array 15 or the redundant circuit 18 through the redundancy switching circuit 19 as the main I / O signal IOS.

  The buffer 16 amplifies the COL address input signal CA2 and the ROW (row) address signal RA and outputs the amplified address to the memory cell array 15 as an address corresponding to a cell from which data is to be read or written.

  The write data latch circuit 24 receives the write bus signal WB, the write latch signal WL, and the address fetch mode signal MODE. When the address fetch mode signal MODE is active, the write data latch circuit 24 latches the write bus signal WB with the write latch signal WL. , And output as a write data signal WD to one end of the comparison circuit 23.

  The comparison start timing circuit 26 receives the write latch signal WL, gives a predetermined delay, and outputs it as a comparison start signal CS to the comparison circuit 23.

  The comparison circuit 23 receives the write data signal WD, the read bus signal RB, the comparison start signal CS, and the address capture mode signal MODE. When the address capture mode signal MODE is active, the comparison start signal CS becomes active. The write data signal WD and the read bus signal RB are compared at the timing. As a result of the comparison, if the data does not match, that is, if the output data (corresponding to the read bus signal RB) by the read operation and the expected value data (corresponding to the write data signal WD) by the write operation do not match, the address fetch signal AL is It is output to the address latch circuit 25 as active.

  The address latch circuit 25 receives an address fetch signal AL, a ROW (row) address signal RA, a COL address input signal CA2, and an address fetch mode signal MODE, and the address fetch mode signal MODE is active (test mode). If the address fetch signal AL is active, the COL system address input signal CA2 and the ROW system address signal RA are latched and output to the capacitor fuse circuit 17. If the address fetch mode signal MODE is not active, that is, in normal operation, whether the input COL address input signal CA2 and the ROW (row) address signal RA are addresses to be repaired in the capacitive fuse circuit 17 or not. If it is determined whether or not to be repaired, the buffer 16 is not operated, and the redundant switching circuit 19 is set to be connected to the data amplifier 14 and the redundant circuit 18. If the data is not to be repaired, the buffer 16 is operated, and the redundancy switching circuit 19 is set so that the data amplifier 14 and the memory cell array 15 are connected.

  The capacitive fuse circuit 17 cuts the fuse element corresponding to the address latched in the test mode in the address latch circuit 25 and whether or not the fuse element corresponding to the address latched in the normal mode in the address latch circuit 25 is cut. Is notified to the address latch circuit 25. That is, it is determined whether or not the address latched in the normal mode is an address to be relieved, and the address latch circuit 25 is notified.

  The memory cell array 15 is composed of a plurality of memory cells, and a cell corresponding to an address given by the buffer 16 is accessed. In the read operation, the data of the corresponding cell is output to the data amplifier 14 as the main I / O signal IOS through the redundancy switching circuit 19. In addition, the main I / O signal IOS output from the data amplifier 14 in the write operation is written to the corresponding cell via the redundancy switching circuit 19.

  The redundancy circuit 18 is a circuit that constitutes a substitute cell for a defective cell in the memory cell array 15, and one of the memory cell array 15 and the redundancy circuit 18 is selected by the redundancy switching circuit 19 and connected to the data amplifier 14.

  Next, a data comparison operation for taking in an address will be described using the timing chart shown in FIG. When the address take-in mode signal MODE is activated (entry to the test mode), the write WL selector circuit 22 becomes valid. When a read command is input, the parallel-serial conversion circuit 11 has a write operation specification. Further, the write data latch circuit 24, the comparison start timing circuit 26, the comparison circuit 23, and the address latch circuit 25, which are data comparison circuits, are enabled.

  When an ACT command and a read command are input, a ROW address signal RA and a COL address input signal CA1 are input in the same manner as in the normal specification operation, and a cell data read signal is operated, and the corresponding cell in the memory cell array 15 is operated. Data is read as the main I / O signal IOS. Data read as the main I / O signal IOS is amplified by the data amplifier 14 and input to the read bus latch circuit 13 as the data bus signal DB. Then, the read bus latch circuit 13 outputs the cell data of the array to the comparison circuit 23 as the read bus signal RB in response to the read latch signal RL. The parallel-serial conversion circuit 11 which is the other output destination of the read bus signal RB is different from the normal read operation in that the read operation is not performed by the address take-in mode signal MODE.

  When the parallel-serial conversion circuit 11 is set to the test mode of the address fetch mode, the parallel-serial conversion circuit 11 performs a write operation equivalent to the normal operation by the address fetch mode signal MODE. After waiting for a time corresponding to the write latency from the read command, an expected value of data read from the cell is input to the external terminal 10. The expected value data input from the external terminal 10 is output from the parallel-serial conversion circuit 11 as the write bus signal WB, and is latched by the write data latch circuit 24 by the write latch signal WL. At this time, the write bus driver 12 is different from the normal write operation in that it is deactivated by the address fetch mode signal MODE.

  The write data latch circuit 24 outputs the latched write bus signal WB to the comparison circuit 23 as the write data signal WD. Here, since there is a write latency waiting period, the write data signal WD that is the expected value data of the cell read data to the comparison circuit 23 according to the write specification is more than the read bus signal RB that is the cell read data according to the read specification. It will be late. Therefore, the comparison start timing circuit 26 adjusts the timing of the write latch signal WL, which is the output timing of the write data signal WD, to generate the comparison start signal CS.

  The comparison circuit 23 compares the read bus signal RB and the write data signal WD with the comparison start signal CS, and outputs the comparison result to the address latch circuit 25 as the address fetch signal AL. If the signal level of the read bus signal RB that is the cell read data and the write data signal WD that is the expected value data of the cell read data are different, that is, if it is determined that the cell read data is in error, the address fetch The signal AL is output to the address latch circuit 25.

  The address latch circuit 25 activated (valid) by the address fetch mode signal MODE latches the ROW address signal RA as a row address and the COL address input signal CA2 as a column address. The capacitive fuse circuit 17 destroys the capacitive fuse related to the cell corresponding to the ROW address signal RA and the COL address input signal CA2 latched by the address latch circuit 25 after the address capture mode is completed. As a result, the defective cell is relieved.

  FIG. 3 is a block diagram showing the main part of the semiconductor memory device according to the second embodiment of the present invention. In FIG. 3, the semiconductor memory device includes an external terminal 10, a parallel-serial conversion circuit 11, a write bus driver 12, a read bus latch circuit 13, a data amplifier 14, a memory cell array 15, a buffer 16, a capacitor fuse circuit 17, a redundant circuit 18, Redundancy switching circuit 19, address AL selector circuit 20, read AL selector circuit 21, write WL selector circuit 22a, comparison circuit 23, write data latch circuit 24, address latch circuit 25, comparison start timing circuit 26, test mode Selector circuits 31, 33, 35, a test mode write timing circuit 32, and a test mode read timing circuit 34 are provided. Here, the read bus latch circuit 13, the write data latch circuit 24, the comparison start timing circuit 26, the test mode selector circuits 31, 33, 35, the test mode write timing circuit 32, and the test mode read timing circuit 34 adjust timing. It corresponds to the part 40a. In FIG. 3, the same reference numerals as those in FIG.

  The write WL selector circuit 22a receives a write signal WS, an internal clock signal CLK, and a WL-MRS (write latency mode register setting) information signal WLM, and generates a write signal WS in synchronization with the timing of the internal clock signal CLK. On the other hand, a delay corresponding to the write latency set by the WL-MRS information signal WLM is given and output to the test mode selector circuit 33.

  When the address take-in mode signal MODE is not active (normal operation mode), the test mode selector circuit 31 outputs the output signal of the address AL selector circuit 20 to the buffer 16 and the address latch circuit 25 as the COL system address input signal CA2. To do. When the address fetch mode signal MODE is active (test mode), the COL system address input signal CA1 is output to the buffer 16 and the address latch circuit 25 as it is as the COL system address input signal CA2.

  The test mode write timing circuit 32 receives the read signal RS, gives a predetermined time delay, and outputs it to the test mode selector circuit 33.

  When the address fetch mode signal MODE is not active (normal operation mode), the test mode selector circuit 33 uses the output signal of the write WL selector circuit 22a as the write latch signal WL, the write bus driver 12, the write data latch circuit 24, The data is output to the comparison start timing circuit 26 and the parallel / serial conversion circuit 11. When the address fetch mode signal MODE is active (test mode), the write bus driver 12, the write data latch circuit 24, the comparison start timing circuit 26, and the output signal of the test mode write timing circuit 32 are used as the write latch signal WL. The data is output to the parallel / serial conversion circuit 11.

  The test mode read timing circuit 34 receives the read signal RS, gives a predetermined time delay, and outputs it to the test mode selector circuit 35.

  When the address take-in mode signal MODE is not active (normal operation mode), the test mode selector circuit 35 uses the output signal of the read AL selector circuit 21 as the read latch signal RL and the read bus latch circuit 13 and the parallel serial conversion circuit 11. Output to. When the address fetch mode signal MODE is active (test mode), the output signal of the test mode read timing circuit 34 is output to the read bus latch circuit 13 and the parallel serial conversion circuit 11 as a read latch signal RL.

  Next, the timing of data comparison for address capture in the test mode will be described using the timing chart shown in FIG. By making the address take-in mode signal MODE active, the test mode selector circuit 31 sets the output timing of the COL system address input signal CA2 to the COL system address signal after waiting for AL (additive latency) that is the timing of standard operation specifications. (The output signal of the address AL selector circuit 20) is switched to the COL system address signal CA1. The test mode selector circuit 35 changes the output timing of the read latch signal RL from the read signal after the AL standby of the standard operation specification (output signal of the read AL selector circuit 21) to the test mode read signal (test mode read timing circuit 34). Output signal). The test mode selector circuit 33 changes the output timing of the write latch signal WL from the write signal after waiting for the standard operation WL (output signal of the write WL selector circuit 22a) to the test mode write signal (test mode write timing circuit 32). Output signal). With these switching operations, the additive latency and write latency settings in the standard operation are invalidated, and the test mode read signal generated by the test mode write timing circuit 32 and the test mode read timing circuit 34 are generated. Set the signal separately from the standard operation.

  Such a setting makes it possible to make the timings of the read latch signal RL and the write latch signal WL as close as possible, and to match the comparison timings of the read bus signal RB and the write data signal WD. As a result, it is not necessary to almost delay the comparison start signal CS, and the address fetch signal AL can be output without waiting as in the first embodiment. Therefore, the time until the comparison result is obtained is shortened, the inspection cycle is accelerated, and the defective bit relief operation can be performed efficiently.

  In other words, in the first embodiment, the write latch signal WL and the read latch signal RL operate after waiting for additive latency and write latency, as in the standard read operation. In contrast, in this embodiment, when the address capture mode signal MODE is activated, the additive latency and write latency settings, which are standard operation specifications, are invalidated, and the write latch signal WL and the read latch signal RL are both Switches to the timing dedicated to the address capture mode. As a result, the waiting time from the read latch signal RL to the generation of the write latch signal WL in the first embodiment can be shortened, and a more efficient operation can be performed.

  The present invention has been described with reference to the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and those skilled in the art within the scope of the invention of each claim of the present application claims. It goes without saying that various modifications and corrections that can be made are included.

1 is a block diagram showing a main part of a semiconductor memory device according to a first embodiment of the present invention. 3 is a timing chart of address fetching in the semiconductor memory device according to the first example of the present invention. FIG. 7 is a block diagram showing a main part of a semiconductor memory device according to a second example of the present invention. 6 is a timing chart of address fetching in a semiconductor memory device according to a second example of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 External terminal 11 Parallel serial conversion circuit 12 Write bus driver 13 Read bus latch circuit 14 Data amplifier 15 Memory cell array 16 Buffer 17 Capacitance fuse circuit 18 Redundant circuit 19 Redundant switching circuit 20 Address AL selector circuit 21 Read AL selector circuit 22, 22a Write WL selector circuit 23 Comparison circuit 24 Write data latch circuit 25 Address latch circuit 26 Comparison start timing circuits 31, 33, 35 Test mode selector circuit 32 Test mode write timing circuit 34 Test mode read timing circuits 40, 40a Timing adjustment unit AL Address capturing signal ALM AL-MRS (mode register setting) information signal CA1, CA2 COL (column) system address signal CLK Internal clock signal CS ratio Start signal DB Data bus signal DQ Data signal IOS Main I / O signal MODE Address take-in mode signal RA ROW system address signal RB Read bus signal RL Read latch signal RS Read signal WB Write bus signal WD Write data signal WL Write Latch signal WLM WL-MRS information signal WS Write signal

Claims (5)

A capacitor fuse circuit for repairing a defective cell is provided, and read data read from a memory cell by a read command in a normal operation mode can be read from an external terminal, and input from the external terminal by a write command in the normal operation mode A semiconductor memory device capable of writing write data to a memory cell,
A timing adjustment unit that is active in a test mode and performs timing adjustment so that read data read from a memory cell by the read command can be compared with expected value data input from the external terminal;
A comparison circuit for comparing the read data and the expected value data whose timing is adjusted by the timing adjustment unit;
An address latch circuit that latches the address of the memory cell as a capacitor fuse address if the comparison results in the comparison circuit do not match;
A capacitive fuse circuit for cutting a capacitive fuse element based on the latched capacitive fuse address;
A semiconductor memory device comprising:   2. The semiconductor memory device according to claim 1, wherein, in the test mode and the normal operation mode, the timing at which the read data is read from the memory cell by the read command is the same. The timing adjustment unit
A first latch circuit that latches the read data read from the memory cell by a read latch signal based on the read command;
A second latch circuit for latching expected value data input from the external terminal by a write latch signal based on the read command;
A timing circuit for providing the comparison circuit with a comparison start timing obtained by delaying the write latch signal;
Including
2. The semiconductor memory device according to claim 1, wherein the comparison circuit compares outputs of the first and second latch circuits according to the comparison start timing.   4. The semiconductor memory device according to claim 3, wherein the timing adjustment unit adjusts the timing of the write latch signal by giving a time delay corresponding to a write latency to the read latch signal in the test mode. .   In the test mode, the timing adjustment unit does not give a time delay corresponding to an additive latency to the read latch signal for the address signal for specifying the memory cell and the read data of the memory cell, and the read latch 4. The semiconductor memory device according to claim 3, wherein timing adjustment is performed without giving a time delay corresponding to the write latency to the signal.

Images