JP2008176038A - Display device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of preventing an error operation of level shift circuits with respect to the display device provided with the level shift circuits. <P>SOLUTION: A VSS power source line extended from a VSS terminal is branched in the middle, a branched first VSS power source line SL1 is extended clockwise along a display region 10 on an insulation substrate 1 and another branched second VSS power source line SL2 is extended counter-clockwise along the display region 10 on the insulation substrate 1. Further, a vertical scanning circuit 20 and the level shift circuits 50V, 51V, 52V, 53V for the vertical scanning circuit 20 are connected with the first VSS power source line SL1 and receive the supply of VSS, wherein the level shift circuits 50V, 51V, 52V, 53V are arranged on positions nearer to the VSS power source line than the vertical scanning circuit 20. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device that is mounted and used in an electronic device or the like having a display screen, and more particularly to a display device that includes a level shift circuit that shifts a level of a control signal.

  In general, in a liquid crystal display device, a horizontal scanning circuit and a vertical scanning circuit are built in a panel, and a control signal for controlling the operation of these scanning circuits is supplied from an IC provided outside the panel. . Therefore, a level shift circuit is provided in the panel in order to convert the signal level of the control signal output from the IC into a signal level suitable for operating these scanning circuits. In this case, the horizontal scanning circuit, the vertical scanning circuit, and the level shift circuit are supplied with power from the power supply line extending from the power supply terminal portion provided in the panel.

A liquid crystal display device including a level shift circuit is described in Patent Document 1.
JP 2004-163961 A

  However, as the panel becomes larger, the wiring length of the power supply line becomes longer, resulting in an increase in wiring resistance, and as the control signal becomes higher in frequency, the current consumption of each circuit increases, resulting in the power supply terminal of the power supply line. As the distance from the power source increases, the potential change of the power supply line (the potential drop of the high-level power supply line, the potential rise of the low-level power supply line) increases. As a result, a malfunction may occur in the level shift circuit in which the input / output characteristics fluctuate due to such a potential change of the power supply line.

  A display device according to the present invention includes a pixel region including a plurality of pixels arranged in a matrix on a substrate, and a vertical scan in the vertical direction of the pixel region arranged on the substrate based on a vertical scan control signal. A vertical scanning circuit for performing horizontal scanning in the horizontal direction of the pixel region based on a horizontal scanning control signal, and a vertical scanning circuit for performing vertical scanning on the substrate. A first level shift circuit for level shifting; a second level shift circuit disposed on the substrate for level shifting the horizontal scanning control signal; and disposed on the substrate, A power supply line for supplying power to a second level shift circuit, the power supply line branching into a first power supply line and a second power supply line and extending on the substrate, and the horizontal scanning circuit And the first label The first shift circuit is connected to the first power supply line, the first level shift circuit is arranged closer to the branch point of the power supply line than the horizontal scanning circuit, and the vertical scanning circuit and the second level shift circuit are The second level shift circuit is connected to the second power supply line, and is closer to the branch point than the vertical scanning circuit.

  According to the present invention, since the power supply line is branched and the level shift circuit is arranged close to the branch point, the change in potential of the power supply line due to the wiring resistance of the power supply line and the current flowing in the power supply line is suppressed, and the level shift circuit Can be prevented from malfunctioning.

  The display device of the present invention includes a pixel region including a plurality of pixels arranged in a matrix on the substrate, and a vertical direction of the pixel region based on the plurality of vertical scanning control signals. A vertical scanning circuit that performs vertical scanning, a horizontal scanning circuit that is disposed on the substrate and that performs horizontal scanning in the horizontal direction of the pixel region based on a plurality of horizontal scanning control signals, and is disposed on the substrate. A plurality of level shift circuits for level-shifting each of the plurality of vertical scanning control signals or the plurality of horizontal scanning control signals; and a plurality of power supply terminals provided on the substrate, extending on the substrate, A power supply line for supplying power to the level shift circuit, and the plurality of level shift circuits are disposed closer to the power supply terminal than the vertical scanning circuit or the horizontal scanning circuit and have a frequency A level shift circuit for level shifting a low vertical scanning control signal or a horizontal scanning control signal is disposed closer to the power supply terminal than a level shifting circuit for level shifting a high frequency vertical scanning control signal or horizontal scanning control signal. To do.

According to the present invention, the plurality of level shift circuits are arranged near the power supply terminal,
Among the multiple level shift circuits, the level shift circuit for level shifting a control signal with a high frequency consumes a large amount of current, so it is placed far from the power supply terminal, and the level shift circuit for level shifting a control signal with a low frequency is consumed. Since the current is small, disposing the power supply terminal far from the power supply terminal can minimize the potential change of the power supply line and prevent malfunction of each level shift circuit.

  According to the display device and the electronic apparatus of the present invention, it is possible to prevent the malfunction of the level shift circuit for level-shifting the control signals of the vertical scanning circuit and the horizontal scanning circuit, and to appropriately control these scanning circuits. Thereby, it can respond to the enlargement of a panel and the high frequency of a control signal.

  A liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view (layout diagram) of a liquid crystal display device mounted and used in an electronic device such as a mobile phone having a display screen and a digital still camera. A vertical scanning circuit 20 that generates a vertical scanning signal is disposed on an insulating substrate 1 such as a glass substrate adjacent to the display region 10 (that is, the pixel region) and along the vertical direction (Y direction). A horizontal scanning circuit 30 for generating a horizontal scanning signal and a negative power supply generating circuit 40 for generating a negative power supply potential are arranged along the direction).

  In the display region 10, a plurality of pixels 10 </ b> P are arranged in a matrix, and one pixel 10 </ b> P includes a pixel TFT 11 connected to the data line DL, a liquid crystal element 12 connected to the drain of the pixel TFT 11, and a storage capacitor 13. have. A gate line GL is connected to the gate of the pixel TFT 11. A data line DL is connected to the source of the pixel TFT 11. A gate signal for controlling the switching of the pixel TFT 11 is output from the vertical scanning circuit 20 to the gate line GL. A video signal is output to the data line DL according to the scanning signal from the horizontal scanning circuit 30.

  Further, level shift circuits 50V, 51V, 52V for level shifting the output enable signal ENB, the vertical clock CKV, the vertical start signal STV, and the vertical scanning direction switching signal CSV, which are vertical scanning control signals of the vertical scanning circuit 20, respectively. 53V is arranged. The vertical scanning control signal is input to corresponding terminals of the terminal group 1T formed along the end of the insulating substrate 1, and signal lines extending from these terminals are connected to the input ends of the corresponding level shift circuits. Yes.

  Further, level shift circuits 50H, 51H, and 52H are provided for level shifting the horizontal clock control signals of the horizontal scanning circuit 30, which are horizontal clocks CKH1 and CKH2, a horizontal start signal STH, and a horizontal scanning direction switching signal CSH. Yes. The horizontal scanning control signal is input to corresponding terminals of the terminal group 1T formed along the end of the insulating substrate 1, and signal lines extending from these terminals are connected to input terminals of the corresponding level shift circuit. Yes.

  The low level power supply potential of the vertical scanning circuit 20, the horizontal scanning circuit 30 and the negative power generation circuit 40 is VSS (0V), and the high level power supply potential of the vertical scanning circuit 20 is VVDD, the horizontal scanning circuit 30 and the negative power supply generation. The high level power supply potential of the circuit 40 is HVDD. On the other hand, the vertical scanning control signal and the horizontal scanning control signal are generated by an IC provided outside the insulating substrate 1 and change between VSS (0 V) and VDD. VDD is set to a value lower than VVDD and HVDD, for example, 3 V in order to reduce the power consumption of the IC. VVDD and HVDD are set to, for example, 8.5 V in order to guarantee circuit operation and to quickly write a target voltage to the pixel 10P.

  Therefore, the level shift circuit is provided to match the high level signal levels of the vertical scanning control signal and the horizontal scanning control signal to VVDD and HVDD. In the level shift circuits 50V, 51V, 52V, and 53V for the vertical scanning circuit 20, the high level power supply potential is set to VVDD, and the low level power supply potential is set to VSS. Further, the high level power supply potential of the level shift circuits 50H, 51H, and 52H for the horizontal scanning circuit 30 is set to HVDD, and the low level power supply potential is set to VSS.

  VVDD, HVDD, and VSS are input from the VVDD terminal, HVDD terminal, and VSS terminal in the terminal group 1T. The first feature of the present invention resides in the layout of the VSS power supply line and the circuit. That is, the VSS power supply line extending from the VSS terminal is branched in the middle, and the branched first VSS power supply line SL1 extends on the insulating substrate 1 along the display region 10 in the clockwise direction. That is, the first VSS power supply line SL1 starts from the branch point P, extends in the direction of the vertical scanning circuit 20 along the display region 10, bends at a right angle, extends into the vertical scanning circuit 20, and extends vertically. Terminate at the end of the scanning circuit 20.

  Further, another branched second VSS power supply line SL2 extends on the insulating substrate 1 along the display region 10 in a counterclockwise direction. That is, the second VSS power supply line SL2 starts from the branch point P, extends in the direction of the horizontal scanning circuit 30 so as to surround the display area 10, and bends at a right angle to form the horizontal scanning circuit 30 and the negative power supply generation circuit 40. And terminates at the end of the negative power supply generation circuit 40.

  The vertical scanning circuit 20 and the level shift circuits 50V, 51V, 52V, 53V for the vertical scanning circuit 20 are connected to the first VSS power supply line SL1 and supplied with VSS, and the level shift circuits 50V, 51V, 52V and 53V are arranged near the branch point P of the VSS power supply line from the vertical scanning circuit 20. That is, the position of each connection point between the level shift circuits 50V, 51V, 52V, 53V and the first VSS power supply line SL1 is closer to the branch point P than the connection point between the vertical scanning circuit 20 and the first VSS power supply line SL1. .

  Further, the horizontal scanning circuit 30, the negative power supply generation circuit 40, and the level shift circuits 50H, 51H, and 52H for the horizontal scanning circuit 30 are connected to the second VSS power supply line SL2 and supplied with VSS to receive the level shift circuit. 50H, 51H, and 52H are arranged near the branch point P of the VSS power supply line from the horizontal scanning circuit 30 and the negative power supply generation circuit 40. That is, the position of each connection point between the level shift circuits 50H, 51H, 52H and the second VSS power supply line SL2 branches from the connection point between the horizontal scanning circuit 30, the negative power supply generation circuit 40 and the second VSS power supply line SL2. Close to point P.

  The VVDD terminal and the HVDD terminal are provided separately, and the VVDD power supply line VL extending from the VVDD terminal extends clockwise on the insulating substrate 1 along the first VSS power supply line SL1 and extends from the HVDD terminal. The HVDD power line HL extends counterclockwise on the insulating substrate 1 along the second VSS power line SL2.

  According to such a layout, fluctuations in the input / output characteristics of the level shift circuit are minimized by minimizing the drop in the high-level power supply potential VVDD and HVDD supplied to the level shift circuit and the rise in the low-level power supply potential VSS. It is possible to suppress the malfunction of the level shift circuit. The reason will be described using the model circuit of FIG. Assuming that the consumption currents I1, I2, and I3 flow in the circuit 1, circuit 2, and circuit 3, respectively, the wiring resistances R1a, R2a, and R3a of the VDD wiring cause a drop in the high-level power supply potential VDD, and the wiring resistance R1b of the VSS wiring. , R2b, and R3b increase the low-level power supply potential VSS. When the consumption current I1 of the circuit 1 is large, changes in VDD and VSS in the circuit 2 and the circuit 3 far from the VDD terminal and the VSS terminal become large. On the other hand, if the current consumption I1 of the circuit 1 is small, changes in VDD and VSS in the circuits 1, 2, and 3 can be minimized. The level shift circuit consumes less current than the vertical scanning circuit 20, the horizontal scanning circuit 30, and the negative power supply generation circuit 40, and the input / output characteristics are affected by changes in the power supply potential, so that the operation margin tends to be small. Therefore, in the present invention, the level shift circuit is arranged near the power supply terminal.

  Further, for the level shift circuits 50V, 51V, 52V, 50H and 51H, the respective outputs are applied, and buffer circuits 60V and 61V for shaping the output waveform (to make the waveform dull due to the wiring resistance steep). 62V, 60H, 61H are provided. The buffer circuits 60V, 61V and 62V are connected to the VVDD power supply line VL and the first VSS power supply line SL1, and are arranged between the level shift circuits 50V, 51V and 52V and the vertical scanning circuit 20. The buffer circuits 60H and 61H are connected to the HVDD power supply line HL and the second VSS power supply line SL2, and are disposed between the level shift circuits 50H and 51H and the horizontal scanning circuit 30.

  The level shift circuits 53V and 52H are circuits for level-shifting the vertical scanning direction switching signal CSV and the horizontal scanning direction switching signal CSH, respectively, and since these signals are DC signals, no buffer circuit is provided.

  The second feature of the present invention is the arrangement relationship of a plurality of level shift circuits and a plurality of buffer circuits. For the level shift circuits 50H, 51H, 52H of the horizontal scanning system, a level shift circuit 52H for level shifting the horizontal scanning direction switching signal CSH is disposed closest to the branch point P, and a level shift circuit for level shifting the horizontal start signal STH. 51H is arranged next to the branch point P, and the level shift circuit 50H for level shifting the horizontal clocks CKH1 and CKH2 is arranged farthest from the branch point P.

  Since the horizontal scanning direction switching signal CSH is a DC signal, the consumption current of the level shift circuit 52H is the smallest among the three level shift circuits 50H, 51H, and 52H. The cycle of the horizontal start signal STH is one horizontal period, and the current consumption of the level shift circuit 51H and the buffer circuit 61H is the next smallest. Since the horizontal clocks CKH1 and CKH2 have a period of several hundred nanoseconds and have the highest frequency, the current consumption of the level shift circuit 50H and the buffer circuit 60H is the largest.

  According to such a layout, on the basis of the principle explained in the model circuit of FIG. 2, the drop in the high level power supply potential VVDD, HVDD supplied to each level shift circuit 50H, 51H, 52H, the low level power supply potential VSS. The rise can be minimized, the fluctuation of the input / output characteristics of each level shift circuit can be suppressed, and the malfunction of each level shift circuit can be prevented.

  For the same reason, for the level shift circuits 50V, 51V, 52V and 53V in the vertical scanning system, the level shift circuit 53V for level shifting the vertical scanning direction switching signal CSV is arranged closest to the branch point P, and the vertical start signal STV Next, a level shift circuit 52V for level shifting is placed near the branch point P, a level shift circuit 51V for level shifting the vertical clock CKV is placed next to the branch point P, and the output enable signal ENB is level shifted. The level shift circuit 50V is arranged farthest from the branch point P.

  Since the vertical scanning direction switching signal CSV is a DC signal, the current consumption of the level shift circuit 53V is the smallest among the four level shift circuits 50V, 51V, 52V, and 53V. The cycle of the vertical start signal STV is one vertical period, and the current consumption of the level shift circuit 52V and the buffer circuit 62V is the next smallest. The cycle of the vertical clock CKV is two horizontal periods, and the current consumption of the level shift circuit 51V and the buffer circuit 61V is the next smallest. The cycle of the output enable signal ENB is one horizontal period, and the current consumption of the level shift circuit 50V and the buffer circuit 60V is the largest.

  In FIG. 1, the level shift circuit and the corresponding buffer circuit are arranged close to each other. However, as shown in FIG. 3, a plurality of level shift circuits are arranged closer to the branch point P than the plurality of buffer circuits. May be. That is, the horizontal scanning buffer circuits 60H and 61H are arranged farther from the branch point P than the level shift circuits 50H, 51H and 52H. As a result, the drop in the high-level power supply potentials VVDD and HVDD and the rise in the low-level power supply potential VSS supplied to the level shift circuits 50H, 51H, and 52H can be further reduced.

  Similarly, the vertical scanning buffer circuits 60V, 61V, and 62V are arranged farther from the branch point P than the level shift circuits 50V, 51V, 52V, and 53V.

  FIG. 4 is a circuit diagram of the level shift circuit and the buffer circuit. The input section of the level shift circuit is composed of a PMOS 51 to which an input signal Vin is applied, and an NMOS 52 to which VVDD or HVDD is applied to the gate, connected in series with the PMOS 51. The NMOS 52 functions as a load resistance. The output part of the level shift circuit is composed of a PMOS 53 having a connection node A between the PMOS 51 and the NMOS 52 connected to the gate, connected in series with the PMOS 53, an NMOS 54 having VVDD or HVDD applied to the gate, and a two-stage inverter 55. Yes. An input signal Vin is applied to the source of the NMOS 54. Further, a buffer circuit composed of four stages of inverters 61 is provided at the output terminal of the level shift circuit. The buffer circuit is not limited to an inverter, and may be formed by another amplifier, for example, an operational amplifier.

  In this level shift circuit, the input signal Vin is assumed to change between VSS and VDD. VDD is smaller than VVDD and HVDD. Here, VSS = 0V, VDD = 3V, VVDD, and HVDD = 8.5V will be described. The potential of the connection node A becomes an analog potential of an intermediate level between 0V and 8.5V according to the level of the input signal Vin. The potential of the connection node B changes to near 0V and close to 8.5V. The two-stage inverter 55 causes the output signal Vout of the level shift circuit to fully swing between 0V to 8.5V as shown in FIG. Therefore, according to the level shift circuit, the input signal Vin of 0V to 3V can be converted into the output signal Vout of 0V to 8.5V. Usually, the threshold value of the level shift circuit is set to 1.5 V which is the middle of the input signal Vin.

  However, when VSS rises, the potential of the connection node A rises and the threshold value of the level shift circuit also rises. Further, when VVDD and HVDD are lowered, the potential of the connection node A is lowered, and the threshold value of the level shift circuit is also lowered. That is, the input / output characteristics of the level shift circuit change. As a result, the operation margin of the level shift circuit is lowered, and there is a risk of causing a level shift malfunction. Therefore, by adopting the above-described layout of the present invention, an increase in VSS, a decrease in VVDD, and HVDD are suppressed, and a malfunction of level shift is prevented.

  4 is applied to the level shift circuits 50V, 51V, 52V, 53V, 51H, and 52H. The level shift circuit 50H is a circuit that simultaneously shifts the level of the horizontal clocks CKH1 and CKH2 (CKH2 is an inverted clock of CKH1), and a dual-phase input / double-phase output type level shift circuit is used. This is the same as the circuit 4. Further, the level shift circuit is not limited to the circuit of FIG. 4 and various circuit configurations are known. However, the level shift circuit is a type of level shift circuit in which the input / output characteristics are changed by the rise of VSS and the fall of VVDD and HVDD. If it exists, it becomes an application object of this invention and can obtain the effect of this invention.

  FIG. 6 is a circuit diagram of the vertical scanning circuit 20. The plurality of vertical shift register units SRV1, SRV2, SRV3,... Sequentially transfer the vertical start signal STV based on the vertical clock CKV and its inverted clock. The plurality of vertical shift register units SRV1, SRV2, SRV3,... Are supplied with a high level power supply potential VVDD from the VVDD power supply line VL, and supplied with a low level power supply potential VSS from the first VSS power supply line VS1. ing. The scanning direction of the vertical scanning circuit 20, that is, the direction in which the vertical start signal STV is transferred is switched according to the vertical scanning switching signal CSV.

  In addition, a NAND circuit 21 is provided which takes a logical product of outputs of two adjacent vertical shift register units, for example, an output of the vertical shift register unit SRV1, an output of the vertical shift register unit SRV2, and an output enable signal ENB. The output enable signal ENB is a signal for preventing overlap between gate signals output to the gate line GL and eliminating mutual interference of these signals. The output signal of the NAND circuit 21 is level-converted by the level shifter circuit LS1 so as to change between VVDD and VBB, and is further output as a gate signal to the gate line GL through the inverter INV1. VBB is a negative power supply potential generated by the negative power supply generation circuit 40.

  Similarly, a NAND circuit 22 that performs a logical product of the output of the vertical shift register unit SRV2, the output of the vertical shift register unit SRV3, and the output enable signal ENB is provided. The output signal of the NAND circuit 22 is level-converted by the level shifter circuit LS2 so as to change between VVDD and VBB, and is further output to the gate line GL through the inverter INV2.

  FIG. 7 is a circuit diagram of the horizontal scanning circuit 30. The plurality of horizontal shift register units SRH1, SRH2, SRH3,... Sequentially transfer the horizontal start signal STH based on the horizontal clocks CKH1, CKH2. A plurality of horizontal shift register units SRH1, SRH2, SRH3,... Are supplied with a high level power supply potential HVDD from the HVDD power supply line HL, and supplied with a low level power supply potential VSS from the second VSS power supply line VS2. ing. The scanning direction of the horizontal scanning circuit 30, that is, the direction in which the horizontal start signal STH is transferred is switched according to the horizontal scanning switching signal CSH.

The output signals of the horizontal shift register units SRH1, SRH2, SRH3,... Are applied to the gates of the corresponding MOS switches 31, 32, 33,. The video signal Vsig is applied to the drains of the MOS switches 31, 32, 33,. The MOS switches 31, 32, 33,... Are sequentially turned on in accordance with the output signals of the horizontal shift register units SRH1, SRH2, SRH3, etc., and the video signal Vsig is turned on by the MOS switches 31, 32, 33,. .. Is output to the corresponding drain line DL.

  In the above embodiment, the VSS power supply line that supplies the low-level power supply potential is branched. However, the power supply line that supplies the high-level power supply potential may be branched. In the above embodiment, the liquid crystal display device has been described as an example. However, the present invention is widely applied to other display devices including a level shift circuit that shifts the level of the scanning control signal, for example, an organic electroluminescence display device. Can be applied.

1 is a first plan view showing a liquid crystal display device according to an embodiment of the present invention. It is a model circuit diagram of a liquid crystal display device. It is a 2nd top view which shows the liquid crystal display device which concerns on embodiment of this invention. It is a circuit diagram which shows a level shift circuit and a buffer circuit. It is a figure which shows the input / output characteristic of a level shift circuit. It is a circuit diagram of a vertical scanning circuit. It is a circuit diagram of a horizontal scanning circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating substrate 10 Display area 10P Pixel 20 Vertical scanning circuit 30 Horizontal scanning circuit 40 Negative power supply generation circuit 50V-53V, 50H-52H Level shift circuit
60V to 62V, 60H, 61H Buffer circuit VS1 First VSS power supply line VS2 Second VSS power supply line VL VVDD electric wire HL HVDD power supply line
GL gate line DL drain line

Claims (7)

A pixel region composed of a plurality of pixels arranged in a matrix on the substrate;
A vertical scanning circuit disposed on the substrate and performing vertical scanning in a vertical direction of the pixel region based on a vertical scanning control signal;
A horizontal scanning circuit disposed on the substrate and performing horizontal scanning in the horizontal direction of the pixel region based on a horizontal scanning control signal;
A first level shift circuit disposed on the substrate for level shifting the vertical scanning control signal;
A second level shift circuit disposed on the substrate for level shifting the horizontal scanning control signal;
A power line disposed on the substrate and supplying power to the first and second level shift circuits,
The power supply line branches into a first power supply line and a second power supply line and extends on the substrate,
The horizontal scanning circuit and the first level shift circuit are connected to the first power supply line,
The first level shift circuit is disposed closer to the branch point of the power line than the horizontal scanning circuit,
The vertical scanning circuit and the second level shift circuit are connected to the second power supply line,
The display device, wherein the second level shift circuit is arranged closer to the branch point than the vertical scanning circuit. A first buffer circuit to which an output of the first level shift circuit is applied and connected to the first power supply line;
A second buffer circuit to which an output of the second level shift circuit is applied and connected to the second power supply line,
The first buffer circuit is disposed between the first level shift circuit and the vertical scanning circuit, and the second buffer circuit is disposed between the second level shift circuit and the horizontal scanning circuit. The display device according to claim 1. 3. The display device according to claim 1, wherein the first and second level shift circuits are level shift circuits whose input / output characteristics change according to a change in power supply potential. A pixel region composed of a plurality of pixels arranged in a matrix on the substrate;
A vertical scanning circuit disposed on the substrate and performing vertical scanning in a vertical direction of the pixel region based on a plurality of vertical scanning control signals;
A horizontal scanning circuit disposed on the substrate and performing horizontal scanning in a horizontal direction of the pixel region based on a plurality of horizontal scanning control signals;
A plurality of level shift circuits disposed on the substrate for level shifting the plurality of vertical scanning control signals or the plurality of horizontal scanning control signals;
A power line extending from the power supply terminal provided on the substrate and supplying power to the plurality of level shift circuits, and
The plurality of level shift circuits are arranged closer to the power supply terminal than the vertical scanning circuit or the horizontal scanning circuit, and a level shift circuit for level shifting a low frequency vertical scanning control signal or horizontal scanning control signal has a high frequency. A display device, wherein the display device is disposed closer to the power supply terminal than a level shift circuit for level-shifting a vertical scanning control signal or a horizontal scanning control signal. An output of the level shift circuit is applied, and includes a buffer circuit connected to the power supply line, the buffer circuit between the level shift circuit and the vertical scanning circuit,
The display device according to claim 4, wherein the display device is disposed between the level shift circuit and the horizontal scanning circuit. 6. The display device according to claim 4, wherein the level shift circuit is a level shift circuit whose input / output characteristics change according to a change in power supply potential. An electronic apparatus comprising the display device according to claim 1.

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