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JP2008171963A - Semiconductor chip cooling structure - Google Patents

Semiconductor chip cooling structure Download PDF

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Publication number
JP2008171963A
JP2008171963A JP2007002943A JP2007002943A JP2008171963A JP 2008171963 A JP2008171963 A JP 2008171963A JP 2007002943 A JP2007002943 A JP 2007002943A JP 2007002943 A JP2007002943 A JP 2007002943A JP 2008171963 A JP2008171963 A JP 2008171963A
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JP
Japan
Prior art keywords
semiconductor chip
heat
heat sink
heat dissipation
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007002943A
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Japanese (ja)
Inventor
Shingo Yamamoto
愼吾 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2007002943A priority Critical patent/JP2008171963A/en
Publication of JP2008171963A publication Critical patent/JP2008171963A/en
Pending legal-status Critical Current

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    • H10W72/884
    • H10W90/756

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

【課題】半導体チップがモールド樹脂で封止された半導体パッケージにおいて、半導体パッケージと冷却機構が一体となった放熱効果の高い半導体チップ冷却構造を提供する。
【解決手段】モールド樹脂4内部に熱伝導性のよい材質で形成した放熱板2、3の2枚で半導体チップ1を挟み込みように前記モールド樹脂内部に配置し、前記放熱板とプリント配線基板10を接続させる構造を有し、半導体チップの両面から前記放熱板を介してプリント配線基板内に放熱することにより、放熱効果の高い半導体チップ冷却構造を実現出来る。
【選択図】図1
In a semiconductor package in which a semiconductor chip is sealed with a mold resin, a semiconductor chip cooling structure having a high heat dissipation effect in which a semiconductor package and a cooling mechanism are integrated is provided.
A heat dissipation plate and a heat radiation plate formed of a material having good thermal conductivity are disposed inside the mold resin so that the semiconductor chip is sandwiched between the heat dissipation plate and the printed wiring board. The semiconductor chip cooling structure having a high heat dissipation effect can be realized by dissipating heat from both sides of the semiconductor chip into the printed wiring board through the heat dissipation plate.
[Selection] Figure 1

Description

本発明は半導体チップをモールド樹脂で封止した半導体パッケージにおいて、前記半導
体チップを効率良く冷却させることを可能とし、冷却機構と半導体パッケージが一体とな
った半導体チップ冷却構造に関するものである。
The present invention relates to a semiconductor chip cooling structure in which a semiconductor chip is sealed with a mold resin, the semiconductor chip can be efficiently cooled, and a cooling mechanism and the semiconductor package are integrated.

近年、半導体装置の高速化および高機能化等が進み、半導体チップの発熱量が増大する
傾向にある。前記傾向により、半導体チップの冷却方法についても様々な方法が提案され
ており、主な冷却方法としては、プリント配線基板上に搭載された半導体装置の表面に金
属製の放熱フィンを固定させ、前記半導体装置で発生した熱を前記放熱フィンに伝えて放
熱させる方法が用いられる。
In recent years, semiconductor devices have been increased in speed and functionality, and the amount of heat generated by semiconductor chips tends to increase. Due to the above-mentioned tendency, various methods for cooling a semiconductor chip have been proposed. As a main cooling method, a metal heat dissipating fin is fixed to the surface of a semiconductor device mounted on a printed wiring board. A method is used in which heat generated in the semiconductor device is transmitted to the heat dissipating fins to dissipate heat.

また、前記放熱フィンを使用しない半導体チップの冷却構造として、図5の断面図に示
す半導体パッケージ内部に放熱板を配置し、前記半導体チップの裏面と前記放熱板を接触
させ、前記放熱板を介してモールド外部に自然空冷にて放熱させる半導体パッケージ構造
や図6の断面図に示す半導体パッケージ内部に配置した放熱板をプリント配線基板に接続
することでプリント配線基板内に放熱させる半導体パッケージ構造も存在する。
Further, as a cooling structure of the semiconductor chip that does not use the heat radiating fins, a heat radiating plate is disposed inside the semiconductor package shown in the cross-sectional view of FIG. 5, the back surface of the semiconductor chip and the heat radiating plate are brought into contact, and the heat radiating plate is interposed. There is also a semiconductor package structure that radiates heat to the outside of the mold by natural air cooling and a semiconductor package structure that dissipates heat in the printed wiring board by connecting the heat sink placed inside the semiconductor package shown in the cross-sectional view of FIG. To do.

特開平4−11758号公報JP-A-4-11758

上述のような従来技術の場合、発熱量の大きな半導体装置を使用した電子機器では、前
記半導体装置を冷却するための放熱フィンやヒートシンク等の別体の冷却機構を用いる場
合が多い。放熱フィン等を使用することで確かに放熱性は向上するが、前記放熱フィンは
表面積を増大し放熱効率を上げるために縦長の溝を設けた形状が多く、大きいものでは半
導体装置の表面から5cm程度、高さ方向に増大することになり、年々進む電子機器の小
型化に対して障害になるという欠点が存在する。また、別体の冷却機構を設けるため、作
業工程やコストアップ増大の要因となる。
In the case of the conventional technology as described above, in an electronic device using a semiconductor device having a large calorific value, a separate cooling mechanism such as a radiating fin or a heat sink for cooling the semiconductor device is often used. Although the heat radiation performance is certainly improved by using heat radiation fins, etc., the heat radiation fins are often provided with vertically elongated grooves in order to increase the surface area and increase the heat radiation efficiency. However, there is a drawback that it increases in the height direction and becomes an obstacle to downsizing of electronic equipment that is progressing year by year. In addition, since a separate cooling mechanism is provided, it becomes a factor in increasing work processes and costs.

このような問題を解決するため、特開平4−11758号公報の半導体パッケージと冷
却機構が一体となった構造が開示されており、傘型の放熱ブロックを半導体チップの表面
に直付けし、前記半導体チップ表面で発生した熱が前記放熱ブロックに伝わりモールド樹
脂外部に放熱することを特徴とする。確かに放熱フィンなどの別体の冷却機構を設ける必
要がない構造となっているが、モールド樹脂外部に露出した前記冷却ブロックの自然空冷
であり、放熱媒体となる空気の熱抵抗が高いため放熱効果は低い。
In order to solve such a problem, a structure in which a semiconductor package and a cooling mechanism of Japanese Patent Laid-Open No. 4-11758 are integrated is disclosed, and an umbrella-shaped heat dissipation block is directly attached to the surface of a semiconductor chip, The heat generated on the surface of the semiconductor chip is transmitted to the heat dissipation block and dissipated outside the mold resin. Although it is a structure that does not necessarily require a separate cooling mechanism such as a heat radiating fin, it is a natural air cooling of the cooling block exposed to the outside of the mold resin, and the heat resistance of the air that becomes the heat radiating medium is high, so it dissipates heat. The effect is low.

また、図6の放熱板をプリント配線基板に接続する構造においては、半導体チップ裏面
から放熱板に伝熱するため半導体チップの発熱部位である回路面で発生した熱を直接伝え
ることが出来ない構造である。
Further, in the structure in which the heat sink of FIG. 6 is connected to the printed wiring board, heat is transferred from the back surface of the semiconductor chip to the heat sink, so that the heat generated on the circuit surface that is the heat generating portion of the semiconductor chip cannot be directly transferred. It is.

本発明では上記した問題を解決し、放熱フィン等の別体の冷却機構を使用せず、モール
ド樹脂で封止された半導体チップを効率良く冷却させる半導体チップ冷却構造を提供する
ものである。
The present invention solves the above-described problems and provides a semiconductor chip cooling structure that efficiently cools a semiconductor chip sealed with a mold resin without using a separate cooling mechanism such as a heat radiating fin.

上記した課題を解決するためには、熱抵抗の低い媒体へ伝熱し放熱させることが重要で
ある。自然空冷の場合は熱抵抗の高い空気が放熱媒体となるため、発熱量の大きな半導体
チップの冷却は困難である。また、半導体チップの発熱部位から直接伝熱させることで放
熱効果を向上させることが出来る。そこで半導体チップをモールド樹脂で封止した半導体
パッケージにおいて、熱伝導性のよい材質で形成した放熱板2枚を前記半導体チップの両
面に接触するように前記モールド樹脂内部に配置し、前記2枚の放熱板をプリント配線基
板と接続する構造を有し、つまりは前記半導体チップを2枚の放熱板で挟み込み前記半導
体チップの両面から前記放熱板を介して前記プリント配線基板内に放熱させる。
In order to solve the above-described problems, it is important to transfer heat to a medium with low thermal resistance to dissipate heat. In the case of natural air cooling, air with high thermal resistance serves as a heat dissipation medium, so it is difficult to cool a semiconductor chip that generates a large amount of heat. Moreover, the heat dissipation effect can be improved by transferring heat directly from the heat generating portion of the semiconductor chip. Therefore, in a semiconductor package in which a semiconductor chip is sealed with a mold resin, two heat radiating plates formed of a material having good thermal conductivity are arranged inside the mold resin so as to be in contact with both surfaces of the semiconductor chip, and the two sheets A heat sink is connected to the printed wiring board, that is, the semiconductor chip is sandwiched between two heat sinks, and heat is radiated from both sides of the semiconductor chip through the heat sink into the printed wiring board.

本発明は2枚の放熱板を用いて半導体チップを挟み込む構造を有し、半導体チップの両
面から伝熱させるため、放熱効果を向上することが可能である。また、半導体パッケージ
と冷却機構である放熱板が一体化した構造のため、放熱フィンやヒートシンク等の冷却機
構を別途設ける必要はない。
Since the present invention has a structure in which a semiconductor chip is sandwiched between two heat sinks and heat is transferred from both sides of the semiconductor chip, the heat dissipation effect can be improved. Further, since the semiconductor package and the heat radiating plate as a cooling mechanism are integrated, it is not necessary to separately provide a cooling mechanism such as a heat radiating fin or a heat sink.

以下に本発明の実施の形態を詳細に説明する。図1は本発明の断面構造図を示しており
、熱伝導性のよい材質例えば銅等で形成した放熱板Aおよび放熱板Bで半導体チップ1を
挟み込む構造を有す。さらに詳しくは、半導体チップ1の回路面に絶縁シート11を介し
て放熱板Aを接触させ、半導体チップ1の裏面には放熱板Bをダイアタッチ材5例えば銀
ペースト等を用いて固着し、半導体チップ1の回路面からワイヤーボンディング6を介し
てリードフレーム6に接続させ、モールド樹脂4例えばエポキシ樹脂等で密閉する構造か
らなる。さらに放熱板Aおよび放熱板Bの接続用として、プリント配線基板10上にパッ
ト8を設け、放熱板Aおよび放熱板Bとパット8をリフローにてはんだ接続する構造から
なる。
Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 shows a cross-sectional structure diagram of the present invention, which has a structure in which a semiconductor chip 1 is sandwiched between a heat radiating plate A and a heat radiating plate B formed of a material having good thermal conductivity, such as copper. More specifically, the heat sink A is brought into contact with the circuit surface of the semiconductor chip 1 via the insulating sheet 11, and the heat sink B is fixed to the back surface of the semiconductor chip 1 using a die attach material 5 such as silver paste. The structure is such that the circuit surface of the chip 1 is connected to the lead frame 6 through the wire bonding 6 and sealed with a mold resin 4 such as an epoxy resin. Further, for connecting the heat sink A and the heat sink B, a pad 8 is provided on the printed wiring board 10, and the heat sink A and the heat sink B and the pad 8 are connected by soldering by reflow.

図2に示す放熱板Aおよび放熱板Bの斜視図を用いさらに詳しく説明すると、放熱板A
にはリードフレーム6の形状と酷似した湾曲形状を有する端子をリードフレーム6と平行
となるように少なくとも2辺形成する。この際、放熱板のはんだ接続部Lの表面積を増大
することで放熱効果も向上する。また、放熱板Aのはんだ接続部とリードフレーム6のは
んだ接続部の高さが相違した場合、プリント配線基板10への搭載時に放熱板Aもしくは
リードフレーム6のどちらか一方がプリント配線基板10のパット8から浮いた状態とな
る可能性があるため、放熱板Aのはんだ接続部とリードフレーム6のはんだ接続部は同じ
高さで揃えるとよい。放熱板Bは半導体チップ1を搭載するために半導体チップ1よりも
一回り大きい面積を持たせ、半導体チップ1裏面を全て接触させる。また、放熱板Aおよ
び放熱板Bにはんだ付け性のよい金属めっき例えば錫系のめっきを施すことにより、放熱
板Aおよび放熱板Bとプリント配線基板10上に形成されたパット8の接続強度が向上し
放熱効果も向上する。
The heat sink A and the heat sink B shown in FIG.
In this case, at least two sides having a curved shape very similar to the shape of the lead frame 6 are formed so as to be parallel to the lead frame 6. At this time, the heat dissipation effect is also improved by increasing the surface area of the solder connection portion L of the heat dissipation plate. In addition, when the solder connection portions of the heat sink A and the solder connection portions of the lead frame 6 are different, either the heat sink A or the lead frame 6 is mounted on the printed wiring board 10 when mounted on the printed wiring board 10. Since there is a possibility of floating from the pad 8, it is preferable that the solder connection portion of the heat sink A and the solder connection portion of the lead frame 6 are aligned at the same height. In order to mount the semiconductor chip 1, the heat sink B has a larger area than the semiconductor chip 1, and contacts the entire back surface of the semiconductor chip 1. Further, by applying metal plating with good solderability to the heat sink A and the heat sink B, for example, tin plating, the connection strength between the heat sink A and the heat sink B and the pad 8 formed on the printed wiring board 10 is increased. The heat dissipation effect is improved.

本発明の伝熱経路は放熱板Aを通る経路と放熱板Bを通る経路が存在し、放熱板Aを通
る経路は半導体チップ1で発生した熱が絶縁シート11を介して放熱板Aに伝わり放熱板
Aからプリント配線基板10へ放熱される経路を有す。また、放熱板Bを通る経路は半導
体チップ1で発生した熱がダイアタッチ材5を介して放熱板Bに伝わり放熱板Bからプリ
ント配線基板10へ放熱される伝熱経路を有し、半導体チップの両面から放熱することで
放熱効果の向上を図ることが出来る。
The heat transfer path of the present invention includes a path that passes through the heat sink A and a path that passes through the heat sink B. In the path that passes through the heat sink A, heat generated in the semiconductor chip 1 is transferred to the heat sink A via the insulating sheet 11. There is a path for radiating heat from the heat sink A to the printed circuit board 10. The path passing through the heat sink B has a heat transfer path through which heat generated in the semiconductor chip 1 is transferred to the heat sink B via the die attach material 5 and radiated from the heat sink B to the printed wiring board 10. The heat dissipation effect can be improved by dissipating heat from both sides.

本発明においては、半導体チップの冷却機構と半導体パッケージを一体化した構造を有
しており、本発明を用いた半導体装置では前記半導体装置をプリント配線基板10に搭載
することで、半導体チップ1の冷却機構も備えることとなる。さらに詳しくは、半導体チ
ップ1の放熱媒体となる放熱板Aおよび放熱板Bも半導体装置をプリント配線基板10に
搭載すると同時にはんだ接続を行えるため、別途、放熱板Aおよび放熱板Bをはんだ接続
させる工程を追加する必要はない。
The present invention has a structure in which a semiconductor chip cooling mechanism and a semiconductor package are integrated. In a semiconductor device using the present invention, the semiconductor device is mounted on a printed wiring board 10 so that the semiconductor chip 1 A cooling mechanism is also provided. More specifically, since the heat sink A and the heat sink B serving as the heat dissipation medium of the semiconductor chip 1 can be soldered simultaneously with the mounting of the semiconductor device on the printed wiring board 10, the heat sink A and the heat sink B are separately soldered. There is no need to add a process.

図3では、放熱板Aに2辺の端子形状部を形成した例を示すが、図4に示すように、放
熱板Aの端子形状部を4辺形成することで、さらに放熱効果の向上を図ることが可能であ
る。
Although FIG. 3 shows an example in which the terminal shape portion of two sides is formed on the heat sink A, as shown in FIG. 4, the heat dissipation effect is further improved by forming four terminal shape portions of the heat sink A. It is possible to plan.

上記実施例では図3および図4に示す放熱板Aの形状を紹介したが、放熱板Aに端子形
状を形成しプリント基板10と接続させる構造であればモールド樹脂4をすべて覆うよう
な形状でもよい。
In the above embodiment, the shape of the heat sink A shown in FIG. 3 and FIG. 4 was introduced. However, if the heat sink A is formed to have a terminal shape and connected to the printed circuit board 10, the shape may cover all the mold resin 4. Good.

また、実施例1にて放熱板とプリント配線基板の接続方法にはんだ付けを紹介したが、
放熱板で半導体チップを挟み込み半導体チップの両面から放熱させる構造であれば、プリ
ント配線基板との接続は熱伝導性のよい接着剤等でも代用可能である。
In addition, soldering was introduced in the connection method between the heat sink and the printed wiring board in Example 1,
If the structure is such that the semiconductor chip is sandwiched between the heat sinks and the heat is dissipated from both sides of the semiconductor chip, the connection with the printed wiring board can be replaced with an adhesive having good thermal conductivity.

実施例1の半導体チップ冷却構造断面図。1 is a cross-sectional view of a semiconductor chip cooling structure according to Embodiment 1. 放熱板Aおよび放熱板Bの斜視図。The perspective view of the heat sink A and the heat sink B. FIG. 2辺から放熱する場合の実施例1全体斜視図。1 is an overall perspective view of Example 1 when heat is radiated from two sides. FIG. 4辺から放熱する場合の実施例1全体斜視図。FIG. 4 is an overall perspective view of the first embodiment when heat is radiated from four sides. 従来の半導体チップ冷却構造断面図(1)。Sectional drawing (1) of the conventional semiconductor chip cooling structure. 従来の半導体チップ冷却構造断面図(2)。Sectional drawing (2) of the conventional semiconductor chip cooling structure.

符号の説明Explanation of symbols

1…半導体チップ、2…放熱板A、3…放熱板B、4…モールド樹脂、5…ダイアタッ
チ材、6…リードフレーム、7…ワイヤーボンディング、8…パット、9…はんだ材、10…プリント配線基板、11…絶縁シート、12…放熱板。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Heat sink A, 3 ... Heat sink B, 4 ... Mold resin, 5 ... Die attach material, 6 ... Lead frame, 7 ... Wire bonding, 8 ... Pad, 9 ... Solder material, 10 ... Print Wiring board, 11 ... insulating sheet, 12 ... heat sink.

Claims (3)

半導体チップをモールド樹脂で封止した半導体パッケージにおいて、熱伝導性のよい材
質で形成した2枚の放熱板で前記半導体チップを挟み込むように前記モールド樹脂内部に
配置し、前記放熱板とプリント配線基板を接続することを特徴とする半導体パッケージ構
造。
In a semiconductor package in which a semiconductor chip is sealed with a mold resin, the heat dissipation plate and the printed wiring board are arranged inside the mold resin so that the semiconductor chip is sandwiched between two heat dissipation plates formed of a material having good thermal conductivity. A semiconductor package structure characterized by connecting the two.
請求項1記載の構造を有す半導体パッケージ。   A semiconductor package having the structure according to claim 1. 請求項1記載の構造を有し、放熱板で半導体チップを挟み込むことで前記半導体チップ
の両面から前記放熱板を介してプリント配線基板内に放熱させることを特徴とする冷却機
構と半導体パッケージが一体となった半導体チップ冷却構造。
A cooling mechanism and a semiconductor package having the structure according to claim 1, wherein the semiconductor chip is sandwiched between heat sinks to dissipate heat from both sides of the semiconductor chip into the printed wiring board through the heat sink. The semiconductor chip cooling structure.
JP2007002943A 2007-01-11 2007-01-11 Semiconductor chip cooling structure Pending JP2008171963A (en)

Priority Applications (1)

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Publication Number Publication Date
JP2008171963A true JP2008171963A (en) 2008-07-24

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015162516A (en) * 2014-02-26 2015-09-07 株式会社ジェイデバイス Semiconductor device
US9269647B2 (en) 2014-05-29 2016-02-23 Samsung Electronics Co., Ltd. Semiconductor package having heat dissipating member
WO2022270161A1 (en) * 2021-06-24 2022-12-29 株式会社日立パワーデバイス Semiconductor module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015162516A (en) * 2014-02-26 2015-09-07 株式会社ジェイデバイス Semiconductor device
US10236231B2 (en) 2014-02-26 2019-03-19 J-Devices Corporation Semiconductor device
US9269647B2 (en) 2014-05-29 2016-02-23 Samsung Electronics Co., Ltd. Semiconductor package having heat dissipating member
WO2022270161A1 (en) * 2021-06-24 2022-12-29 株式会社日立パワーデバイス Semiconductor module
JP2023003573A (en) * 2021-06-24 2023-01-17 株式会社 日立パワーデバイス semiconductor module
JP7551571B2 (en) 2021-06-24 2024-09-17 ミネベアパワーデバイス株式会社 Semiconductor Module

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