JP2008171890A - Electrode film for semiconductor devices - Google Patents

Abstract

An electrode film that eliminates the occurrence of spikes is provided.
A back electrode film has an adhesion layer, a diffusion prevention layer, a barrier layer, an electrode body layer and an affinity layer formed in this order on the surface of a collector layer. 15 is connected to the stage by a low melting point metal layer 16. The adhesion layer 11 is an aluminum alloy, and the diffusion prevention layer 12 is a metal including one of Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, Ta, W, and Co, and the electrode body layer 14. Is a Ni alloy, and the barrier layer 13 is a metal nitride of the diffusion preventing layer 12.
[Selection] Figure 2

Description

  The present invention relates to the technical field of electrode films, and particularly relates to a back electrode film of a semiconductor element and a semiconductor device having the back electrode film.

  An IGBT, a diode, or the like that controls high power is composed of a device surface formed on the surface of a silicon substrate and a back electrode formed on the back surface. Further, it is connected and fixed to the wiring board via the back electrode by solder.

  FIG. 3 is a sectional view of a general IGBT (Insulated Gate Bipolar Transistor) 101. In the IGBT 101, an n-type drift layer 132 is formed on a p-type collector layer 131. A p-type back gate region 133 and an n-type emitter region 134 disposed inside the back gate region 133 are formed on the inner surface of the n-type drift layer 132. A region sandwiched between the outer periphery of the back gate region 133 and the outer periphery of the emitter region 134 is a channel region, and a gate insulating film 135 is disposed on the channel region. A gate electrode film 136 is disposed on the gate insulating film 135.

  An interlayer insulating film 137 is disposed on the surface of the gate electrode film 136, and an emitter electrode film 138 is disposed on the surface, the surface of the emitter region 134, and the surface of the back gate region 133. A back electrode film 105 is disposed on the back surface of the collector layer 131.

When the channel region is p-type like the IGBT 101, if a positive voltage is applied to the gate electrode film 136 while applying a negative voltage or a ground voltage to the emitter electrode film 138 and a positive voltage to the back electrode film 105, An n-type inversion layer is formed on the inner surface of the region, the emitter region 134 and the n-type drift layer 132 are connected by the inversion layer, and a current flows. This current flows through the back electrode film 105 in the thickness direction.
In the IGBT 101 as described above, the back electrode film 105 side is fixed on a stage 141 such as a wiring board by a low melting point metal layer 116 such as solder.

  FIG. 4 is a cross-sectional view for explaining the laminated structure of the back electrode film 105. The back electrode film 105 is formed on the surface of the collector layer 131, and has an adhesive layer 111 having good adhesion to the semiconductor, and the back electrode film. 105, an affinity layer 115 having good adhesion to the low melting point metal layer 116, and an electrode body layer 114 located between the adhesion layer 111 and the affinity layer 115 and serving as the body of the back electrode film 105. is doing.

  The adhesion layer 111 is a metal film that forms a compound with a silicon semiconductor (silicide) and has good adhesion, and is mainly composed of aluminum in order to prevent diffusion of silicon atoms into the adhesion layer 111. An aluminum alloy added with 1% by weight is used. For the affinity layer 115, a thin film of silver or gold having high affinity with the low melting point metal is used.

The electrode body layer 114 is made of a low-resistance copper-nickel alloy or nickel-vanadium alloy having good adhesion to metal.
However, in the back electrode film 105, the low melting point metal layer 116 is melted by the heat treatment when the IGBT 101 is fixed to the stage 141. If the molten metal is in contact with the back electrode film 105 for a long time, the affinity layer 115, the electrode body layer 114, and the adhesion layer 111 are partially dissolved in the molten metal, and the molten metal is in contact with the collector layer 131. Then, voids are formed, resulting in a defective product.

  As a countermeasure, for example, as shown in FIG. 5, an electrode film 106 in which a barrier layer 113 having high dissolution resistance is inserted between the adhesion layer 111 and the electrode body layer 114 has been proposed. Even if the main body layer 114 is dissolved, the molten low melting point metal does not come into contact with the adhesion layer 111 or the collector layer 131, so that a defective product is not generated.

The barrier layer 113 needs to have high adhesion to the adhesion layer 111 and be not eroded by solder, and a refractory metal film such as a titanium thin film or a tungsten thin film is used.
However, in the electrode film 106 in which the barrier layer 113 is disposed between the adhesion layer 111 and the electrode body layer 114, the low melting point metal is melted and fixed, and after the heat treatment process for mounting the IGBT 101 on the stage 141, The silicon atoms diffuse into the adhesion layer 111, and aluminum atoms enter the cavities formed by twisting in place of the lost silicon atoms, thereby forming a spike 139a.

In recent solder low-melting-point layers, the alloys used do not contain lead, and since the alloys have a higher melting temperature than solder metals containing lead, the silicon atoms are bonded to the aluminum layer. As diffusion increases, so does spike growth.
D. Prramanik, AN Saxena, "VLSI Metallization Using Aluminum and its Alloys", Solid State Technology, January, p127 (1983)

  Prevent spikes.

In order to solve the above-described problems, the present invention provides an electrode film formed on a silicon substrate, wherein the electrode film is disposed on a surface of the first layer that is in close contact with the silicon substrate and the surface of the first layer. A second layer; a third layer disposed on a surface of the second layer; and a fourth layer disposed on a surface of the third layer, wherein the first layer is aluminum mainly composed of aluminum. The second layer is a metal including one of Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, Ta, W, and Co, and the fourth layer is mainly composed of Ni. The third layer is an electrode film that is a nitride thin film of the second layer metal.
In addition, the present invention is a semiconductor device in which an electrode film is formed.

  The occurrence of spikes is suppressed and malfunction of the semiconductor device is prevented.

  Reference numeral 1 in FIG. 1 is an IGBT (insulated gate bipolar transistor element) of the present invention, and a back electrode film 5 formed on the back surface of the semiconductor layer 30 is formed on a stage 41 such as a lead frame by a low melting point metal layer 16. It is fixed.

  The structure of the IGBT 1 will be described. If one of the p-type and n-type is the first conductivity type and the other is the second conductivity type, in this IGBT 1, the semiconductor layer 30 includes a collector layer 31 of the second conductivity type (here p-type), A drift layer 32 of the first conductivity type (here, n-type) opposite to the collector layer 31 disposed on the collector layer 31 is provided. The collector layer 31 and the drift layer 32 form a pn junction.

One or a plurality of back gate regions 33 having the same conductivity type as that of the collector layer are formed in the drift layer 32, and the first conductivity type emitter region having a high impurity concentration is formed in each back gate region 33. 34 are formed.
Reference numeral 39 denotes a channel region sandwiched between the outer periphery of the back gate region 33 and the outer periphery of the emitter region 34.

  A gate insulating film 35 is disposed on the channel region 39, and a gate electrode film 36 is disposed on the gate insulating film 35. The end portions of the gate insulating film 35 and the gate electrode film 36 are located on the end portion of the surface of the emitter region 34 and the end portion of the surface of the drift layer 32, and the portion therebetween is disposed on the channel region 39.

An interlayer insulating film 37 is disposed on the surface of the gate electrode film 36.
At least part of the surfaces of the emitter region 34 and the back gate region 33 are exposed, and an emitter electrode film 38 is formed on the exposed surfaces. The emitter electrode film 38 and the gate electrode film 36 are insulated by an interlayer insulating film 37.

  In the case of an IGBT or MOSFET, when the first conductivity type is n-type and the second conductivity type is p-type, a positive voltage is applied to the gate electrode film 36 while applying a negative voltage to the emitter electrode film 38 and a positive voltage to the back electrode film 5. Is applied, an inversion layer of the first conductivity type is formed on the inner surface of the channel region 39, and the emitter region 34 and the drift layer 32 are connected by the inversion layer. As a result, a current flows from the back electrode film 5 toward the emitter electrode film 38 through the drift layer 32 and the emitter region 34. When the first conductivity type is p-type and the second conductivity type is n-type, an inversion layer is formed in the same manner when a voltage having the opposite polarity is applied to the back electrode film 5 from the emitter electrode film 38. Current flows.

In this IGBT 1, in the back electrode film 5, as shown in FIG. 2, a diffusion preventing layer 12 is disposed between the adhesion layer 11 and the barrier layer 13.
That is, the back electrode film 5 has an adhesion layer 11 formed on the surface of the collector layer 31, the diffusion prevention layer 12 is formed on the surface of the adhesion layer 11, and the barrier layer 13 is composed of the diffusion prevention layer 12. Is formed on the surface. An electrode body layer 14 and an affinity layer 15 are formed on the surface of the barrier layer 13.

  The adhesion layer 11 is a metal film mainly composed of aluminum having good adhesion to the material of the semiconductor layer 30, here, silicon, and an aluminum alloy film to which 1 wt% of silicon is added is used. A refractory metal nitride film is used for the diffusion prevention layer 12.

  The barrier layer 13 is a refractory metal thin film made of the same refractory metal as the diffusion prevention layer 12, and the electrode body layer 14 has good adhesion to the metal and is made of a low resistance copper nickel alloy or nickel vanadium alloy. A thin film is used. For the affinity layer 15, silver, gold, or an alloy thin film thereof having high affinity for the low melting point metal is used.

  For example, the adhesion layer 11 has a thickness of 200 nm, the diffusion prevention layer 12 has a thickness of 5 to 100 nm of titanium nitride (TiN) thin film, the barrier layer 13 has a thickness of 200 nm of titanium metal, and the electrode body layer 14 has a thickness of 700 nm of nickel metal. The affinity layer 15 is a 100 nm gold thin film.

  The low melting point metal layer 16 is composed of a low melting point material of Ag—Sn alloy containing no lead, and the low melting point material is disposed between the metal stage 41 and the back electrode film 5 and melted by heat treatment at 350 ° C.・ Fixed and thinned. The back electrode film 5 is fixed to the stage 41 by a low melting point metal layer 16.

  The process of forming the back electrode film 5 will be described. First, a large number of IGBTs with the collector layer 31 exposed are formed, the substrate is carried into a vacuum chamber, and an adhesion layer is formed on the surface of the collector layer 31 by sputtering. 11 is then moved to another vacuum chamber without being exposed to the atmosphere, nitrogen gas and sputtering gas (for example, argon gas) are introduced into the vacuum chamber using metal titanium as a target, and nitrogen gas is added. A target of titanium metal is sputtered with the sputtering gas thus formed to form a diffusion prevention layer 12 made of a titanium nitride thin film on the surface of the adhesion layer 11.

Then, the introduction of nitrogen gas is stopped in the same vacuum chamber, the same metal titanium target is sputtered by sputtering gas not containing nitrogen gas, and the barrier layer 13 made of a metal titanium thin film is formed on the surface of the diffusion prevention layer 12. . The electrode body layer 14 and the affinity layer 15 are formed by sputtering or vapor deposition in another vacuum chamber.
The substrate on which the back electrode film 5 is formed is taken out of the vacuum chamber, divided by dicing, and the IGBT 1 is separated.

Next, the surface state of the semiconductor layer 30 of the IGBT 1 of the present invention will be described.
First, the IGBT 1 on which the back electrode film 5 is formed is subjected to the same heat treatment as mounting on the stage 41 with the low melting point metal layer 16 to peel off the back electrode film 5, and the surface of the semiconductor layer 30 (the surface of the collector layer 31). ) Was observed.

  6A to 6D show the observation results, which are electron micrographs of the collector layer 31 surface. The film thicknesses of the diffusion prevention film 12 are a: 5 nm, b: 20 nm, c: 50 nm, and d: 100 nm, respectively, and it can be seen that no spike occurs in all cases.

  7A to 7D are comparative examples. FIG. 7A shows the case where only the adhesion layer 11 is formed on the surface of the semiconductor layer 30. FIG. 7B shows the case where the adhesion layer 11 and the barrier layer 13 are formed. When the adhesion layer 11, the barrier layer 13, and the electrode main body layer 14 are formed, FIG. D: when the adhesion layer 11, the barrier layer 13, the electrode main body layer 14, and the affinity layer 15 are formed. The material of each layer 11, 13-15 is the same as the said Example.

  In FIG. 7a where only the adhesion layer 11 is formed, no spike is observed, but as observed in FIGS. 7b to 7d, spikes are generated when the barrier layer 13 is formed. Thereby, it turns out that the barrier layer 13 is a cause of spike generation.

Sectional drawing for demonstrating an example of IGBT of this invention Sectional drawing for demonstrating the electrode film Sectional drawing for demonstrating general IGBT Example of conventional electrode film Another example of conventional electrode film a to d: Electron micrographs showing the surface state of the semiconductor layer when the electrode film of the present invention is used. ad: Electron micrographs showing the surface states of the semiconductor layers of the comparative examples

Explanation of symbols

1 ... IGBT
5 ... Back electrode film 11 ... Adhesion layer 12 ... Diffusion prevention layer 13 ... Barrier layer 14 ... Electrode body layer 15 ... Affinity layer 16 ... Low melting point metal layer 31 ... Collector layer 32 ... Drift layer 33 …… Back gate region 34 …… Emitter region 35 …… Gate insulating film 36 …… Gate electrode film 39 …… Channel region

Claims (2)

An electrode film formed on a silicon substrate,
The electrode film includes a first layer adhered to the silicon substrate,
A second layer disposed on a surface of the first layer;
A third layer disposed on the surface of the second layer;
A fourth layer disposed on the surface of the third layer,
The first layer is an aluminum alloy mainly composed of aluminum,
The second layer is a metal including one of Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, Ta, W, and Co,
The fourth layer is a Ni alloy containing Ni as a main component,
The electrode layer, wherein the third layer is a nitride thin film of the second layer metal.   A semiconductor device having the electrode film according to claim 1 formed thereon.