JP2008165090A - Method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving a plasma display panel by which a high definition picture can be achieved. <P>SOLUTION: The method of driving the plasma display panel is provided, wherein the plasma display panel has: a front substrate and a back substrate opposed to each other across a discharge space; a plurality of row electrodes which are disposed side by side on an internal surface of the front substrate, each of the adjacent paired electrodes constituting a scan line; and a plurality of column electrodes which are disposed side by side on an internal surface of the back substrate in a direction crossing the row electrodes and each constitute cells at positions of intersection with scan lines. The method includes a sustain step of applying one or more sustain pulses to each scan line to perform a line sequential scan for a sustain discharge and applying address potentials to the column electrodes for each of the scan lines based upon display data, and in the sustain step, a blank period where no potential is applied is provided before the sustain pulses are applied for each of the scan lines. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for driving a surface discharge AC plasma display panel.

  FIG. 1 shows a panel structure of a conventional plasma display panel, and is a front view schematically showing the relationship between row electrode pairs X and Y and barrier ribs 6. (See Patent Document 1).

  The plasma display panel of FIG. 1 is formed by laminating a back substrate and a front substrate facing each other through a discharge space in parallel. On the front side of the rear substrate, a plurality of column electrodes (indicated by broken lines) each extending in the column direction and arranged in the row direction are provided, and a column electrode protection layer is formed thereon. A plurality of row electrode pairs X and Y, each extending in the row direction and arranged in parallel in the column direction, are provided on the back side of the front substrate.

  As shown in FIG. 1, on the column electrode protection layer of the back substrate, a vertical barrier rib extending in the column direction and a horizontal barrier rib extending in the row direction are coupled to each other at positions between the column electrodes arranged in the row direction. A partition wall 6 formed in a substantially lattice shape (well shape) is formed.

A cell D is defined as a rectangular chamber by the substantially lattice-shaped partition 6 so that a unit light-emitting portion is formed at the intersection of the column electrode and the row electrode pair. A T-shaped transparent electrode portion Ka protrudes in the column direction from each of the row electrode pairs X and Y.
JP2002-197981

  The plasma display panel has excellent performance as a large thin display. Currently, large panels of 30 inches or more are manufactured in the market.

  In recent years, it has been studied to use a plasma display panel not only for a conventional large panel but also for a medium-sized, full HD class high definition display of about 26 inches.

  However, when the size of the cell is reduced, for example, when the size (passage) becomes 100 μm or less, the cell D becomes too narrow, the discharge space is reduced, and the light emission efficiency is significantly reduced. was there. This is because if the size of the unit cell is reduced, the positive column of the plasma (plasma in the space between the cathode and the anode) cannot be taken sufficiently large. As a result, the luminance and the luminous efficiency are reduced.

  The present invention has been made to solve the problems in the conventional surface discharge type AC plasma display panel as described above. Problems to be solved by the present invention include reduction in luminance and error in cells. An example is to provide a method for driving a plasma display panel that can prevent discharge and realize high definition of the screen.

  Further, in the plasma display panel, the image display is not performed by the address display separation (ADS) subframe method, but in the unit display period (one field, one frame) of the input image signal, the sustain between the row electrode pairs constituting the scanning line is maintained. An example is to provide a driving method in which an address potential is applied to each column electrode in accordance with display data at the same time that the discharge is line-sequentially scanned.

  In order to achieve such an object, a plasma display panel according to the present invention has the following configuration, and features thereof are as follows.

The driving method of the plasma display panel according to claim 1, wherein a front substrate and a rear substrate facing each other through a discharge space, and a plurality of scanning lines that are arranged in parallel on the inner surface of the front substrate and constitute adjacent pairs. Driving a plasma display panel comprising: a row electrode; and a plurality of column electrodes arranged in parallel in a direction intersecting the row electrode on the inner surface of the rear substrate and each constituting a cell at the intersection with the scanning line A method,
A sustain step of applying one or more sustain pulses for each scan line to perform a line sequential scan of a sustain discharge and applying an address potential to a column electrode based on display data for each scan line;
In the sustain step, a blank period in which no potential is applied is provided before the sustain pulse is applied to each scanning line. The blank period set before applying the sustain pulse can prevent erroneous discharge and stabilize the operation.

  In the blank period, the potential of the column electrode reaching the address potential may be changed or maintained. Since a voltage is applied to the column electrode during the blank period set before the sustain pulse is applied, erroneous discharge is prevented and the operation is stabilized.

  Before the blank period, a preliminary erasing discharge period in which an erasing pulse for erasing wall charges is applied for each scanning line may be provided.

  The potential of the column electrode in the preliminary erasure discharge period may be set according to the intensity of the sustain discharge immediately before the preliminary erasure discharge period. The column electrode potential during the erasing discharge period is set during a blank period provided before that, and the column electrode potential at this time is determined by the intensity of the sustain discharge during the immediately preceding sustain period, that is, the luminance level. Thereby, the erasing discharge can be completed and the subsequent sustain discharge can be stabilized.

  A second blank period may be provided before the preliminary erasing discharge period, and the column electrode potential reaching the address potential may change during the second blank period.

  Before the first sustaining step every frame period, a reset step may be included in which a reset pulse is applied to each scanning line to form wall charges in the cells.

  A third blank period may be provided before the reset step, and the potential of the column electrode reaching the address potential may change during the third blank period.

  After the sustaining step for all the lines is completed, a main erasing discharge step for applying an erasing pulse for equalizing wall charges all at once in the scanning lines may be included.

BEST MODE FOR CARRYING OUT THE INVENTION

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is an exploded perspective view disassembled into a front substrate and a rear substrate for explaining the configuration of the main body 120 of the plasma display panel.

  As shown in FIG. 2, a front substrate in which a plurality of row electrodes X and Y are made of glass on the rear surface of the front substrate 1 made of glass as a display surface (the inner surface facing the rear substrate 4 spaced apart in parallel). 1 are arranged in parallel so as to extend in the row direction (left-right direction in FIG. 2).

  The row electrode X has a strip-like common bus electrode portion Kb made of a metal film extending in the row direction of the front substrate 1, and is arranged in parallel at equal intervals along the common bus electrode portion Kb. With a T-shaped transparent electrode portion Ka (a discharge electrode that protrudes in the column direction from the bus electrode portion) made of a transparent conductive film such as ITO (indium tin oxide) connected to the common bus electrode portion Kb. It is configured.

  Similarly, the row electrode Y has a strip-like common bus electrode portion Kb made of a metal film extending in the row direction of the front substrate 1, and a narrow base end arranged in parallel at equal intervals along the common bus electrode portion Kb. The portion is constituted by a T-shaped transparent electrode portion Ka (discharge electrode) made of a transparent conductive film such as ITO connected to the common bus electrode portion Kb.

  The row electrodes X and Y are alternately arranged in the column direction of the front substrate 1 (vertical direction in FIG. 2), and transparent electrode portions Ka arranged in parallel along the two common bus electrode portions Kb are paired with each other. The wide apexes of the transparent electrode portions Ka are opposed to each other via a discharge gap having a required width. In the row electrode Y, the transparent electrode portions Ka are arranged in high density so that the row electrode adjacent to the opposite side of the row electrode X also forms a row electrode pair. That is, the transparent electrode portions Ka are provided on both sides in the column direction of the row electrodes.

  As shown in FIG. 2, a dielectric layer 2 is formed on the row electrode pairs X and Y on the back side of the front substrate 1 so as to cover them.

  On the back side of the dielectric layer 2, a strip-like raised dielectric layer 2 </ b> A that protrudes from the dielectric layer 2 to the discharge space on the back side is formed in parallel on the bus electrode portion Kb. A protective layer 3 made of MgO is formed on the back side of the dielectric layer 2 and the raised dielectric layer 2A.

  On the other hand, on the lower side of the surface (inner surface) facing the front substrate 1 of the rear substrate 4 arranged in parallel with the front substrate 1 through the discharge space, column electrodes C (address electrodes) are respectively connected to the row electrode pairs X. , Y are arranged in parallel at equal intervals so as to extend in the column direction at positions facing the paired transparent electrode portions Ka.

  A column electrode protective layer 5 (dielectric layer) is further formed on the inner surface of the rear substrate 4 on the display side to cover the column electrode C. A partition wall 6 formed in a lattice shape (well shape) is formed on the protective layer 5. In other words, the discharge space is partitioned by the barrier ribs 6, and a plurality of cells D that are aligned in the row and column directions are defined.

  On each inner surface of the partition wall 6 facing each cell D and on the surface of the column electrode protective layer 5, a phosphor layer 7 that is excited by discharge and emits light is formed so as to cover these surfaces. For example, in a full color display panel, each cell D on the back substrate is divided into phosphor layers of three primary colors of red (R), green (G), and blue (B), and the discharge area of the cell for each color is divided. .

  A discharge gas containing xenon gas Xe is sealed in the discharge space of each cell D between the front substrate 1 and the back substrate 4.

  FIG. 3 is a schematic block diagram showing a configuration example of the plasma display panel device according to the present embodiment. The display device includes various drive devices that drive the panel body 120 of the plasma display panel, a column electrode drive circuit 212, a row electrode drive circuit 210, and the like.

  The panel body 120 includes odd-numbered row electrodes X1 to Xn and even-numbered row electrodes Y1 to Yn and column electrodes C1 to Cm arranged in a matrix. The column electrodes C1 to Cm are connected to the column electrode drive circuit 212, and the row electrodes X1 to Xn and Y1 to Yn are connected to the row electrode drive circuit 210. A cell Dij (unit light emitting portion) is formed at the intersection of one of the column electrodes C1 to Cm and a pair of adjacent odd and even row electrodes. For each cell, a row electrode pair is provided with the above-described opposed discharge electrodes, although not shown. That is, each of a pair of adjacent row electrode pairs X and Y constitutes a scanning line.

  The row electrode drive circuit 210 applies a drive pulse such as a sustain pulse to the adjacent row electrode pair X and Y, scans the row electrode pair X and Y sequentially in line display, and in synchronization with this line display scan, The electrode drive circuit 212 generates pixel data pulses (pulses having address potentials such as a discharge suppression potential, a reference potential, and a discharge promotion potential) corresponding to each pixel data supplied from the output processing circuit 206 to Applied to the column electrodes C1 to Cm. Although not shown, the row electrode drive circuit 210 sends an X driver that generates a first sustain pulse to the row electrodes X1 to Xn, and a second sustain pulse that has an opposite phase to the first sustain pulse to the row electrodes Y1 to Yn. Y driver to be generated is included. The column electrode drive circuit 212 changes the potential of the column electrode from a reference potential, for example, the ground potential (0 V), to a large potential in the negative polarity direction (discharge suppression potential) or a large potential in the positive polarity direction (discharge promotion potential). A pixel data pulse (address potential) is generated.

  Thus, in the plasma display panel, display driving is performed by supplying an address potential to the column electrodes C1 to Cm on the back substrate side in synchronization with the line sequential scanning of the row electrode pairs X and Y on the front substrate side. The discharge current of the light emitting unit is adjusted for each group of cells in one row of row electrode pairs. When an address potential corresponding to an image signal is applied to each column electrode while the sustain pulse is applied to the row electrode, sampling is performed and the gradation (brightness level of light and dark) of the light emitting unit can be controlled. For example, in a full color display panel, RGB image signals are sequentially supplied to the corresponding cells, and an image is displayed according to the image signal by applying a discharge suppression potential to a column electrode of a color that is not displayed.

  In the plasma display panel apparatus of FIG. 3, the sync separation circuit 201 extracts horizontal and vertical sync signals from the supplied input video signal and supplies them to the timing pulse generation circuit 202. The timing pulse generation circuit 202 generates an extracted synchronization signal timing pulse based on the extracted horizontal and vertical synchronization signals, and outputs the extracted synchronization signal timing pulse to each of the A / D converter 203, the memory control circuit 205, and the read timing signal generation circuit 207. To supply. The A / D converter 203 converts the input video signal into digital pixel data corresponding to each pixel in synchronization with the extraction synchronization signal timing pulse, and supplies this to the frame memory 204. The memory control circuit 205 supplies the frame memory 204 with a write signal and a read signal synchronized with the extraction synchronization signal timing pulse. The frame memory 204 sequentially captures each pixel data supplied from the A / D converter 203 according to the write signal. Further, the frame memory 204 sequentially reads out the pixel data stored in the frame memory 204 according to the read signal and supplies it to the output processing circuit 206 at the next stage. The read timing signal generation circuit 207 generates various timing signals for controlling the discharge light emission operation and supplies them to the row electrode drive circuit 210 and the output processing circuit 206, respectively. The output processing circuit 206 supplies the pixel data supplied from the frame memory 204 to the column electrode drive circuit 212 in synchronization with the timing signal from the readout timing signal generation circuit 207.

  Further, the row electrode drive circuit 210 is used to regenerate a pre-discharge pulse for performing pre-discharge and charged particles in addition to a sustain pulse for maintaining discharge between all the row electrode pairs of the panel body 120. It is possible to generate a priming pulse, a reset pulse for stabilizing the discharge at the time of data writing, and an erasing pulse for stopping the sustain light emission discharge. The row electrode drive circuit 210 applies these pulses to the row electrodes X1 to Xn and Y1 to Yn of the panel body 120 at timings according to various timing signals supplied from the read timing signal generation circuit 207.

  Here, it should be noted that the row electrode driving circuit 210 applies a sustain pulse train having an antiphase of about 1 to 30 pulses to each pair of adjacent row electrodes X and Y to maintain discharge, and performs line sequential. That is, it has a function of performing scanning, and the column electrode driving circuit 212 has a function of controlling discharge by selectively applying an address potential to the column electrodes.

  Next, a method for driving the plasma display panel of this embodiment will be described.

  FIG. 4 shows a timing chart of drive pulse waveforms applied to the electrodes in one frame period displayed periodically and repeatedly in the surface discharge AC type plasma display panel device of this embodiment. The row electrodes are labeled X1, Y1, X2, Y2,... Xn, Yn in order from the top. The column electrodes are sequentially labeled C1... Cm below the row electrodes.

  Each frame that is repeatedly displayed periodically includes a reset discharge period (reset step), a sustain discharge period (sustain step), and an erase discharge period (erase discharge step). The sustain discharge period (sustain step) is composed of a predetermined number (row electrode number-1) of row discharge periods (row discharge steps).

  First, a sustain discharge period (sustain step) in which a sustain pulse is generated by line sequential scanning by applying a sustain pulse to a pair of row electrodes which is a main part of line sequential display will be described. As shown in the figure, the sustain pulse waveforms are applied to the row electrode pairs so that the phases thereof are shifted from each other by 180 degrees.

  In a set of row electrode pairs (scanning lines), when a pulse is applied only to one of the row electrodes, no discharge occurs. When anti-phase pulses are applied to both synchronously, discharge occurs only during that period. For example, focusing on the row electrode pair X1, Y1, that is, the first and second row electrodes, when a positive / negative pulse is applied to the row electrode X1, a negative / positive pulse is applied to the row electrode Y1 almost simultaneously. As a result, the first discharge is generated at the timing when the negative polarity pulse of the row electrode Y falls to a predetermined value. In accordance with this, by applying a predetermined image signal to each of the column electrodes C1 to Cm, the cells of the first scanning line emit light with a predetermined luminance distribution (first row discharge period).

  After that, since the row electrode X1 becomes the ground potential (0 V), the light is extinguished in the cell of the first scanning line, but 2 in the row electrode pair of the row electrode Y1 and the next row electrode X2 to which the positive / negative pulse is applied. A second discharge potential is generated, and by applying a predetermined image signal to each of the column electrodes C1 to Cm, the cells of the second scanning line emit light with a predetermined luminance distribution (second row discharge). period). Next, similarly, the cells of the third scanning line of the row electrode pair X2, Y2 emit light (third row discharge period). Similarly, light is emitted sequentially to the cells of the nth scanning line of the row electrode pair Xn, Yn (nth row discharge period). Note that both the row electrode X and the row electrode Y straddle (shared) between adjacent row electrode pairs. However, only one side of the row electrode is actually discharged by this driving, and scanning can be sequentially performed. It becomes. Accordingly, since a pair of row electrode pairs corresponds to one scanning line, for example, in the case of an input image signal having a frame size of 1920 × 1080 dots in the case of monochrome display, 1920 column electrodes and 1081 A plasma display panel can be constituted by the row electrodes.

  In other words, the sustain operation is replaced with the scan operation in the conventional ADS driving method of the plasma display panel. In the conventional driving method of the plasma display panel, the scan pulse is only once. However, the sustain pulse of the present embodiment has a pulse number of 1 or more and continues sequentially for each display period of one scan line. Discharging is performed line-sequentially and line-sequential display is performed.

  Further, the brightness adjustment is controlled by the magnitude of the column electrode potential (address potential) during the sustain discharge period. If the column electrode potential is large in the negative direction, even if the sustain potential is the same, the electron intrusion region is suppressed, the discharge current and the light emission efficiency are reduced, and even if the column electrode potential is large in the positive direction, this time the ions enter. The region is suppressed, and the discharge current and the light emission efficiency are reduced. By adjusting the luminance for each RGB, the hue can be adjusted.

  Here, the timing of setting the column electrode potential during discharge in the sustain discharge period will be described with reference to FIGS.

  In the driving method shown in FIG. 4, there is little time margin before the surface discharge light emission in the second row after the surface discharge light emission in the first row. For this reason, a voltage is applied stepwise to the column electrode, and there is a possibility that an erroneous discharge between the row electrode and the column electrode, which is originally unnecessary, may occur. This erroneous discharge adversely affects the subsequent sustain discharge. The configuration for preventing this is the embodiment shown in FIGS. The figure shows a detailed timing chart of the sustain discharge period (sustain step) of the drive sequence. In the row electrode pair, the columns of positive and negative sustain pulses So1 to So8 applied to the odd row electrodes X1 to Xn and the columns of positive and negative sustain pulses Se1 to Se8 applied to the even row electrodes Y1 to Yn are mutually connected. It is applied so as to have an opposite phase.

  In the sustain discharge period shown in FIG. 5, a first blank period Tb1 in which no potential is applied is set for each sustain pulse train (row discharge period), and the column electrode potential V (B) is set in the first blank period Tb1. (B means a predetermined luminance level) is changed or maintained according to the luminance of the screen.

  Since the first blank period Tb1 is set to a length sufficient to set the column electrode potential V (B), the above-described erroneous discharge does not occur.

  In another embodiment shown in FIG. 6, a preliminary erasing discharge period Tstp is inserted before the first blank period Tb1 shown in FIG. In the preliminary erasing discharge period Tstp, one or more erasing pulses, which are weak pulses for erasing wall charges during the sustaining discharge and have a pulse amplitude and a pulse width lower than the sustaining pulse, are applied. Further, a second blank period Tb2 in which a potential different from the first blank period Tb1 is not applied is inserted before the preliminary erasing discharge period Tstp, and the potential of the column electrode (in the second blank period Tb2 ( Address discharge stop voltage Vstpadr (B)) is set. If the driving method of this embodiment is used, the possibility of erroneous discharge at the time of shifting the scanning line emission is further reduced. Note that the second blank period Tb2 may be omitted, and the preliminary erasure discharge period Tstp and the first blank period Tb1 may be inserted for each sustain pulse train in the sustain discharge period with the column electrode potential set to a predetermined value.

  In the embodiment, for example, the first blank period Tb1 is set to 0.5 μs to 10 μs, and the second blank period Tb2 is set to 0 μs to 10 μs. The preliminary erasing discharge period Tstp can be set to 0 μs to 10 μs.

  As shown in FIG. 6, an erase pulse voltage is applied to the row electrode during the preliminary erase discharge period Tstp. For example, the erase pulse voltage Vstpo to the odd-numbered row electrodes X1 to Xn is −200 to + 300V, and the erase pulse voltage Vstpe to the even-numbered row electrodes Y1 to Yn is +200 to −300V.

  Further, as shown in FIG. 6, the address discharge stop voltage Vstpadr (B) is applied to the column electrode during the preliminary erasing discharge period Tstp, but the preliminary erasing discharge period Tstp for erasing the wall charge at the time of the sustain discharge. The address discharge stop voltage Vstpadr (B) is preferably set in accordance with the intensity of the last sustain discharge (depending on the luminance level B). This is because it is necessary to adjust the intensity of the erasing discharge for each cell when the discharge luminescence intensity is different for each cell.

  In the embodiment, the column electrode potential can be automatically set in accordance with the luminance by using a method such as a linear interpolation method (a method in which levels are connected by a linear function to make the entire level change smoothly). Thereby, high stability of discharge light emission for each frame period can be obtained.

  Here, a procedure for setting the address discharge stop voltage Vstpadr (B) corresponding to an arbitrary luminance level by the linear interpolation method is shown below.

  First, the luminance B is divided into, for example, 16 levels and is set to B0, B1, B2,.

  Address discharge stop voltage Vstpadr (Bi) (where i = 0, 1, 2,... 15) corresponding to each luminance is set. When the luminance is B0, the address discharge stop voltage Vstpadr (B0), when the luminance is B1, the address discharge stop voltage Vstpadr (B1), and so on. The voltage of Vstpadr (Bi) is in the range of approximately -200 to + 300V.

  Here, if an arbitrary luminance is B, the address discharge stop voltage Vstpadr (B) is calculated by the following calculation formula.

(Equation 1)
Vstpadr (B) = Vstpadr (Bi) + (Vstpadr (B (i + 1))-Vstpadr (Bi)) (B-Bi) / (B (i + 1) -Bi)

Next, FIG. 7 shows a detailed timing chart of reset discharge (reset step) which is the first step of the drive sequence. During the reset discharge period (reset step) at the beginning of the frame period, rectangular reset pulses (X1, X2,... Xn) and reset pulses (Y1, Y2,. In addition to applying Yn), a predetermined potential is applied simultaneously to the column electrodes C1 to Cm, and wall charges are formed in all cells by reset discharge to perform initialization. The column electrode potential at the time of reset discharge is also set by the above-described linear interpolation method according to the luminance level for each cell at the time of sustain discharge of the corresponding row, whereby the stability of discharge light emission repeated for each frame can be improved.
In FIG. 7, the second reset pulse is applied after the rectangular and gradually changing reverse polarity reset pulse, but the second reset pulse may be omitted as shown in FIG. 4.

  The reset discharge period is 10 μs to 1000 μs, the even lines are all in the same waveform and the voltage is about −250 to +400 V, and the odd lines are preferably all in the same waveform and the voltage is about −400 to +150 V.

  The column electrode potential V (Adr) in the reset discharge period is about −350 to +250 V, and the third blank period Tb3 is preferably set to 0.5 μs to 10 μs.

  Next, FIG. 8 shows a detailed timing chart of the main erase discharge step which is the final step of the drive sequence.

  In FIG. 8, after the end of the sustain discharge of all the lines (after the nth row discharge), all the lines are erased simultaneously (main erasing discharge period). At this time, a simultaneous erasing pulse different from the preliminary erasing pulse in the sustaining step shown in FIG. 8 is applied to the column electrodes to make the wall charge amount at the time of reset discharge substantially uniform.

  The erase pulse length Tstp in the main erase discharge period is 0.5 μs to 20 μs, the erase pulse voltage of the odd-numbered row electrodes X1 to Xn is V (STPo) = + 300 to −300 V, and the erase pulse of the even-numbered row electrodes Y1 to Yn. Preferably, the voltage is V (STPe) = − 300 to + 300V, the pulse length of the column electrode is the same as Tstp, and the applied voltage VAdr (STP) to the column electrode is preferably set to be −300V to + 200V. .

  As described above, the above-described embodiment solves the problem of deterioration of luminous efficiency and discharge instability because the discharge space is narrowed by reducing the cell size for the purpose of high definition of the conventional plasma display panel. it can. According to the above embodiment, a high-performance plasma display panel corresponding to high definition of the screen can be provided.

It is a front view which shows typically the relationship between the row electrode pair and partition for demonstrating the conventional surface discharge alternating current type plasma display panel. 1 is an exploded perspective view of a front substrate and a rear substrate in order to explain a surface discharge AC type plasma display panel according to an embodiment of the present invention. It is a block diagram which shows the structure of the display apparatus of the surface discharge alternating current type plasma display panel of embodiment by this invention. FIG. 3 is a timing diagram of various applied pulses showing an outline of a method for driving a surface discharge AC type plasma display panel according to an embodiment of the present invention. FIG. 5 is a timing diagram illustrating the timing of an applied sustain pulse, illustrating an embodiment of a surface discharge AC type plasma display panel driving method according to an embodiment of the present invention. FIG. 10 is a timing diagram illustrating the timing of an applied sustain pulse, illustrating an embodiment of a surface discharge AC type plasma display panel driving method according to another embodiment of the present invention. It is a timing diagram explaining the pulse timing of the applied reset step showing the embodiment of the driving method of the surface discharge AC type plasma display panel of another embodiment according to the present invention. FIG. 6 is a timing diagram illustrating pulse timings of an applied erasing discharge step showing an embodiment of a surface discharge AC type plasma display panel driving method according to another embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Front substrate 2 Dielectric layer 2A Raised dielectric layer 3 Protective layer 4 Back substrate 5 Column electrode protective layer 7 Phosphor layer 120 Panel body 201 Synchronous separation circuit 202 Timing pulse generation circuit 203 A / D converter 204 Frame memory 205 Memory Control circuit 206 Output processing circuit 207 Read timing signal generation circuit 210 Row electrode drive circuit 212 Column electrode drive circuit C Column electrode D Cell X, Y Row electrode Kb Common bus electrode part Ka Transparent electrode part

Claims (8)

A front substrate and a rear substrate facing each other through a discharge space; a plurality of row electrodes arranged in parallel on the inner surface of the front substrate and constituting scanning lines in pairs; and the row on the inner surface of the rear substrate. A plurality of column electrodes arranged in parallel in a direction intersecting with the electrodes and constituting cells at intersections with the scanning lines, respectively,
A sustain step of applying one or more sustain pulses to each scan line to perform a line sequential scan of sustain discharge, and applying an address potential to the column electrode based on display data for each scan line;
In the sustaining step, a blank period in which no potential is applied is provided before applying the sustaining pulse for each scanning line.   2. The method of driving a plasma display panel according to claim 1, wherein the column electrode potential reaching the address potential is changed or maintained during the blank period.   3. The method of driving a plasma display panel according to claim 2, wherein a preliminary erasing discharge period in which an erasing pulse for erasing wall charges is applied for each scanning line is provided before the blank period.   4. The method of driving a plasma display panel according to claim 3, wherein the potential of the column electrode in the preliminary erasure discharge period is in accordance with the intensity of the sustain discharge immediately before the preliminary erasure discharge period.   5. The method according to claim 3, wherein a second blank period is provided before the preliminary erasing discharge period, and a potential of the column electrode that reaches the address potential changes during the second blank period. 6. Driving method of plasma display panel.   6. The method according to claim 1, further comprising a reset step of forming a wall charge in the cell by applying a reset pulse for each scanning line before the first sustain step for each frame period. Driving method of the plasma display panel.   7. The plasma display panel according to claim 6, wherein a third blank period is provided before the reset step, and the potential of the column electrode reaching the address potential changes during the third blank period. Driving method.   8. The main erasing discharge step of applying an erasing pulse for making wall charges uniform all at once after the sustaining step for all the lines is completed. Driving method of the plasma display panel.

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